CN103176945A - Field programmable gate array device dead-weight configuration device and method - Google Patents
Field programmable gate array device dead-weight configuration device and method Download PDFInfo
- Publication number
- CN103176945A CN103176945A CN2011104396288A CN201110439628A CN103176945A CN 103176945 A CN103176945 A CN 103176945A CN 2011104396288 A CN2011104396288 A CN 2011104396288A CN 201110439628 A CN201110439628 A CN 201110439628A CN 103176945 A CN103176945 A CN 103176945A
- Authority
- CN
- China
- Prior art keywords
- output
- counter
- level signal
- output terminal
- input end
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Abstract
The invention relates to a field programmable gate array (FPGA) device dead-weight configuration device and method. The FPGA device dead-weight configuration device comprises a self configuration circuit which is arranged in a FPGA device and a signal processing circuit which is arranged at the outer portion of the FPGA device. The self configuration circuit comprises a first counter, a second counter, a third counter and a detection circuit, wherein the first counter, the second counter and the third counter are used for receiving the same clock pulse signal to fix time and a low level signal is output when the fixed time reaches a preset value. One of the counters is detected whether the one is different from the other two in output by the detection circuit, the low level signal is output when the one is different from the other two in the output, and a level signal the same with the first counter, the second counter and the third counter is output when the one is the same with the other two in the output. An output end of the detection circuit is connected with the signal processing circuit which transmits the low level signal output by the detection circuit to a reconfiguration pin and controls the reconfiguration pin to keep time of low level above preset time. The FPGA device dead-weight configuration device and method has the advantages of being few in needed external devices, simple in structure and few in occupied printed circuit board (PCB) resources.
Description
Technical field
The application relates to the space apparatus engineering field, relates in particular to a kind of deadweight inking device and method of FPGA.
Background technology
Along with the development of spationautics and the demand of every field, increasing satellite and spacecraft come into operation.Function at the rail spacecraft becomes increasingly complex, this just needs complicated logic to realize more function, extensive field programmable gate array (Field-Programmable Gate Array, the FPGA device) be more satisfactory device, particularly SRAM (Static Random Access Memory, static RAM) but the advantages such as type FPGA device has that scale is large, the strong overprogram of function.At present, SRAM type FPGA device is widely used at commercial field.due to various particles being arranged in space environment, proton for example, electronics, the α particle, heavy ion, gamma-rays etc., multiple single particle effect (Single Event Effect will occur in these particle bombardments to SRAM type FPGA device, SEE), single-particle inversion (Single Event Upset for example, SEU), single event function interrupt (Single Event Functional Interrupt, SEFI), total dose effect, locking single particle (Single Event Functional Latchup, SEL), single event burnout (Single Event Burnout, SEB), displacement damage, single-particle instantaneous disturbance (Single Event Transient, SET) etc.These single particle effects directly affect the reliability of the function and space electronic device of FPGA device.Therefore, the application in space flight need to be carried out extra Design of Reinforcement for SRAM type FPGA device, to strengthen the ability of its anti-single particle effect, guarantees reliability service.
Often from device level and design level, SRAM type FPGA device is reinforced in order to resist single particle effect.Device level is that device itself is carried out anti-Radiation Hardened, is mainly to resist total dose effect and locking single particle etc., and it is available that each large chip manufacturer can release the chip of anti-Radiation Hardened of some aerospace levels.Design level is further reinforced by various design meanses, is mainly to resist single-particle inversion (SEU) and single event function interrupt (SEFI) etc.From design angle, SRAM type FPGA device is carried out anti-single particle effect and reinforce, two kinds of popular ways are at present:
1: triplication redundancy+timing is reshuffled: triplication redundancy is that the user logic in the FPGA device is backed up, and when guaranteeing that by the majority voting device some backups make mistakes, correct output is arranged still.Regularly reshuffle by periodically the FPGA device being reshuffled to eliminate the mistake accumulation that single particle effect causes fully.
2: triplication redundancy+timing heavily refreshes: triplication redundancy is that the user logic in the FPGA device is backed up, and when guaranteeing that by the majority voting device some backups make mistakes, correct output is arranged still.Regularly heavily refresh by the config memory to the FPGA device inside periodically and fully heavily refresh to correct the mistake accumulation that single particle effect causes.
Wherein, it is fairly simple that scheme is reshuffled in triplication redundancy+timing, is suitable for the undemanding occasion of all kinds of requirement of real-times, in all kinds of spacecrafts, practical application arranged at present.The heavy refresh scheme of triplication redundancy+timing designs more complicated, is suitable for occasion strict to requirement of real-time and can not the interrupt routine operation.
In scheme was reshuffled in triplication redundancy+timing, the way of main flow was to adopt outside device to control regularly to reshuffle at present, and triplication redundancy is added in the program design of FPGA device by the user.External devices can be single-chip microcomputer, watchdog circuit and the anti-fuse FPGA of Actel aerospace level device etc.This design proposal is except the FPGA device of normal operation, also need extra external devices, taken like this PCB area of hardware circuit, the complicacy that increases design and circuit board wiring difficulty, gain in weight and power consumption, thereby cause the reliability of hardware design to reduce.
Summary of the invention
Provide hereinafter about brief overview of the present invention, in order to basic comprehension about some aspect of the present invention is provided.Should be appreciated that this general introduction is not about exhaustive general introduction of the present invention.It is not that intention is determined key of the present invention or pith, neither be intended to limit scope of the present invention.Its purpose is only that the form of simplifying provides some concept, with this as the preorder in greater detail of discussing after a while.
A fundamental purpose of the present invention be to provide a kind of need not to increase the outside reshuffle circuit, required external devices few, simple in structure, take PCB resource few FPGA device deadweight inking device and method.
for achieving the above object, the invention provides a kind of FPGA device deadweight inking device, comprise the self-configuring circuit that is arranged in the FPGA device and the signal conditioning circuit that is arranged on FPGA device outside, the self-configuring circuit comprises the first to the 3rd counter and the testing circuit that is connected to the first to the 3rd counter, the first to the 3rd counter is used for receiving same clock pulse signal to carry out timing, and when regularly reaching preset value the output low level signal, otherwise output high level signal, whether one of them exports different level signals from other two counters to testing circuit for detection of the first to the 3rd counter, and output low level signal simultaneously detected not, when exporting identical level signal, exports by the first to the 3rd counter the level signal identical with the first to the 3rd counter when detecting, the output terminal of testing circuit connects signal conditioning circuit, signal conditioning circuit is used for the low level signal of testing circuit output is transferred to the pin of reshuffling of FPGA device, and control and reshuffle the pin low level time of maintenance more than Preset Time.
For realizing purpose of the present invention, the present invention also provides a kind of FPGA device from method for reconfiguration, comprising:
Receive same pulse signals and carry out timing by being arranged on three counters in the FPGA device, and when regularly reaching preset value output low level, otherwise export high level;
Detect by the testing circuit that is arranged in the FPGA device level signal that three counters are exported, if the level signal of three counter outputs is different, testing circuit output low level signal, if the level signal of three counter outputs is identical, the level signal that testing circuit output is identical with the first to the 3rd counter;
With the low level signal of the testing circuit output pin of reshuffling from the external transmission of FPGA device to FPGA, and control and reshuffle pin and keep the low level time more than Preset Time.
FPGA device deadweight inking device of the present invention and method do not need to increase extra single-chip microcomputer, FPGA device or watchdog circuit, the self-configuring circuit only is set in the FPGA device, get final product at the simple signal conditioning circuit of FPGA device outer setting, simple in structure, easily wiring, only take very little FPGA device inside resource, the PCB resource that takies is less, not only realized regularly reshuffling, also had and detect wrong function, can execute when mistake being detected and reshuffle.
Description of drawings
Below with reference to the accompanying drawings illustrate embodiments of the invention, can understand more easily above and other objects, features and advantages of the present invention.Parts in accompanying drawing are just in order to illustrate principle of the present invention.In the accompanying drawings, same or similar technical characterictic or parts will adopt same or similar Reference numeral to represent.
Fig. 1 is the block scheme of a kind of embodiment of field programmable gate array deadweight inking device of the present invention.
Fig. 2 is the circuit diagram of a kind of embodiment of field programmable gate array deadweight inking device of the present invention.
Fig. 3 is that field programmable gate array of the present invention is from the process flow diagram of a kind of embodiment of method for reconfiguration.
Fig. 4 is the process flow diagram of step S2 in Fig. 3.
Embodiment
Embodiments of the invention are described with reference to the accompanying drawings.The element of describing in an accompanying drawing of the present invention or a kind of embodiment and feature can combine with element and the feature shown in one or more other accompanying drawing or embodiment.Should be noted that for purpose clearly, omitted expression and the description of unrelated to the invention, parts known to persons of ordinary skill in the art and processing in accompanying drawing and explanation.
For SRAM type FPGA device, generally all provide one and reshuffle pin, by apply the low level pulse of a predetermined width at this pin, just can make the FPGA device enter the stage of reshuffling.The invention provides a kind of FPGA device deadweight inking device.in device of the present invention, the low level pulse of this predetermined width self is provided by FPGA device to be configured, particularly, in FPGA device to be configured, the self-configuring circuit is set, this self-configuring circuit output end is as an I/O pin of FPGA device to be configured, reshuffling pin by the signal conditioning circuit of outside with this is connected, but when reshuffling signal or mistake detected, force this self-configuring circuit timing output output to reshuffle signal, this is reshuffled signal and export the pin of reshuffling of FPGA device to after the signal conditioning circuit conditioning, make the FPGA device enter the stage of reshuffling, signal conditioning circuit is used for controlling reshuffles the pin low level time of maintenance more than Preset Time.
the invention provides a kind of FPGA device deadweight inking device, comprise the self-configuring circuit that is arranged in the FPGA device and the signal conditioning circuit that is arranged on FPGA device outside, the self-configuring circuit comprises the first to the 3rd counter and the testing circuit that is connected to the first to the 3rd counter, the first to the 3rd counter is used for receiving same clock pulse signal to carry out timing, and when regularly reaching preset value the output low level signal, otherwise output high level signal, whether one of them exports different level signals from other two counters to testing circuit for detection of the first to the 3rd counter, and output low level signal simultaneously detected not, when exporting identical level signal, exports by the first to the 3rd counter the level signal identical with the first to the 3rd counter when detecting, the output terminal of testing circuit connects signal conditioning circuit, signal conditioning circuit is used for the low level signal that testing circuit is exported is transferred to reshuffles pin, and control and reshuffle the pin low level time of maintenance more than Preset Time.
alternatively, testing circuit comprises the first to the 3rd voting machine, the first to the 3rd arithmetical unit, the first to the 3rd tri-state gate circuit, the first to the 3rd voting machine respectively has the first to the 3rd input end and the first output terminal and the second output terminal, the output terminal of the first counter is connected to the first input end of the first voting machine, the second input end of the second voting machine and the second input end of the 3rd voting machine, the output terminal of the second counter connects the first input end of the second voting machine, the second input end of the first voting machine and the 3rd input end of the 3rd voting machine, the output terminal of the 3rd counter connects the first input end of the 3rd voting machine, the 3rd input end of the first voting machine and the 3rd input end of the second voting machine, first arithmetic device be used for the first output terminal to the output terminal of the first counter and the first voting machine carry out with computing after export the input end of the first tri-state gate circuit to, the second output terminal of the first voting machine is as the control end of the first tri-state gate circuit, second arithmetic device be used for the first output terminal to the output terminal of the second counter and the second voting machine carry out with computing after export the input end of the second tri-state gate circuit to, the second output terminal of the second voting machine is as the control end of the second tri-state gate circuit, the 3rd arithmetical unit be used for the first output terminal to the output terminal of the 3rd counter and the 3rd voting machine carry out with computing after export the input end of the 3rd tri-state gate circuit to, the second output terminal of the 3rd voting machine is as the control end of the 3rd tri-state gate circuit, the connected rear output terminal as testing circuit of the output terminal of the first to the 3rd tri-state gate circuit, first, the first output terminal of the second or the 3rd voting machine is in second of correspondence, output high level signal when the level signal of the 3rd input end is identical, in second of correspondence, the level signal of the 3rd input end is output low level signal simultaneously not, first, the second output terminal of the second or the 3rd voting machine is in the level signal of the first input end of correspondence and corresponding second, output high level signal when the level signal of the 3rd input end is all identical, level signal and second at the first input end of correspondence, output low level signal when one of them level signal of the 3rd input end is identical.
With reference to figure 1, be the block scheme of FPGA device deadweight inking device of the present invention.In embodiments of the invention, be specifically described as an example of the FPGA device 100 of Xilinx Virtex series example, make the FPGA device 100 of Xilinx Virtex series enter the stage of reshuffling, need its pin PROGRAM to keep the above low level of 300ns (nanosecond).In this FPGA device 100 inside, self-configuring circuit 10 is set, the output terminal I/O of self-configuring circuit 10 connects the pin PROGRAM of FPGA devices 100 by the signal conditioning circuit 20 that is arranged on FPGA device 100 outsides, the output terminal I/O of self-configuring circuit 10 output high level during normal operation.Self-configuring circuit 10 is used for the receive clock signal carrying out timing, its output terminal I/O can be when timing reaches preset value output low level signal, i.e. configuration signal; When self-configuring circuit 10 detected mistake, it forced output low level; The low level signal of self-configuring circuit 10 outputs transfers to pin PROGRAM through modulate circuit 20, and it is above so that FPGA device 100 enters reset phase that modulate circuit 20 guarantees that this low level signal is kept 300ns.
With reference to figure 2, be the circuit diagram of FPGA device deadweight inking device of the present invention.In order to satisfy the demand of AEROSPACE APPLICATION, need to carry out the anti-single particle overturn Design of Reinforcement to the FPGA device, self-configuring circuit of the present invention adopts the triplication redundancy design of having improved, and possesses simultaneously the function of reinforcing and error detection function.As shown in Figure 2, self-configuring circuit 10 comprises counter Counter1-Counter3, voting machine M1-M3, and arithmetical unit U1-U3, tri-state gate circuit T1-T3, voting machine M1-M3 respectively have input end P, I1, I2 and output terminal X and Y.Voting machine M1-M3, arithmetical unit U1-U3, tri-state gate circuit T1-T3 consist of testing circuit.The input end of counter Counter1-Counter3 is used for the receive clock pulse signal, and the output terminal of counter Counter1 is connected to the input end P of voting machine M1, also connects the input end I1 of voting machine M2 and M3.The output terminal of counter Counter2 connects the input end P of voting machine M2, also connects the input end I1 of voting machine M1 and the input end I2 of voting machine M3.The output terminal of counter Counter3 connects the input end P of voting machine M3 and the input end I2 of voting machine M1, M2.Arithmetical unit U1 be used for output terminal X to the output terminal of counter Counter1 and voting machine M1 carry out with computing after export the input end of tri-state gate circuit T1 to, the output terminal Y of voting machine M1 is as the control end of tri-state gate circuit T1.Arithmetical unit U2 be used for output terminal X to the output terminal of counter Counter2 and voting machine M2 carry out with computing after export the input end of tri-state gate circuit T2 to, the output terminal Y of voting machine M2 is as the control end of tri-state gate circuit T2.Arithmetical unit U3 be used for output terminal X to the output terminal of counter Counter3 and voting machine M3 carry out with computing after export the input end of tri-state gate circuit T3 to, the output terminal Y of voting machine M3 is as the control end of tri-state gate circuit T3.The connected rear output terminal I/O as self-configuring circuit 10 of the output terminal of tri-state gate circuit T1-T3.
Counter Counter1-Counter3 is used for the time clock that receives is counted, output low level when counting reaches preset value, otherwise output high level.
See table, be the truth table of input end P, I1, I2 and output terminal X, the Y of each voting machine M1-M3.Input end I1, the I2 of each voting machine M1-M3 are for detection of mistake, when the level signal of the input end I1 of each voting machine M1-M3 and I2 is identical, corresponding output terminal X output high level " 1 ", when the level signal of the input end I1 of each voting machine M1-M3 and I2 not simultaneously, corresponding output terminal X output low level " 0 ".If the input end P of each voting machine M1-M3 is all different from corresponding input end I1 and I2, corresponding output terminal Y output high level " 1 ", if the input end P of each voting machine M1-M3 and corresponding input end I1 and one of them identical, corresponding output terminal Y output low level " 0 " of I2.
| P | I1 | I2 | X | Y |
| 0 | 0 | 0 | 0 | 1 |
| 0 | 0 | 1 | 0 | 0 |
| 0 | 1 | 0 | 0 | 0 |
| 0 | 1 | 1 | 1 | 1 |
| 1 | 0 | 0 | 1 | 1 |
| 1 | 0 | 1 | 0 | 0 |
| 1 | 1 | 0 | 0 | 0 |
| 1 | 1 | 1 | 0 | 1 |
Under normal circumstances, the clock pulse signal that counter Counter1-Counter3 receives is identical, therefore output is also identical, the output terminal X of three voting machine M1-M3 all exports high level, the equal output low level of output terminal Y of three voting machine M1-M3, when counting did not reach preset value, the output terminal of tri-state gate circuit T1-T3 was all exported high level, when reaching preset value, the equal output low level of the output terminal of tri-state gate circuit T1-T3.
Suppose due to the space single particle effect, the storage unit generation single-particle inversion that causes FPGA device 100 inside, cause one of them counter, Counter1 makes mistakes as counter, all the other two counters are normal, at this moment, for voting machine M1, the level signal of its input end I1, I2 is identical, and the level signal of its input end P is different from the level signal of input end I1, I2, so output terminal X output high level, output terminal Y exports high level, tri-state gate circuit T1 closes, and the output terminal of tri-state gate circuit T1 becomes high-impedance state, forbids output.
For voting machine M2, the level signal of its input end I1, I2 is different, and the level signal of input end P is identical with one of input end I1, I2, so output terminal X output low level, output terminal Y output low level, arithmetical unit U2 output low level, tri-state gate circuit T2 output low level.
For voting machine M3, its input end I1, I2 are different, and the level signal of input end P is identical with one of input end I1, I2, so output terminal X output low level, output terminal Y output low level, arithmetical unit U3 output low level, tri-state gate circuit T3 output low level.
in signal conditioning circuit 20, capacitor C 1 and pull-up resistor R1 consist of charge-discharge circuit, during normal operation, capacitor C 1 two ends are high level, when receiving the low level signal of tri-state gate circuit T2 and T3 output, capacitor C 1 begins discharge so that pin PROGRAM is drawn as low level, the parameter value of suitably choosing capacitor C 1 and pull-up resistor R1 just can make the low level retention time of pin PROGRAM more than 300ns, for other serial FPGA device, can obtain different discharge times by the selection of capacitor C 1 and pull-up resistor R1 parameter value, to adapt to the demand of different low level retention times.After discharge finished, capacitor C 1 played the effect of isolation, by on pull on resistance R 1 and guarantee that pin PROGRAM reverts to high level, after completing to guarantee to reset, FPGA device 100 recovers normal operation.
Alternatively, signal conditioning circuit also comprises hand switch K1, and hand switch K1 one end connects pin PROGRAM, other end ground connection, and hand switch is used for hand-reset to start reshuffling of FPGA device 100.
Alternatively, signal conditioning circuit 20 also comprises pull down resistor R2, and the end of pull down resistor R2 connects the output terminal of tri-state gate circuit T1-T3, other end ground connection.In AEROSPACE APPLICATION, except single particle effect easily occurs and making a mistake in the config memory of FPGA device inside, single particle effect also can occur and make mistakes in the important register of some of FPGA device inside, to cause like this some critical functions of FPGA device to lose efficacy, single event function interrupt namely, single event function interrupt can be divided into following two kinds of situations;
1, electrification reset logic (POR) register and some overall signals etc. make a mistake, and will cause all inputs of FPGA device, output pin to lose efficacy, and become high-impedance state.
2, SelectMAP configuration register, JTAG configuration register and FAR frame address register make a mistake, and will cause the configuration interface of FPGA device to lose efficacy, and all the other output/output interfaces are normal.
For the first situation, although the program of FPGA device inside can also normally be moved, the I/O pin becomes high-impedance state and lost efficacy, and also will cause the FPGA device to work.Pull down resistor R2 is set in signal conditioning circuit 20, in case becoming high-impedance state, all I/O of FPGA device lost efficacy, capacitor C 1 will be discharged by this pull down resistor R2, cause pin PROGRAM to become low level, the appearance value by suitable selection capacitor C 1 and the resistance of pull down resistor R2 can make more than the low level of pin PROGRAM keeps 300ns.Like this, automatically enter reconfiguration status when just having realized the generation single event function interrupt, make FPGA device 100 recover normal operation.
For the second situation, be only the configuration circuit interface fails, the program of all the other I/O pins and FPGA device inside still can work, and does not affect like this systemic-function.Wait for counting reach preset value carry out regularly reshuffle after, will correct these mistakes, thereby make FPGA device 100 recovery normal operating conditionss.
Therefore, pull down resistor R2 is set in signal conditioning circuit 20, automatically reshuffling in the time of can realizing single event function interrupt is so that the FPGA device recovers normal operation.
With reference to figure 3, FPGA device of the present invention is used FPGA device deadweight inking device of the present invention from method for reconfiguration and is carried out reshuffling of FPGA device, comprises the following steps:
Step S1: receive same pulse signal and carry out timing by being arranged on three counters (being counter Counter1-Counter3) in the FPGA device, and when regularly reaching preset value output low level, otherwise export high level;
Step S2: detect the level signal that three counters are exported by the testing circuit that is arranged in the FPGA device, if the level signal of three counter outputs is different, testing circuit output low level signal, if the level signal of three counter outputs is identical, testing circuit output and three level signals that counter is identical;
Step S3: with the low level signal of the testing circuit output pin of reshuffling from the external transmission of FPGA device to the FPGA of institute device, i.e. pin PROGRAM, and control and reshuffle pin and keep the low level time more than Preset Time.
With reference to figure 4, alternatively, step S2 comprises the following steps:
Step S21: judge respectively whether the wherein output of two in three counters is identical; In this step, respectively the output of three counters judged in twos, for example, whether whether the output that judges counter Counter1 and Counter2 identical (being namely all high level " 1 " or low level " 0 "), whether the output that judges counter Counter2 and Counter3 is identical, judges also whether the output of counter Counter1 and Counter3 is identical;
Step S22: for the identical situation of any two counters output, output and the high level " 1 " of another counter carried out AND operation; For the different situation of any two counters output, another counter and low level " 0 " are carried out AND operation; For example, identical when the output of counter Counter1 and Counter2, output and the high level " 1 " of counter Counter3 carried out AND operation, otherwise output and the low level " 0 " of counter Counter3 are carried out AND operation; Identical when the output of counter Counter2 and Counter3, output and the high level " 1 " of counter Counter1 carried out AND operation, otherwise output and the low level " 0 " of counter Counter1 are carried out AND operation; Identical when the output of counter Counter1 and Counter3, output and the high level " 1 " of counter Counter2 carried out AND operation, otherwise output and the low level " 0 " of counter Counter2 are carried out AND operation;
Step S23: judge respectively whether three counters are identical with the output of two other counter; In this step, whether the output that judges counter Counter1 is identical with counter Counter1 and Counter2, whether the output that judges counter Counter2 is identical with counter Counter1 and Counter3, judges also whether the output of counter Counter3 is identical with counter Counter1 and Counter2;
Step S24: if one of them counter is all different from two other counter output, forbid exporting the result after this counter and high level " 1 " or low level " 0 " carry out AND operation; For example, if the output of counter Counter1 is all different from counter Counter1 and Counter2, forbid the result after output counter Counter1 and high level " 1 " or low level " 0 " are carried out AND operation; If the output of counter Counter2 is all different from counter Counter1 and Counter3, forbid the result after output counter Counter2 and high level " 1 " or low level " 0 " are carried out AND operation; If the output of counter Counter3 is all different from counter Counter1 and Counter2, forbid the result after output counter Counter3 and high level " 1 " or low level " 0 " are carried out AND operation;
Step S25: if the output of one of them counter is identical with the output of one of two other counter, export the result after this counter and high level " 1 " or low level " 0 " are carried out AND operation.For example, if the output of counter Counter1 is identical with the output of counter Counter1 or Counter2, output counter Counter1 and high level " 1 " or low level " 0 " are carried out the result after AND operation; If the output of counter Counter2 is identical with counter Counter1 or Counter2, output counter Counter2 and high level " 1 " or low level " 0 " are carried out the result after AND operation; If the output of counter Counter3 is identical with counter Counter1 or Counter2, output counter Counter3 and high level " 1 " or low level " 0 " are carried out the result after AND operation.
deadweight inking device of the present invention and method do not need to increase extra single-chip microcomputer, FPGA device or watchdog circuit, the self-configuring circuit only is set in the FPGA device, get final product at the simple signal conditioning circuit of FPGA device outer setting, simple in structure, easily wiring, only take very little FPGA device inside resource, take less PCB resource, utilize three counters and testing circuit to realize the reinforcing mode of triplication redundancy, not only realized regularly reshuffling, also have and detect wrong function, can execute when mistake being detected and reshuffle, automatically reshuffling in the time of also can realizing single event function interrupt occurs.
In system of the present invention, obviously, after can decomposing, make up and/or decompose, each parts or each step reconfigure.These decomposition and/or reconfigure and to be considered as equivalents of the present invention.Simultaneously, in the above in the description to the specific embodiment of the invention, can use in one or more other embodiment in same or similar mode for the feature that a kind of embodiment is described and/or illustrated, combined with the feature in other embodiment, or the feature in alternative other embodiment.
In equipment of the present invention, obviously, each parts reconfigure after can decomposing, make up and/or decomposing.These decomposition and/or reconfigure and to be considered as equivalents of the present invention.In the above in the description to the specific embodiment of the invention, can use in one or more other embodiment in same or similar mode for the feature that a kind of embodiment is described and/or illustrated, combined with the feature in other embodiment, or the feature in alternative other embodiment.
Should emphasize, term " comprises/comprises " existence that refers to feature, key element, step or assembly when this paper uses, but does not get rid of the existence of one or more further feature, key element, step or assembly or add.
Although described the present invention and advantage thereof in detail, be to be understood that in the situation that do not exceed the spirit and scope of the present invention that limited by appended claim and can carry out various changes, alternative and conversion.And the application's scope is not limited only to the specific embodiment of the described process of instructions, equipment, means, method and step.The one of ordinary skilled in the art will readily appreciate that from disclosure of the present invention, can use according to the present invention carry out with the essentially identical function of corresponding embodiment described herein or obtain result essentially identical with it, existing and want exploited process, equipment, means, method or step future.Therefore, appended claim is intended to comprise such process, equipment, means, method or step in their scope.
Claims (7)
1. FPGA deadweight inking device, comprise the self-configuring circuit that is arranged in FPGA and the signal conditioning circuit that is arranged on described field programmable gate array outside, described self-configuring circuit comprises the first to the 3rd counter and the testing circuit that is connected to described the first to the 3rd counter, described the first to the 3rd counter is used for receiving same clock pulse signal to carry out timing, and when regularly reaching preset value the output low level signal, otherwise output high level signal, whether one of them exports different level signals from other two counters to described testing circuit for detection of described the first to the 3rd counter, and output low level signal simultaneously detected not, when exporting identical level signal, exports by described the first to the 3rd counter the level signal identical with described the first to the 3rd counter when detecting, the output terminal of described testing circuit connects described signal conditioning circuit, described signal conditioning circuit is used for the low level signal of described testing circuit output is transferred to the pin of reshuffling of described FPGA, and control the described pin of reshuffling and keep the low level time more than Preset Time.
2. FPGA as claimed in claim 1 deadweight inking device, it is characterized in that, described testing circuit comprises the first to the 3rd voting machine, the first to the 3rd arithmetical unit, the first to the 3rd tri-state gate circuit, described the first to the 3rd voting machine respectively has the first to the 3rd input end and the first output terminal and the second output terminal, the output terminal of described the first counter is connected to the first input end of described the first voting machine, the second input end of described the second voting machine and the second input end of the 3rd voting machine, the output terminal of described the second counter connects the first input end of described the second voting machine, the second input end of the first voting machine and the 3rd input end of the 3rd voting machine, the output terminal of described the 3rd counter connects the first input end of described the 3rd voting machine, the 3rd input end of the first voting machine and the 3rd input end of the second voting machine, described first arithmetic device be used for the first output terminal to the output terminal of described the first counter and described the first voting machine carry out with computing after export the input end of described the first tri-state gate circuit to, the second output terminal of described the first voting machine is as the control end of described the first tri-state gate circuit, described second arithmetic device be used for the first output terminal to the output terminal of described the second counter and the second voting machine carry out with computing after export the input end of described the second tri-state gate circuit to, the second output terminal of described the second voting machine is as the control end of described the second tri-state gate circuit, described the 3rd arithmetical unit be used for the first output terminal to the output terminal of described the 3rd counter and described the 3rd voting machine carry out with computing after export the input end of described the 3rd tri-state gate circuit to, the second output terminal of described the 3rd voting machine is as the control end of described the 3rd tri-state gate circuit, the connected rear output terminal as described testing circuit of the output terminal of described the first to the 3rd tri-state gate circuit, described first, the first output terminal of the second or the 3rd voting machine is in second of correspondence, output high level signal when the level signal of the 3rd input end is identical, in second of correspondence, the level signal of the 3rd input end is output low level signal simultaneously not, described first, the second output terminal of the second or the 3rd voting machine is in the level signal of the first input end of correspondence and corresponding second, output high level signal when the level signal of the 3rd input end is all identical, level signal and second at the first input end of correspondence, output low level signal when one of them level signal of the 3rd input end is identical.
3. FPGA as claimed in claim 1 deadweight inking device, it is characterized in that, described signal conditioning circuit comprises electric capacity and pull-up resistor, one end of described electric capacity connects the output terminal of described testing circuit, the other end connects the pin of reshuffling of an end of described pull-up resistor and described FPGA, and the other end of described pull-up resistor connects power supply.
4. FPGA deadweight inking device as claimed in claim 3, is characterized in that, described signal conditioning circuit also comprises hand switch, and an end of described hand switch connects the described pin of reshuffling, other end ground connection.
5. FPGA deadweight inking device as claimed in claim 3, is characterized in that, described signal conditioning circuit also comprises pull down resistor, and an end of described pull down resistor connects the output terminal of described testing circuit, other end ground connection.
6. a FPGA from method for reconfiguration, comprising:
Receive same pulse signals and carry out timing by being arranged on three counters in FPGA, and when regularly reaching preset value output low level, otherwise export high level;
Detect by the testing circuit that is arranged in described FPGA the level signal that described three counters are exported, if the level signal of described three counters output is different, described testing circuit output low level signal, if the level signal of described three counters output is identical, the described testing circuit output level signal identical with described the first to the 3rd counter;
With the low level signal of the described testing circuit output pin of reshuffling from the external transmission of described FPGA to described FPGA, and control the described pin of reshuffling and keep the low level time more than Preset Time.
7. FPGA as claimed in claim 6 from method for reconfiguration, is characterized in that, the step that testing circuit detects the level signal of described three counters output comprises:
Judge respectively whether the wherein output of two in described three counters is identical;
For the identical situation of any two counters output, output and the high level " 1 " of another counter carried out AND operation; For the different situation of any two counters output, another counter and low level " 0 " are carried out AND operation;
Judge respectively whether described three counters are identical with the output of two other counter;
If one of them counter is all different from two other counter output, forbid exporting the result after this counter and high level " 1 " or low level " 0 " carry out AND operation;
If the output of one of them counter is identical with the output of one of two other counter, export the result after this counter and high level " 1 " or low level " 0 " are carried out AND operation.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110439628.8A CN103176945B (en) | 2011-12-23 | 2011-12-23 | FPGA is from reconfiguration device and method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110439628.8A CN103176945B (en) | 2011-12-23 | 2011-12-23 | FPGA is from reconfiguration device and method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103176945A true CN103176945A (en) | 2013-06-26 |
| CN103176945B CN103176945B (en) | 2015-11-18 |
Family
ID=48636831
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201110439628.8A Expired - Fee Related CN103176945B (en) | 2011-12-23 | 2011-12-23 | FPGA is from reconfiguration device and method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103176945B (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104750481A (en) * | 2015-03-10 | 2015-07-01 | 深圳大学 | FPGA output pin multiplex circuit, method and equipment |
| US9411613B1 (en) | 2015-04-22 | 2016-08-09 | Ryft Systems, Inc. | Systems and methods for managing execution of specialized processors |
| US9411528B1 (en) | 2015-04-22 | 2016-08-09 | Ryft Systems, Inc. | Storage management systems and methods |
| US9542244B2 (en) | 2015-04-22 | 2017-01-10 | Ryft Systems, Inc. | Systems and methods for performing primitive tasks using specialized processors |
| CN108536637A (en) * | 2018-04-24 | 2018-09-14 | 姜黎 | A kind of communication system and method for transmitter conditioning chip |
| US10454524B2 (en) | 2016-11-11 | 2019-10-22 | Tesat-Spacecom Gmbh & Co. Kg | Tristate and cross current free output buffer |
| CN111104240A (en) * | 2019-11-28 | 2020-05-05 | 中国航空工业集团公司西安航空计算技术研究所 | FPGA fault self-recovery circuit and method |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5825202A (en) * | 1996-09-26 | 1998-10-20 | Xilinx, Inc. | Integrated circuit with field programmable and application specific logic areas |
| US20040017724A1 (en) * | 2002-07-24 | 2004-01-29 | Hitachi, Ltd. | Semiconductor processing device |
| US20070038790A1 (en) * | 2005-08-11 | 2007-02-15 | Young-Min Lee | Integrated circuit devices, methods, and computer program products for monitoring a bus |
-
2011
- 2011-12-23 CN CN201110439628.8A patent/CN103176945B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5825202A (en) * | 1996-09-26 | 1998-10-20 | Xilinx, Inc. | Integrated circuit with field programmable and application specific logic areas |
| US20040017724A1 (en) * | 2002-07-24 | 2004-01-29 | Hitachi, Ltd. | Semiconductor processing device |
| US20070038790A1 (en) * | 2005-08-11 | 2007-02-15 | Young-Min Lee | Integrated circuit devices, methods, and computer program products for monitoring a bus |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104750481A (en) * | 2015-03-10 | 2015-07-01 | 深圳大学 | FPGA output pin multiplex circuit, method and equipment |
| CN104750481B (en) * | 2015-03-10 | 2018-04-17 | 深圳大学 | A kind of FPGA output pins multiplex circuit, method and apparatus |
| US9411613B1 (en) | 2015-04-22 | 2016-08-09 | Ryft Systems, Inc. | Systems and methods for managing execution of specialized processors |
| US9411528B1 (en) | 2015-04-22 | 2016-08-09 | Ryft Systems, Inc. | Storage management systems and methods |
| US9542244B2 (en) | 2015-04-22 | 2017-01-10 | Ryft Systems, Inc. | Systems and methods for performing primitive tasks using specialized processors |
| US10454524B2 (en) | 2016-11-11 | 2019-10-22 | Tesat-Spacecom Gmbh & Co. Kg | Tristate and cross current free output buffer |
| CN108536637A (en) * | 2018-04-24 | 2018-09-14 | 姜黎 | A kind of communication system and method for transmitter conditioning chip |
| CN108536637B (en) * | 2018-04-24 | 2021-07-02 | 杭州芯声智能科技有限公司 | Communication system and method for transmitter conditioning chip |
| CN111104240A (en) * | 2019-11-28 | 2020-05-05 | 中国航空工业集团公司西安航空计算技术研究所 | FPGA fault self-recovery circuit and method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103176945B (en) | 2015-11-18 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103176945B (en) | FPGA is from reconfiguration device and method | |
| CN111352338B (en) | Dual-redundancy flight control computer and redundancy management method | |
| Bridgford et al. | Single-event upset mitigation selection guide | |
| US10078565B1 (en) | Error recovery for redundant processing circuits | |
| Label et al. | Single-event-effect mitigation from a system perspective | |
| CN108055031B (en) | Self-recovery triple modular redundancy structure for resisting single-particle soft error accumulation | |
| KR102415148B1 (en) | Voting circuit and self-correcting latch | |
| CN104731668B (en) | The fault management of FPGA triplication redundancy frameworks and recovery controller and its control method | |
| US7990173B1 (en) | Single event upset mitigation | |
| Carmichael et al. | Correcting single-event upsets in Virtex-4 FPGA configuration memory | |
| Straka et al. | Fault tolerant structure for sram-based fpga via partial dynamic reconfiguration | |
| Petrović et al. | Fault-tolerant TMR and DMR circuits with latchup protection switches | |
| EP1146423B1 (en) | Voted processing system | |
| Györök et al. | Duplicated control unit based embedded fault-masking systems | |
| Straka et al. | Modern fault tolerant architectures based on partial dynamic reconfiguration in fpgas | |
| CN101794241A (en) | Circuit of power-on reset of triple redundancecy fault-tolerance computer based on programmable logic device | |
| Choi et al. | Area-efficient fault tolerant design for finite state machines | |
| Agiakatsikas et al. | FMER: A hybrid configuration memory error recovery scheme for highly reliable FPGA SoCs | |
| Dumitriu et al. | Decentralized run-time recovery mechanism for transient and permanent hardware faults for space-borne FPGA-based computing systems | |
| Czajkowski et al. | SEU mitigation for reconfigurable FPGAs | |
| CN106301352B (en) | A kind of Anti-radioactive Fault-tolerant circuit design method based on door or door and selector | |
| Yuanqing et al. | A self-checking approach for SEU/MBUs-hardened FSMs design based on the replication of one-hot code | |
| Cherezova et al. | Understanding fault-tolerance vulnerabilities in advanced SoC FPGAs for critical applications | |
| Hane | A fault-tolerant computer architecture for space vehicle applications | |
| Tabero et al. | Modular fault tolerant processor architecture on a SoC for space |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20151118 Termination date: 20181223 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |