CN103180933A - 提高具有纳米颗粒的半导体互连的机械性质的方法 - Google Patents

提高具有纳米颗粒的半导体互连的机械性质的方法 Download PDF

Info

Publication number
CN103180933A
CN103180933A CN2011800432052A CN201180043205A CN103180933A CN 103180933 A CN103180933 A CN 103180933A CN 2011800432052 A CN2011800432052 A CN 2011800432052A CN 201180043205 A CN201180043205 A CN 201180043205A CN 103180933 A CN103180933 A CN 103180933A
Authority
CN
China
Prior art keywords
nano particle
ulk
cap rock
sandwich construction
dielectric layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN2011800432052A
Other languages
English (en)
Inventor
鲍军静
N·E·勒斯蒂格
郑天人
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of CN103180933A publication Critical patent/CN103180933A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/022Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02203Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being porous
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02296Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02345Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to radiation, e.g. visible light
    • H01L21/02348Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to radiation, e.g. visible light treatment by exposure to UV light
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76825Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by exposing the layer to particle radiation, e.g. ion implantation, irradiation with UV light or electrons etc.
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76832Multiple layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329Insulating materials
    • H01L23/53295Stacked insulating layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00Semiconductor device manufacturing: process
    • Y10S438/96Porous semiconductor

Abstract

在BEOL工艺中,在超低k(ULK)电介质100的固化工艺中使用UV辐射。这一辐射经过ULK材料渗透并且到达在它下面的盖层膜。在UV光与膜之间的相互作用造成盖层膜的性质的改变。特别关注盖层的应力状态从压缩应力改变成拉伸应力。这造成更弱的电介质-盖层界面和ULK膜的机械失效。在盖层130与ULK膜之间插入纳米颗粒层120。纳米颗粒在UV光可以损坏盖层膜之前吸收UV光,因此维持ULK电介质的机械完整性。

Description

提高具有纳米颗粒的半导体互连的机械性质的方法
技术领域
本发明主要地涉及半导体集成电路和器件,并且更具体地涉及在半导体互连处理中应用纳米颗粒。
背景技术
基于半导体的器件和电路由硅晶片表面上的通常为晶体管的有源器件和互连它们的传导线的集合构成。这一接线集合通常称为后端工艺(BEOL),而有源晶体管称为前端工艺(FEOL)。需要传导互连的复杂网络以便电接线大量器件,由此创建功能电路。这通过构建由绝缘介电介质中嵌入的金属线构成的多级结构来实现。现代高速互连通常由通过低介电常数(低k)材料相互绝缘的铜(Cu)导体构成。互连结构可以由多达十五个竖直堆叠的金属级构成而在级之间有称为过孔的传导路径。接线由它们的线宽和到最近邻居的距离表征。这一接线宽度和间隔之和称为节距。以如光刻确定的最小允许技术节距构建第一数个接线级。紧密节距允许构建最密集电路,而以最小节距的倍数构建更高级。这一分级结构在通常用于跨越芯片分发信号和功率的更高级允许也称为胖接线的粗字线。除了用作电绝缘体之外,介电材料提供用于多级结构的机械支撑。
目前,通常通过双大马士革处理形成Cu/低k多级结构如下:电介质材料被沉积为毯(blanket)膜、光刻图案化、然后反应离子蚀刻(RIE)从而创建沟槽和过孔二者。图案然后由难熔金属屏障(诸如Ta和TaNx)、继而由薄溅射铜籽晶层涂覆。籽晶层允许电化学沉积(ECD)厚铜层,该铜层填充孔。去除过量铜并且通过化学机械抛光(CMP)平坦化表面。最后,在图案化的铜线之上沉积也称为‘盖层’的薄电介质膜。在构建的更高级中的每级重复这一双大马士革工艺。
如摩尔定律预测的那样,半导体器件继续按比例缩减以便提高器件性能并且在衬底上放置更多晶体管。互连结果的对应按比例缩减引起与铜/低k互连关联的寄生电阻(R)和电容(C)的增加。RC乘积是BEOL向电路中引入的时间延迟的测量。为了减少RC延迟,使用低k和超低k(ULK)材料作为电介质。
典型类型的低k电介质是也称为SiCOH的有机硅酸盐玻璃材料。它由作为骨干的交联SiO2式四面结构和作为用于降低可极化性、引入有孔性并且减少体积密度的端基团或者侧链的一些-CH3或者-H构成。通常通过等离子体增强化学气相沉积(PECVD)工艺沉积低k电介质,该工艺混合用于牺牲造孔(porogen)的有机前体(例如环己烯等)和用于低k骨干结构的基质前体(例如十甲基环戊硅氧烷(decamethylcyclopentasiloxane)、甲基二乙氧基硅烷(diethoxymethylsilane)、二甲氧基二甲基硅烷(dimethyldimethoxysilane)、四甲基环四硅氧烷(tetramethylcyclotetrasilane)、八甲基环四硅氧烷(octamethylcyclotetrasilane)等)。在沉积步骤之后是用于去除松弛键合到低k骨干的挥发性有机造孔的紫外线(UV)固化工艺。因而向低k电介质中引入有孔性。此外,UV固化工艺也引起低k电介质的交联从而提高机械强度。然而已知ULK膜比它们的非有孔低k对应物在机械上更弱。有孔性和减少的介电常数伴随有膜的杨氏模量的减少。典型ULK模量依赖于有孔性的程度在2-8Gpa范围中从而使ULK膜在BEOL处理期间和在芯片封装期间尤其易受机械应力影响。
覆盖大马士革金属结构的顶部的电介质膜防止铜向外扩散到周围低k电介质中。从性能和可靠性的观点来看,盖层电介质的物理和机械性质(诸如击穿电压、与下层金属和电介质的粘合性、密封性、内部应力以及弹性模量)颇为重要。一般而言,与铜具有良好粘合性的机械压缩膜帮助抑制Cu电迁移并且提供在机械上鲁棒的结构。更密集的压缩模也往往具有更高击穿电压并且提供铜线的增强密封性和钝化。在高级半导体制造中使用的典型电介质屏障是非晶态碳氮化硅(SiCNH)。
在ULK电介质的固化工艺中使用的UV辐射波长范围从200nm到600nm并且由UV灯泡生成,下文参照图1举例说明。辐射可以经过ULK膜渗透并且损坏SiCNH盖层,从而造成它的机械应力状态从压缩改变成拉伸。这继而可以造成在盖层以上的有孔ULK材料的自发破裂和在芯片封装操作期间的不良可靠性。现有解决方案是用双层低k盖层替换常规单层SiCHN。这一解决方案具有两个问题:首先,盖层的应力状态仍然以更慢速率改变。仅如果UV固化时间短(<70秒),则膜才保持压缩。典型ULK固化时间大于100秒。对于这些更长固化时间,双层盖层应力状态变成拉伸;并且其次,在底部上有富氮SiCNH而在顶部上有富碳SiCNH的双层盖层往往在UV辐射之下收缩。粗略估计在UV固化的70秒之下约为2%厚度,而高k(标准)SiCNH的厚度改变在相同照射条件之下约为零。盖层的这一收缩不合需要并且可能造成BEOL结构上的附加机械应力。
参照图2,图示在ULK固化期间由于曝光于UV所致的SiCHN盖层膜的内部应力改变(以MPa为单位测量)。针对在不同UV固化时间的不同盖层材料示出应力测量。更具体而言,在ULK固化期间由于曝光于UV所致的应力改变示出内部应力随着UV固化时间增加而从负值(压缩应力)改变成正值(拉伸应力)。标识为SiCNH高k的曲线代表常规沉积工艺,而引用为SiCNH低k的第二曲线代表双层沉积工艺。虽然双层盖层可以减缓应力改变速率,但是膜最终变成拉伸(即从负到正值穿越y轴)。可以在吸收高能UV光子时SiCHN膜中的键合断裂机制方面理解从压缩到拉伸应力的这一改变。所得断裂(也称为悬摆(dangling))的键造成内部打开空间的增加和减少的压缩应力。拉伸膜更易于破裂和失去与下层图案的粘合性。
图3示出在曝光于UV辐射时收缩的双层低k盖层的厚度。这一盖层膜由于失去膜中的键合氢和碳基团而失去它的初始厚度的约2%。常规高k SiCNH在相似曝光于UV辐射时厚度未收缩。
参照图4,示出与关联反应物一起分散于双蒸馏水中的典型金属氧化物(例如ZnO)的UV-VIS吸收特征曲线。曲线1、2和3分别对应于PVP(用来防止凝聚的聚乙烯吡咯烷酮)、ZnO(纳米颗粒)和Zn(NO3)2。可以通过不同类型的醇溶液(比如甲醛、乙醇、丙醇或者更高醇)合成ZnO纳米颗粒。
X射线衍射、TEM和EDAX用来验证ZnO纳米颗粒的形成。在落在体ZnO的388nm(Eg=3.2eV)的带隙波长(表示为图4中的虚线)以下的262nm观测到用于ZnO纳米颗粒的吸收峰值。吸收边缘中的向更低波长的移位是纳米颗粒的基本性质并且归结于带隙在颗粒尺寸变小时加宽。
参照图5,针对各种颗粒直径图示纳米颗粒尺寸对峰值吸收波长的影响。ZnO纳米颗粒在平均颗粒尺寸为2.1nm时在近似262nm示出峰值吸收。图5中的圆点指示如从TEM分析获得的平均颗粒尺寸的值。根据前文不言而喻,ZnO纳米颗粒针对少于约8nm的颗粒直径表现显著限制效果。
附图说明
在说明书中并入的并且构成说明书的部分的附图图示本发明的当前优选实施例,这些实施例与上文给出的一般描述和下文给出的优选实施例的具体描述一起用于说明本发明的原理,在附图中,相似标号表示相似单元和部分,在附图中:
图1是示出如现有技术中已知的UV灯泡的光谱输出的、辐射功率比对波长的绘图;
图2是示出如现有技术中已知的在ULK固化期间由于曝光于UV辐射所致的单层和双层SiCHN盖层膜的内部应力改变的绘图;
图3示出如下图形,该图形绘制双层低k盖层的百分比膜厚度收缩比对UV固化时间。如现有技术中已知,这一收缩归结于失去键合氢和碳;
图4示出如现有技术中已知的ZnO纳米颗粒的UV-VIS吸收特征曲线;
图5图示如现有技术中已知的纳米颗粒(例如ZnO纳米胶体)的尺寸对峰值吸收波长的影响;
图6图示根据本发明一个实施例的结构的侧视截面图,该图示出在超低k(ULK)电介质与SiCNH盖层之间的多分布尺寸纳米颗粒允许吸收具有宽波长的UV射线;
图7示出通过用UV固化沉积第二ULK级将结构转换成多级互连配置的侧视截面图;
图8是一个实施例的侧视截面图,该图示出形成用于光刻目的的TEOS HM层、继而为用于形成沟槽和过孔的ULK蚀刻、继而为纳米颗粒的选择性去除;
图9示出侧视截面图,该图图示填充沟槽和过孔155(图8)的原位Cu籽晶和TaN/Ta衬垫沉积、继而为电镀铜沉积。
图10是侧视截面图,该图示出根据本发明一个实施例的最终BEOL堆叠物,该堆叠物描绘在ULK电介质与SiCNH盖层之间的界面中放置的多级结构纳米颗粒。
发明内容
在一个方面中,本发明描述在覆盖金属互连的盖层材料与在它以上的ULK绝缘电介质材料之间插入纳米颗粒。使用纳米颗粒造成在处理期间的减少的紫外线(UV)辐射损坏。在无辐射损坏时,盖层材料保持在机械上压缩,因此增加BEOL结构的强度。在本发明的一个实施例中使用的紫外线照射优选地由具有如下光谱的UV灯泡生成,该光谱范围从200nm至600nm而波长的大部分优选地在400nm以下。
在盖层与UL之间插入多尺寸纳米颗粒层以在ULK固化工艺期间吸收UV辐射。纳米颗粒优选地由直径范围从1nm至4nm的金属氧化物制成。这一纳米颗粒尺寸范围保证上至近似375nm的UV辐射的高度吸收。根据膜的碳含量的用于SiCNH膜的吸收边缘对于26%的碳近似地为400nm。在一个实施例中,如RBS确定的那样,膜的范围在20-26%碳之间。波长比400nm更长的辐射经过SiCNH膜透射并且不能引起损坏,该损坏将膜驱动成拉伸应力。另一方面,纳米颗粒吸收可以损坏SiCHN膜的落在200nm至400nm之间的UV灯泡光谱的约90%。
纳米颗粒单层的形成有助于提供特别是在制造半导体后端(BEOL)和后续集成期间能够应对机械应力的鲁棒结构。提供优选地由金属氧化物(诸如ZnO或者TiO2)制成并且能够衰减和吸收在形成超低k电介质时使用的UV辐射的纳米颗粒单层。
在又一方面中,在本发明的一个实施例中,在SiCNH盖层与超低k电介质之间放置纳米颗粒,从而吸收UV辐射,保护盖层免受UV损坏和关联的压缩到拉伸应力改变。(注意:盖层适用于下一级用作为用于下一纳米颗粒沉积的基础,因为在构建的多级结构的每个ULK级都需要纳米颗粒保护以防UV)。调整纳米颗粒的尺寸以在某些波长时高效吸收UV辐射。
在又一方面中,本发明提供在盖层上旋涂并且通过去除溶液来干燥的纳米颗粒,溶液由甲醇或者其它有机醇制成。
在又一方面中,本发明的一个实施例包括:a)旋涂(spinning)纳米颗粒并且通过有机溶液干燥它们,溶液由甲醇或者其它有机醇制成;b)用UV固化沉积下一级ULK;c)ULK蚀刻,继而在通过蚀刻来创建的打开区域处用有机溶剂去除纳米颗粒,使用DHF以清理溶剂和其它残留物;d)原位沉积TaN/Ta衬垫和Cu籽晶,继而电镀铜和退火;并且e)通过CMP去除过多(过量)Cu/衬垫,继而沉积SiCNH盖层层。
在又一方面中,本发明取代UV对盖层造成的损坏,该盖层在来自更高级的UV辐射之下变成拉伸,这造成在ULK/盖层界面形成破裂。引入双层低k盖层仅在某些UV条件内起作用,该盖层的厚度在UV辐射之下收缩。另外,尺度改变可能破坏BEOL结构的完整性。
在又一方面中,本发明的一个实施例提供一种多层结构,该结构包括:一个或者多个超低k(ULK)电介质层而每个交替ULK电介质层具有在其中形成的多个金属填充沟槽和过孔;盖层,覆盖和密封具有多个金属填充沟槽和过孔的ULK电介质层;以及纳米颗粒,在ULK电介质层与盖层之间的界面处形成单层。
在又一方面中,本发明提供一种形成多层结构的方法,该方法包括:形成一个或者多个超低k(ULK)电介质层而每个交替ULK电介质层具有在其中形成的多个金属填充沟槽和过孔;形成盖层,覆盖和密封具有多个金属填充沟槽和过孔的ULK电介质层;以及旋涂覆盖在ULK电介质层与每个盖层之间的界面处形成单层的纳米颗粒。
具体实施方式
现在将参照本申请附带的附图通过以下讨论更具体描述本发明。注意仅出于示例目的而提供本申请的附图。
下文将描述本发明的一个实施例。为了简化和清楚图示,在附图中示出的单元未必按比例绘制。例如一些单元的尺度可以相对于其它尺度而夸大以求清楚。
图6图示本发明结构的一个实施例,该结构包括在Cu层140上面的SiCNH盖层层130上面旋涂的纳米颗粒120,其中优选地通过有机溶液干燥纳米颗粒。SiCNH膜可以用范围在150A与500A之间的厚度来制成并且用来覆盖在下面的大马士革铜图案。在纳米颗粒之上旋涂的ULK层100优选地由厚度范围为500A-10000A的低K有机硅酸盐电介质(诸如SiCOH)制成。
纳米颗粒120优选地由金属氧化物(例如ZnO)制成。可以理解,可以有利地使用具有相似特性的其它材料,诸如TiO2等。纳米颗粒的优选直径范围在1nm与4nm之间。均匀旋涂(旋涂)纳米颗粒从而形成单层。已经示出可以包括甲醇、乙醇和更高醇的不同类型的醇溶液中成功合成ZnO或者TiO2纳米颗粒。
可以调整纳米颗粒的尺寸,以在某些波长频率时高效吸收UV辐射。如先前描述的那样,纳米颗粒的目的是保护SiCNH盖层免受UV射线辐射,因此保护盖层,以免将它的内部应力从压缩改变成拉伸。如沉积的盖层为压缩性。在曝光于UV辐射时,盖层如图2中先前所示变成拉伸。拉伸膜往往比压缩膜更容易破裂。盖层膜中的破裂可能在它与之接触的低模量ULK膜中引起破裂。纳米颗粒优选地被制成为具有多分布尺寸(主要为1nm至4nm),从而可以高效吸收多数UV。
峰值吸收如先前参照图5所示随颗粒尺寸而变化。吸收峰值随着颗粒尺寸由于量子限制效果而减少移向更短波长。旨在于吸收波长比约400nm更短的辐射,其中UV灯泡如先前参照图1所示发出它的UV辐射的多数,并且其中SiCHN盖层具有吸收边缘。
纳米颗粒通过从共价带的顶部上至传导带的电子转变来吸收辐射。受激电子通常通过经过光学带隙中的缺陷状态的转变序列回落至共价带。所得光致发光光谱对于ZnO而言峰值约为550nm(可见光)。
参照图7,然后在所选位置处形成具有范围从40nm至1000nm的临界尺度(CD)的沟槽,这些沟槽的侧部通过衬垫170来加衬,该衬垫优选地、但不限于由Ta/TaN制成并且具有近似10nm或者更少的厚度。然后例如使用溅射、优选地用PVD(物理气相沉积)Cu籽晶涂覆沟槽,这些沟槽的厚度具有约100nm或者更少这一量级的厚度。在这之后进行电镀铜填充180。
将这样形成的结构转换成多级互连配置。在纳米颗粒单层120(即具有范围为1nm-4nm的尺寸)上面优选地使用PECVD、继而为UV固化来沉积与先前超低k层相似的新超低k层100’。如先前描述的那样,可以再次通过添加沟槽和过孔以提供附加互连或者通过将Cu连接到先前级来变更上ULK级。
参照图8说明前文,该图图示通过ULK蚀刻上级、在通过RIE蚀刻来创建的打开区域处优选地用有机溶剂去除纳米颗粒、继而通过DHF(稀释氢氟酸)以清理溶剂和其它残留物。有利地通过向顶级提供出于光刻目的而优选地使用PECVD来形成的TEOS硬掩模(HM)沉积160来实现该工艺。TEOS HM的厚度可以优选地范围从15nm至50nm。在图8中也描绘示出通过蚀刻来形成的若干沟槽150和过孔155,该蚀刻包括纳米颗粒的选择性的去除,其中需要与第一ULK衬底中的镀Cu沟槽接触。这样形成的附加沟槽的目的是使得有可能形成VLSI芯片所必需的多级互连网络。
参照图9,示出先前描述的TEOS HM沉积160具有原位TaN/Ta衬垫沉积185、继而进行Cu籽晶沉积和ECP铜190、填充沟槽和过孔以及退火。优选地使用CMP来平坦化这样形成的结构。电化学镀制用来用铜填充双大马士革沟槽、通常在室温(25℃)执行。使用物理沉积技术(诸如溅射)来沉积由铜合金(即铝、镁或者其它合金元素)构成的籽晶层。
参照图10,示出在低k与SiCNH盖层之间有纳米颗粒的最终BEOL堆叠物的方案。通过CMP抛光和平坦化该结构。在该工艺之后是SiCNH盖层沉积。可以在SiCNH盖层覆盖的ULK层的每个后续组合上面形成附加纳米颗粒单层,由此创建多级结构。
概括而言,本说明书描述一种通常为15至22级这一量级的用于创建BEOL堆叠物的多级结构。用于形成堆叠物的每级的优选工艺包括:
1.旋涂纳米颗粒并且干燥溶液;
2.沉积下一级ULK,继而进行UV固化;
3.线或者过孔的光刻图案化;
4.通过蚀刻向ULK电介质中转移线或者过孔图案;
5.用有机溶剂在打开区域(即通过RIE工艺形成的打开区域,其中在ULK膜中打开线和过孔)的底部去除纳米颗粒;
6.稀释HF(DHF)清洗溶剂和RIE残留物;
7.通过物理气相沉积(PVD)原位沉积TaN/Ta衬垫和Cu籽晶,继而进行电化学镀制(ECP)铜并且退火所述Cu;
8.CMP过多的铜和衬垫;
9.沉积SiCNH盖层;并且
10.返回到步骤1。
尽管已经参照本发明的优选实施例具体示出和描述本发明,但是本领域技术人员将理解可以进行形式和细节上的前述和其它改变而未脱离本发明的精神实质和范围。因此旨在于本发明不限于描述和图示的确切形式和细节、但是落入所附权利要求的范围内。
工业适用性
本发明发现在集成电路芯片中并入的高性能半导体场效应晶体管(FET)器件的设计和制作中的工业适用性,这些集成电路芯片发现在大量多种电子和电气装置中的应用。

Claims (25)

1.一种多层半导体结构,包括:
一个或者多个超低k(ULK)电介质层100,而每个交替ULK电介质层具有在其中形成的多个金属填充沟槽和过孔;
盖层130,覆盖和密封具有所述多个金属填充沟槽180和过孔150的所述ULK电介质层100;以及
纳米颗粒120,在所述ULK电介质层与所述盖层之间的界面处形成单层。
2.如权利要求1所述的多层结构,其中所述纳米颗粒为多尺寸。
3.如权利要求2所述的多层结构,其中在所述盖层与所述ULK层之间插入的所述纳米颗粒在ULK固化期间衰减和吸收UV辐射。
4.如权利要求1所述的多层结构,其中在化学溶液中合成所述纳米颗粒,并且随后通过去除所述溶液来干燥所述纳米颗粒。
5.如权利要求4所述的多层结构,其中所述溶液是有机的,所述溶液包括甲醇、乙醇和更高醇。
6.如权利要求1所述的多层结构,其中所述纳米颗粒的尺寸在1nm与4nm之间变化。
7.如权利要求1所述的多层结构,还包括具有多分布尺寸以吸收波长范围在200nm与600nm之间的UV的所述纳米颗粒。
8.如权利要求1所述的多层结构,其中所述纳米颗粒在损坏影响所述盖层之前吸收UV光。
9.如权利要求1所述的多层结构,其中所述纳米颗粒由金属氧化物制成。
10.如权利要求9所述的多层结构,其中所述金属氧化物是ZnO或者TiO2
11.如权利要求1所述的多层结构,其中在所述盖层上均匀旋涂所述纳米颗粒。
12.一种形成多层结构的方法,包括:
形成一个或者多个超低k(ULK)电介质层100,而每个交替ULK电介质层具有在其中形成的多个金属填充沟槽180和过孔155,
形成盖层130,所述盖层130覆盖和密封具有所述多个金属填充沟槽180和过孔155的所述ULK电介质层;并且
旋涂覆盖纳米颗粒120,所述纳米颗粒120在所述ULK电介质层与每个所述盖层130之间的界面处形成单层。
13.如权利要求12所述的方法,还包括:
a.在所述纳米颗粒上旋涂溶液,继而进行从溶剂干燥出所述纳米颗粒;
b.用UV固化沉积下一级ULK;
c.蚀刻所述ULK并且从蚀刻的打开区域去除所述纳米颗粒;
d.沉积难熔衬垫185和传导层,继而进行电镀铜填充所述打开区域,继而进行退火;
e.抛光所述衬垫和传导层;并且
f.在其上沉积电介质盖层。
14.如权利要求13所述的方法,其中所述传导层由Cu或者Cu合金制成。
15.如权利要求13所述的方法,其中所述电介质盖层由SiCHN制成。
16.如权利要求13所述的方法,其中通过加热来执行所述干燥。
17.如权利要求13所述的方法,其中使用有机溶剂来执行所述纳米颗粒的所述干燥。
18.如权利要求13所述的方法,其中在所述抛光之后是清理所述溶剂和其它残留物。
19.如权利要求13所述的方法,其中所述难熔衬垫由TaN、Ta、W、WNx、TiNx、Ru或者Co制成。
20.如权利要求18所述的方法,其中使用稀释氢氟酸(DHF)来执行清理所述溶剂和残留物。
21.如权利要求12所述的方法,其中通过电化学镀制执行所述沟槽填充。
22.如权利要求13所述的方法,其中通过化学机械抛光(CMP)执行所述抛光。
23.如权利要求13所述的方法,还包括固化所述超低k(ULK)电介质。
24.如权利要求13所述的方法,其中辐射穿透经过所述ULK电介质,从而到达所述盖层。
25.一种形成多级后端工艺(BEOL)堆叠物的方法,每级包括:
旋涂包含纳米颗粒120的溶液,继而进行干燥所述溶液;
形成ULK电介质层100,继而进行UV固化;
光刻图案化线或者过孔155;
通过蚀刻向所述ULK电介质层100中转移所述图案化的线或者过孔;
在通过用有机溶剂冲洗来创建的打开区域的底部去除所述纳米颗粒120;
通过涂敷DHF并且清洗所述溶剂和所述蚀刻残留物进行表面清理;
形成由TaN、Ta、W、WNx、TiNx、Ru、Co制成的衬垫185,继而进行Cu或者Cu合金沉积190,继而进行所述Cu的电化学工艺,继而进行退火所述Cu;并且
应用所述过多铜和衬垫的化学机械抛光;并且沉积SiCNH盖层130。
CN2011800432052A 2010-09-20 2011-08-10 提高具有纳米颗粒的半导体互连的机械性质的方法 Pending CN103180933A (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US12/885,596 2010-09-20
US12/885,596 US8129269B1 (en) 2010-09-20 2010-09-20 Method of improving mechanical properties of semiconductor interconnects with nanoparticles
PCT/US2011/047152 WO2012039850A2 (en) 2010-09-20 2011-08-10 Method of improving mechanical properties of semiconductor interconnects with nanoparticles

Publications (1)

Publication Number Publication Date
CN103180933A true CN103180933A (zh) 2013-06-26

Family

ID=45757901

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2011800432052A Pending CN103180933A (zh) 2010-09-20 2011-08-10 提高具有纳米颗粒的半导体互连的机械性质的方法

Country Status (5)

Country Link
US (2) US8129269B1 (zh)
CN (1) CN103180933A (zh)
DE (1) DE112011103146B4 (zh)
GB (1) GB2497485B (zh)
WO (1) WO2012039850A2 (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104658967A (zh) * 2013-11-21 2015-05-27 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制造方法
CN110972403A (zh) * 2019-12-04 2020-04-07 广东工业大学 一种基于纳米铜的精细嵌入式线路的成型方法

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120235304A1 (en) * 2011-03-18 2012-09-20 Globalfoundries Inc. Ultraviolet (uv)-reflecting film for beol processing
US8461683B2 (en) * 2011-04-01 2013-06-11 Intel Corporation Self-forming, self-aligned barriers for back-end interconnects and methods of making same
US9367654B2 (en) * 2013-02-28 2016-06-14 Taiwan Semiconductor Manufacturing Company Limited Variation modeling
CN104112700B (zh) * 2013-04-18 2017-03-29 中芯国际集成电路制造(上海)有限公司 一种改善金属互连工艺中线路断裂缺陷的方法
US20150357236A1 (en) 2014-06-08 2015-12-10 International Business Machines Corporation Ultrathin Multilayer Metal Alloy Liner for Nano Cu Interconnects
KR102491577B1 (ko) 2015-09-23 2023-01-25 삼성전자주식회사 유전 층을 갖는 반도체 소자 형성 방법 및 관련된 시스템
US9768061B1 (en) * 2016-05-31 2017-09-19 Taiwan Semiconductor Manufacturing Co., Ltd. Low-k dielectric interconnect systems
US10211153B2 (en) * 2016-08-30 2019-02-19 International Business Machines Corporation Low aspect ratio interconnect
EP3633431A1 (en) * 2018-10-05 2020-04-08 Indigo Diabetes N.V. Weld protection for hermetic wafer-level sealing
US10679892B1 (en) * 2019-02-28 2020-06-09 International Business Machines Corporation Multi-buried ULK field in BEOL structure

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008033227A2 (en) * 2006-09-11 2008-03-20 Applied Nano Works, Inc. Optically clear nanoparticle colloidal suspensions and method of making thereof
US20080122103A1 (en) * 2006-11-29 2008-05-29 International Business Machines Corporation Embedded nano uv blocking barrier for improved reliability of copper/ultra low k interlevel dielectric electronic devices

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6930034B2 (en) * 2002-12-27 2005-08-16 International Business Machines Corporation Robust ultra-low k interconnect structures using bridge-then-metallization fabrication sequence
US7253125B1 (en) 2004-04-16 2007-08-07 Novellus Systems, Inc. Method to improve mechanical strength of low-k dielectric film using modulated UV exposure
US7367739B2 (en) * 2004-08-02 2008-05-06 Clark Equipment Company Two component seal
JP2006161969A (ja) * 2004-12-08 2006-06-22 Toyota Industries Corp 軸受部のシール方法及びシール装置
US7166531B1 (en) * 2005-01-31 2007-01-23 Novellus Systems, Inc. VLSI fabrication processes for introducing pores into dielectric materials
WO2006081664A1 (en) * 2005-02-03 2006-08-10 Héroux-Devtek Inc. Alternative uplock release assembly
KR101329143B1 (ko) 2007-01-10 2013-11-20 삼성전자주식회사 금속 나노입자를 이용한 자외선 차단 재료
WO2009102363A2 (en) * 2007-11-15 2009-08-20 Stc.Unm Ultra-thin microporous/hybrid materials
US20090258230A1 (en) 2008-04-11 2009-10-15 Kobo Products, Inc. Porous and/or hollow material containing uv attenuating nanoparticles, method of production and use

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008033227A2 (en) * 2006-09-11 2008-03-20 Applied Nano Works, Inc. Optically clear nanoparticle colloidal suspensions and method of making thereof
US20080122103A1 (en) * 2006-11-29 2008-05-29 International Business Machines Corporation Embedded nano uv blocking barrier for improved reliability of copper/ultra low k interlevel dielectric electronic devices

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
刘娅莉等: "无机纳米粒子在涂料中的应用及其进展", 《现代涂料与涂装》, 31 March 2002 (2002-03-31) *

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104658967A (zh) * 2013-11-21 2015-05-27 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制造方法
CN104658967B (zh) * 2013-11-21 2017-10-20 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制造方法
CN110972403A (zh) * 2019-12-04 2020-04-07 广东工业大学 一种基于纳米铜的精细嵌入式线路的成型方法

Also Published As

Publication number Publication date
US8129269B1 (en) 2012-03-06
WO2012039850A3 (en) 2012-06-07
GB2497485A (en) 2013-06-12
US20120146224A1 (en) 2012-06-14
DE112011103146T5 (de) 2013-07-25
WO2012039850A2 (en) 2012-03-29
DE112011103146B4 (de) 2015-02-26
US8384219B2 (en) 2013-02-26
US20120068315A1 (en) 2012-03-22
GB2497485B (en) 2014-12-24
GB201305611D0 (en) 2013-05-15

Similar Documents

Publication Publication Date Title
CN103180933A (zh) 提高具有纳米颗粒的半导体互连的机械性质的方法
US7541276B2 (en) Methods for forming dual damascene wiring for semiconductor devices using protective via capping layer
TWI233181B (en) Very low effective dielectric constant interconnect Structures and methods for fabricating the same
US10170396B2 (en) Through via structure extending to metallization layer
CN105374745B (zh) 制造后段制程中间层结构的方法
US9613880B2 (en) Semiconductor structure and fabrication method thereof
US10062645B2 (en) Interconnect structure for semiconductor devices
TW201810591A (zh) 半導體裝置與其形成方法
TW201011861A (en) Method for fabricating integrated circuit
US8212330B2 (en) Process for improving the reliability of interconnect structures and resulting structure
US9059259B2 (en) Hard mask for back-end-of-line (BEOL) interconnect structure
TWI608541B (zh) 空氣隙互聯結構之形成方法
US9870944B2 (en) Back-end-of-line (BEOL) interconnect structure
TW201724436A (zh) 互連線結構與其製造方法
US20070080461A1 (en) Ultra low-k dielectric in damascene structures
US20080171442A1 (en) Metal interconnect structure and process for forming same
KR101842903B1 (ko) 에어 갭 상호연결 구조의 형성 방법
US20210335706A1 (en) Semiconductor device including a porous dielectric layer, and method of forming the semiconductor device
CN104425357A (zh) 双镶嵌结构的形成方法
US20060118955A1 (en) Robust copper interconnection structure and fabrication method thereof
US9153538B2 (en) Semiconductor devices and methods of manufacture thereof
JP2004296620A (ja) 半導体装置の製造方法
KR20080022383A (ko) 반도체 소자의 금속 배선 형성 방법
KR20020090441A (ko) 반도체 소자의 구리배선 형성방법

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication

Application publication date: 20130626

RJ01 Rejection of invention patent application after publication