CN103259529B - A kind of integrated circuit adopting carry skip chain - Google Patents
A kind of integrated circuit adopting carry skip chain Download PDFInfo
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- CN103259529B CN103259529B CN201210038130.5A CN201210038130A CN103259529B CN 103259529 B CN103259529 B CN 103259529B CN 201210038130 A CN201210038130 A CN 201210038130A CN 103259529 B CN103259529 B CN 103259529B
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Abstract
The embodiment of the present invention discloses a kind of integrated circuit adopting carry skip.This integrated circuit comprises multiple look-up table unit with carry function, carry skip input unit and jump output unit; Wherein, carry skip output unit produces according to the Output rusults of described multiple look-up table unit and selects signal, for one of carry signal that carry skip input unit selects input carry signal and multiple look-up table unit to produce as carry signal.The carry skip of the embodiment of the present invention all has very important significance for the lifting of addition and subtraction performance and the lifting of overall system performance.
Description
Technical field
The present invention relates to integrated circuit fields, particularly relate to the carry chain in a kind of FPGA.
Background technology
Many application requirement integrated circuits are had to have able to programme or configurable interference networks.Such application is field programmable gate array (Fieldprogrammablegatearray is called for short FPGA), and wherein, gate is connected to each other by configurable interference networks.The FPGA worked as core in individual chips or system has extensively been applied in a large amount of microelectronic device.
In the middle of the design of FPGA, carry chain is a kind of very common structure, for realizing the basic operation such as addition, subtraction.The carry chain of major part FPGA all adopts the ripple carrier chain (ripplecarrychain) of main flow, the carry of every one-level exports the carry all depending on previous stage and exports, the feature of this carry chain is that structure is simple, be convenient to realize, but when user design addition or subtraction bit wide very large time, carry chain can be caused very long, and time delay is larger.
Due to FPGA application more and more extensively and function from strength to strength, its logical block held or logical block also get more and more, and delay phenomenon more and more becomes the problem needing special concern.
Summary of the invention
The embodiment of the present invention provides a kind of integrated circuit that can overcome the problems referred to above.This integrated circuit comprises multiple look-up table unit with carry function, carry skip input unit and jump output unit; Wherein, carry skip output unit produces according to the Output rusults of described multiple look-up table unit and selects signal, for one of carry signal that carry skip input unit selects input carry signal and multiple look-up table unit to produce as carry signal.
Preferably, carry skip input unit inputs from the carry of look-up table unit place logical block, selects an input signal as carry chain the carry signal from other logical block and the carry skip signal from other logical block.
Preferably, look-up table unit comprises look-up table, MUX and XOR gate; The output of look-up table is connected to the first input end of XOR gate and the selection control end of MUX; The first input end of MUX and the second input of XOR gate are connected to carry signal input; Second input of MUX is connected to the first input end of look-up table.Further preferably, the second input of MUX is also coupled to the output of another look-up table unit.
Carry skip chain structure is introduced in the middle of the integrated circuit (IC) design of such as FPGA by the embodiment of the present invention, can avoid the carry chain occurring growing very much, the effective time delay reducing carry chain.The carry skip of the embodiment of the present invention all has very important significance for the lifting of addition and subtraction performance and the lifting of overall system performance.
Accompanying drawing explanation
Below by drawings and Examples, technical scheme of the present invention is described in further detail.In accompanying drawing,
Fig. 1 illustrates the structure chart of the system having flush system (Tile-based) FPGA (Field Programmable Gate Array) and interconnecting unit;
Figure 2 shows that the basic composition structure chart of basic logic unit LE;
Fig. 3 illustrates the general principle of carry skip of the present invention (carryskip);
Fig. 4 is the carry skip chain of LE;
Fig. 5 is that the basic structure of the LUT4C of band carry chain structure is shown;
Fig. 6 is the detailed construction schematic diagram of carry skip chain;
Fig. 7 is for realize an example of 12 additions and the analysis schematic diagram of critical path thereof by carry skip chain (carryskipchain);
Figure 8 shows that and realize an example of 16 additions and the analysis schematic diagram of critical path thereof by carry skip chain;
Fig. 9 is that the structural diagrams realizing multidigit and function by carry chain is intended to.
Embodiment
Fig. 1 illustrates the structure chart of the system having flush system (Tile-based) FPGA (Field Programmable Gate Array) and interconnecting unit.As shown in Figure 1, this system comprises: configurable logic array (Configurablelogicarray), embedded adder and multiplier (MAC), in-line memory (EMB), phase-locked loop (PLL) and input and output IO etc.Can also comprise in some SOC (system on a chip) (SOC): flush bonding processor (ARM/8051/MIPS), code data memory (SRAM/Flash) etc.
In figure, enlarged fragmentary portion is depicted as FPGA (Field Programmable Gate Array) and the interconnection structure of typical Tile-based.The FPGA (Field Programmable Gate Array) of this tile-based and interconnection structure are made up of basic tile unit: PLB (programmablelogicblock, programmable logic block).PLB is made up of basic logic unit (LE) and basic interconnection unit (xbar).Wherein LE is made up of such as 4 LP (LogicParcel, logic chip).Take PLB as the programmable logic array that elementary cell can be combined as arbitrary size; The IP of more additional specific functions, as Embedded memory (EMB), embedded adder and multiplier (MAC), the IO of specific function, can form a typical FPGA system.
Fig. 2 is the basic composition structure chart of basic logic unit LE.LE is by such as 4 LP (Logicparcel, logic chip), and jump input unit (carryskipin), jump output unit (carryskipout) and LBUF form.
Each LP comprises such as 2 LUT4,1 LUT4C (LUT4 of band carry chain) and 2 registers.As shown in the figure, LP0, LP1, LP2, LP3 all comprise two LUT4 and LUT4C, and 2 register REG.LE has such as 12 LUT4 and 8 registers altogether, the ratio of LUT4 and register is such as 3:2, consider the major applications of FPGA, the resource consumption of combinational logic part is larger than sequential logic part, the resource of LUT4 than register aboundresources some, can area be saved, improve the utilance of chip simultaneously.
Carry skip input unit and carry skip output unit are used for realizing carry skip chain function.When LBUF is used for the control signal of register in LE, the generation of clock, does not have direct relation with the present invention, does not repeat again.
It may be noted that in this manual, logic chip is only the one segmentation of logical block.The present invention is not restricted to the integrated circuit with logic chip, also should contain the integrated circuit with various logic unit embodying thinking of the present invention.
Fig. 3 illustrates the general principle of carry skip of the present invention (carryskip).The figure first half is depicted as the basic structure of 4 full adders.Full adder comprises adder FA0, adder FA1, adder FA2 and adder FA3.Adder FA0, adder FA1, between adder FA2 and adder FA3, there is carry chain.
Specifically, adder FA0 receives carry at input and generates signal G0 and carry propagation signal P0 and the carry signal Ci0 from previous full adder, and produces new carry signal Co0 based on these signals; Carry signal Co0 is input to adder FA1.Adder FA1 docking is taken in position generation signal G1 and carry propagation signal P1 and carry signal Co0 and is produced new carry signal Co1; Carry signal Co1 is input to adder FA2.Adder FA2 receives carry generation signal G2 and carry propagation signal P2 and carry signal Co1 and produces new carry signal Co2; Carry signal Co2 is input to adder FA3.Adder FA3 receives carry generation signal G3 and carry propagation signal P3 and carry signal Co2 and produces new carry signal Co3.Carry signal Co3 as four full adders carry export and export.The output of each full adder of this structure depends on the carry chain output of previous full adder.
Coi＝Gi+PiCi
Gi＝AiBi,Pi＝(Ai^Bi)
If increase a MUX in the structure of this full adder, the full adder structure shown in figure Lower Half just can be obtained.When P0, P1, P2, P3 are 1, carry chain exports and the input of carry chain is identical, and MUX selects original input as the output of this carry chain.That is, this feature can be utilized to realize the carry chain structure of jumping.
Because in above-mentioned calculating process, the generation of carry skip signal is only relevant with Gi with Pi, be not produce prerequisite with Coi, therefore arithmetic speed improves, and postpones also significantly to reduce.
Although it may be noted that mainly invention has been described in conjunction with addition in this manual, the present invention equally also goes for subtraction.
Fig. 4 is the carry skip chain structure of LE.As shown in Figure 4, carry skip chain comprises carry chain three parts in jump input unit and jump output unit and LE between multiple LUT4C.Illustrate 4 LUT4C in the drawings.4 LUT4C can be coupled together by ripple carrier chain (ripplecarrychain); Connected by carry skip chain between LE, the high-speed carry of such as 4 and the high-speed carry of such as 8 can be realized thus.For neighbouring two LE, below the output of jump output unit of LE can be directly connected to the input of the jump input unit of LE above.
Generation, as the look-up table of routine, outputs signal by LUT4C, and is exported by the corresponding port of multiplexer mux_dy in port dy [0], dy [1], dy [2], dy [3].The carry that signed magnitude arithmetic(al) obtains also is transmitted by carry chain by LUT4C, and exports through c4_out.
The effect of jump input unit is as current LE selects suitable carry input.The input of jump input unit divides three groups: one group to be the local carry input of current LE, comprises the outside input (byp [4], byp [16]) in gnd and two, ground; One group be LE below carry chain input: c4_in, c_skip4_in, c_skip8_in; Another group is the output of the jump output unit of LE below: r4_in_b, p4_in_b, p8_in_b, the selection signal that the carry chain as current LE inputs.The output of jump input unit is the carry chain input of current LE.Under the control selecting signal, jump input unit from the input of local carry and below LE carry chain input select a signal to input as the carry of current LE.
Above the effect of jump output unit is, the adjacent LE in (i.e. the downstream of carry chain) provides the selection signal of carry signal.The input of jump output unit is divided into two groups: one group to be the output of 4 LUT4C, and another signal is the same input signal shared with jump input unit: p4_in_b, this signal can indicate adjacent LE below and whether the carry skip of 4 occurs.It exports when the input signal as the jump input unit of LE above, i.e. carry select signal r4_in_b, jumps 4 and selects signal p4_in_b, jumps 8 selections signal p8_in_b (carry skip selection signal).
After four LUT4C of current LE carry out add operation when output output is the signal of 1 entirely, jump output unit produces effective selection signal p4_in_b.When this selection invalidating signal, the c4_out of current LE is selected to input as the carry of its LE in the jump input unit of LE above; When this selection signal is effective, c_skip4_out or c_skip8_out of current LE is selected to input as the carry of its LE in the jump input unit of LE above.
Fig. 5 is the basic structure schematic diagram of the LUT4C of band carry chain structure.As shown in Figure 5, the carry chain between LUT4C is ripple carrier chain structure.The structure of this carry chain mainly comprises: XOR gate (xor) for obtaining the output of addition, multiplexer mux_co and multiplexer mux_ca.
LUT40, XOR gate and multiplexer mux_co realize the signed magnitude arithmetic(al) of band carry.The f2 input of LUT40 is coupled to the first input end of multiplexer mux_co, input carry signal ci is input to second input of multiplexer mux_co and the second input of XOR gate, and the first input end of XOR gate receives the output signal from LUT40.The output signal of LUT40 is also as the selection control end input signal of multiplexer mux_co.
The input of multiplexer mux_ca can be GND, directly inputs, the output of LUT0 or the input of LUT40.Different according to the selection of mux_ca, different functions can be realized.When selecting the input of directly input or LUT40, basic signed magnitude arithmetic(al) can be realized; When selecting the output of GND or LUT0, can realize multi input with or function.
It may be noted that the LUT of other form band carry chain adopted beyond Fig. 5 in embodiments of the present invention is also feasible.
Fig. 6 is the detailed construction schematic diagram of carry skip chain.The basic structure for jump input unit of left side signal, right side is illustrated as the basic structure of jump output unit.
For jump input unit, by MUX mux0, the function being realized carry chain by carry skip chain or ripple carrier chain can be selected.When realizing the addition and subtraction of multidigit, carry skip chain can be selected.When realized by carry chain multidigit with or function time, can be realized by ripple carrier chain.
When selecting carry skip chain, by carry select signal r4_in_b, jump 4 and select signal p4_in_b, jump 8 and select signal p8_in_b to decide option value signal c4_in, jump 4 carry signal c_skip4_in and still jump the input of 8 carry signal c_skip8_in as carry chain.In addition, the input that the initial input for carry chain can be selected constant by MUX mux1 and mux5 or directly be inputted as lowest order carry chain, and can determine whether will inputting negate to carry chain by MUX mux4.
When selecting ripple carrier chain, decided the input selected constant or directly input as lowest order carry chain by MUX mux2, mux4, mux5, and can determine whether negate is inputted to carry.
For jump output unit, it is input as the output of 4 LUT4C connected through pulsation carry chain and selects signal p4_in_b with the input jumping 4 that jump input unit is shared.When the output of 4 LUT4C is 1 entirely, and jump 4 when to select into signal p4_in_b as high (last carry chain jump 4 carry signals invalid), jumping 4, to select signal p4_out_b signal effective, can realize the carry skip of 4.Be 1 entirely when 4 LUT4C export, and when jumping 4 to select into signal p4_in_b be low (last carry chain jump 4 carry signals effective), jumping 8, to select signal p8_out_b signal effective, can realize the carry skip of 8.When 4 LUT4C outputs are not 1 entirely, it is effective that carry select goes out signal r4_out_b, realizes ripple carrier.
It may be noted that Fig. 6 only illustrates an example of jump input unit, jump output unit.Those skilled in the art will recognize that, the replacement circuit of other form can be adopted to realize jump input unit, jump output unit.
The ripple carrier chain of jump input unit, jump output unit and 4 is combined, common ripple carrier chain function can be realized, the carry skip of 4 and 8, this carry skip all has very important significance for the lifting of addition and subtraction performance and the lifting of overall system performance.
Fig. 7 realizes an example of 12 additions and the analysis schematic diagram of critical path thereof by carry skip chain.As shown in the figure, the addition completing 12 needs 3 LE, LE0, LE1 and LE2.Each LE realizes the addition of 4.
Wherein, LE0 carries out add operation to 0-3 position, A [3:0] and B [3:0] is added, must with Sum [3:0]; LE1 carries out add operation to 4-7 position, A [7:4] and B [7:4] is added, must with Sum [7:4]; LE2 carries out add operation to 8-11 position, A [11:8] and B [11:8] is added, must with Sum [11:8].
4 LUT4C of LE inside are connected by ripple carrier chain, and the details on the right side of figure to LE0 has been done and amplified signal.Be connected with the carry skip chain structure of jump output unit by jump input unit between LE.
Realized the addition of 12 by carry skip chain structure, its critical path as shown in the figure.The time delay of critical path is made up of the ripple carrier chain time delay of 24 grades and the carry skip chain time delay (carryskip4delay, hereinafter referred to as the time delay of jumping 4 carry) of 14.Compared to the ripple carrier chain time delay of 12 grades, performance is greatly improved.
Fig. 8 realizes an example of 16 additions and the analysis schematic diagram of critical path thereof by carry skip chain.Can see that the addition of 16 needs 4 LE, each LE realizes the addition of 4.4 LUT4C of LE inside are connected by ripple carrier chain.Be connected with the carry skip chain structure of jump output unit by jump input unit between LE.
The addition of 16 is realized by carry skip chain structure.The time delay of critical path is made up of the ripple carrier chain time delay of 24 grades and the carry skip chain time delay (namely carryskip8delay jumps 8 carry time delays) of 18.Compared to the ripple carrier chain time delay of 16 grades, performance is greatly improved.
Fig. 9 is that the structural diagrams realizing multidigit and function by carry chain is intended to.The structure of the LUT4C according to Fig. 9, the output of LUT0 can as the input of MUX mux_ca, such LUT40 and LUT0 can by mux_co couple together realize 8 with or function.
As shown in the figure, 8 can be exported by carry chain with the output of function, and in LP0, two LUT4 are in conjunction with MUX mux_ca, mux_co, then through the MUX mux_sc of LP1 and mux_dy, can obtain 8 and output AND8.
Fig. 9 give one 16 with the implementation structure figure of function, in a LP by carry chain structure can realize 8 and/or function, can realize at most in LE 20 and/or function, but all this with or function all exported by carry chain, therefore all need multiplexer mux_sc and mux_dy using the LP be adjacent to export.
Above-described embodiment, further describes object of the present invention, technical scheme and beneficial effect.Institute it should be understood that and the foregoing is only the specific embodiment of the present invention, the protection range be not intended to limit the present invention.Within the spirit and principles in the present invention all, any amendment made, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (2)
1. an integrated circuit, comprises multiple LE, and each LE comprises multiple look-up table unit with carry function, carry skip input unit and jump output unit; Described multiple LE comprises a LE adjacent one another are and the 2nd LE, and a LE is positioned at the downstream of the 2nd LE; Wherein, carry skip output unit in 2nd LE produces carry select signal according to the described multiple Output rusults with the look-up table unit of carry function in the 2nd LE and signal is selected in carry skip, carry skip input unit in one LE selects signal according to from the carry select signal of the 2nd LE and carry skip, selects one of carry signal produced from the multiple look-up table unit with carry function in the carry skip signal of the 2nd LE and the 2nd LE as carry signal.
2. integrated circuit as claimed in claim 1, wherein said multiple LE comprises the 3rd LE, and the 3rd LE is positioned at the upstream of a LE; Carry skip signal comprises jumping 4 carry signal and jumps 8 carry signals; The described carry skip from the 2nd LE selects signal effectively effectively to be determined with the output with the look-up table of carry chain of the 2nd LE according to jumping 4 carry signal from the 3rd LE by the 2nd LE.
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| US9590633B2 (en) * | 2014-12-11 | 2017-03-07 | Capital Microelectronics Co., Ltd. | Carry-skip one-bit full adder and FPGA device |
| CN106934077B (en) * | 2015-12-29 | 2020-06-16 | 京微雅格（北京）科技有限公司 | Precise block carry chain time sequence analysis method |
| CN109992255B (en) * | 2019-03-07 | 2022-06-24 | 中科亿海微电子科技（苏州）有限公司 | Dual-output lookup table with carry chain structure and programmable logic unit |
| CN110265002B (en) * | 2019-06-04 | 2021-07-23 | 北京清微智能科技有限公司 | Speech recognition method, speech recognition device, computer equipment and computer readable storage medium |
| CN112949830B (en) * | 2021-03-09 | 2022-12-06 | 合肥辉羲智能科技有限公司 | Intelligent inference network system and addition unit and pooling unit circuitry |
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| US7185035B1 (en) * | 2003-10-23 | 2007-02-27 | Altera Corporation | Arithmetic structures for programmable logic devices |
| US7256612B1 (en) * | 2005-06-14 | 2007-08-14 | Xilinx, Inc. | Programmable logic block providing carry chain with programmable initialization values |
| CN101312347A (en) * | 2007-05-21 | 2008-11-26 | 阿尔特拉公司 | a programmable logic device having complex logic blocks with improved logic cell functionality |
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| US7185035B1 (en) * | 2003-10-23 | 2007-02-27 | Altera Corporation | Arithmetic structures for programmable logic devices |
| US7256612B1 (en) * | 2005-06-14 | 2007-08-14 | Xilinx, Inc. | Programmable logic block providing carry chain with programmable initialization values |
| CN101312347A (en) * | 2007-05-21 | 2008-11-26 | 阿尔特拉公司 | a programmable logic device having complex logic blocks with improved logic cell functionality |
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