CN103280508A - Wafer-level LED (Light Emitting Diode) packaging method - Google Patents
Wafer-level LED (Light Emitting Diode) packaging method Download PDFInfo
- Publication number
- CN103280508A CN103280508A CN2013101975485A CN201310197548A CN103280508A CN 103280508 A CN103280508 A CN 103280508A CN 2013101975485 A CN2013101975485 A CN 2013101975485A CN 201310197548 A CN201310197548 A CN 201310197548A CN 103280508 A CN103280508 A CN 103280508A
- Authority
- CN
- China
- Prior art keywords
- silica
- die cavity
- silicon
- wafer scale
- based die
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
Abstract
The invention relates to a wafer-level LED (Light Emitting Diode) packaging method, belonging to the technical field of semiconductor packaging. The method comprises the steps of providing an LED chip (100) with positive and negative electrodes (110); providing a silicon body (200) with a silicon-base cavity (210) on one surface and through silicon vias on the other surface; arranging conducting electrodes (300) in the silicon-base cavity (210); inversely installing the LED chip (100) on the conducting electrodes (300); filling a photoluminescence layer (400) in the silicon-base cavity (210), wherein the photoluminescence layer (400) covers the light emitting surface of the LED chip (100); and forming a single wafer-level LED packaging structure through a wafer cutting and separation method. The wafer-level LED packaging method provided by the invention has the advantages that the thermal resistance is low, the heat dissipating performance is good, the light emitting efficiency is improved, the packaging expense is low and the application scope of LEDs can be effectively widened.
Description
Technical field
The present invention relates to a kind of wafer scale LED method for packing, belong to the semiconductor packaging field.
Background technology
Entire society is high to the sound day of energy-saving and cost-reducing appealing, and engineering that country is also carrying out so-called " ten thousand in ten cities ", its purpose are effectively to reduce power consumption by advancing the LED lighting technology.Yet, compare with traditional fluorescent lamp tube, at present the packaging cost of LED itself is to carry out energy-saving and cost-reducing biggest obstacle, its price is 2-3 times of fluorescent tube, thus with fluorescent tube quite or more cheaply the LED lighting technology become the object that industry is chased.
LED encapsulation is at present mainly carried out with single form, is about to led chip after the cutting by on the mounted substrate (as metallic support, lead frame, ceramic substrate, metal substrate), then interconnected by going between, by a some glue; Because nearly all work step all is to carry out with single, production efficiency is lower, and production cost is than higher; Simultaneously, have the not high problem of radiating control difficulty, light efficiency, this has seriously restricted the application of LED.
Summary of the invention
The objective of the invention is to overcome the deficiency of current method for packing, provide that a kind of thermal resistance is low, perfect heat-dissipating, be lifted out optical efficiency, encapsulation overhead low, can effectively widen the wafer scale LED method for packing of the application of LED.
The object of the present invention is achieved like this: a kind of wafer scale LED method for packing comprises step:
Led chip with positive and negative electrode is provided;
Silicon body is provided, a surface of described silicon body arranges silica-based die cavity, described silica-based die cavity inwall and bottom deposit some layer insulatings, the surface of described insulating barrier forms the reflector, form the reflector opening on the reflector of described silica-based cavity bottom, in the described silica-based die cavity conductive electrode is set, described conductive electrode forms in the opening of reflector;
The carrier disk is provided, and bonding is carried out by the bonding material in the above-mentioned surface of described carrier disk and silicon body;
Another surface of described silica-based die cavity is by grinding, etching method forms several silicon through holes, some layers of insulating protective layer of deposition in the described silicon through hole, described insulating protective layer covers the above-mentioned surface of silicon body simultaneously, utilize photoetching, develop, method such as etching and/or laser drilling is with the insulation protection layer open of silicon via top, expose conductive electrode, cover the metallic circuit layer at insulating protective layer, described metallic circuit layer also covers the above-mentioned surface of the conductive electrode that exposes, and disconnect in the corresponding below in the both positive and negative polarity gap of electrode, apply the circuit sealer by photoetching process at the metallic circuit laminar surface, and optionally form circuit sealer opening;
By disk solution bonding technology the carrier disk from the silicon body sur-face peeling;
In silica-based die cavity, described electrode is connected with conductive electrode with the led chip upside-down mounting, fills the luminescence generated by light layer in the described silica-based die cavity, and described luminescence generated by light layer covers the exiting surface of led chip, and the exiting surface of described luminescence generated by light layer is plane, cambered surface or sphere;
Method by the wafer cutting and separating forms single wafer scale LED encapsulating structure.
Further, described conductive electrode is formed in the silica-based die cavity by sputter, photoetching and/or electroplating technology.
Further, described conductive electrode does not contact with the reflector.
Further, described silica-based die cavity forms by photoetching process and/or etching process.
Further, described insulating barrier adopts gluing or plasma enhanced chemical vapor deposition method to be deposited on silica-based die cavity inwall and bottom.
Further, described reflector adopts magnetron sputtering or electron beam evaporation method to be formed on the insulating barrier.
Further, described reflector opening forms in the reflector of silica-based cavity bottom by the technology of photoetching and/or corrosion.
Further, described insulating protective layer adopts gluing or plasma enhanced chemical vapor deposition method to be deposited on another surface of silicon body.
Further, described metallic circuit layer is covered on the insulating protective layer by sputter, photoetching and/or electric plating method.
Further, the described upside-down mounting mode mode that is upside-down mounting backflow or thermocompression bonding.
The invention has the beneficial effects as follows:
The positive and negative electrode of led chip of the present invention passes through the conductive electrode upside-down mounting in silica-based die cavity, the metallic circuit layer of filling in the silicon through hole that the face battle array that communicates with conductive electrode is arranged, increase area of dissipation, increased heat dissipation channel, reduced the thermal resistance of LED overall package, promote the radiating rate of led chip, improved reliability of products; The luminescence generated by light layer of the usefulness resin-encapsulated that the top of led chip arranges helps to improve the luminescence generated by light layer of light extraction efficiency, especially its spherical shape of led chip, also the beam angle of extending LED; Main technique of the present invention all realizes in the wafer scale mode, so production cost is lower, and package dimension can be littler, thereby can widen the application of LED effectively.
Description of drawings
Fig. 1 is the flow chart of a kind of wafer scale LED method for packing of the present invention.
Fig. 2 to Fig. 9 is the schematic diagram of a kind of wafer scale LED method for packing of one embodiment of the invention.
Among the figure:
Led chip 100
Electrode 110
Silica-based die cavity 210
Reflector opening 213
Silicon through hole 220
Insulating protective layer 221
Luminescence generated by light layer 400
Carrier disk T1
Bonding material T2.
Embodiment
Referring to Fig. 1, Fig. 1 is a kind of wafer scale LED method for packing of the present invention, and its technological process is as follows:
Execution in step S101: the led chip 100 that positive and negative electrode 110 is set is provided;
Execution in step S102: silicon body 200 is provided, and a surface of silicon body 200 arranges silica-based die cavity 210, and several conductive electrodes 300 are set in the silica-based die cavity 210, and another surface of silica-based die cavity 210 arranges silicon through hole 220;
Execution in step S103: with led chip 100 upside-down mountings on conductive electrode 300;
Execution in step S104: fill luminescence generated by light layer 400 in the silica-based die cavity 210, luminescence generated by light layer 400 covers the exiting surface of led chip 100;
Execution in step S105: the method by the wafer cutting and separating forms single wafer scale LED encapsulating structure.
The embodiment of a kind of wafer scale LED method for packing of the present invention
As shown in Figure 2, on silicon body 200, form the silica-based die cavity 210 that several led chips 100 are enough placed in the space by photoetching and/or etching technics, adopt gluing or plasma enhanced chemical vapor deposition method to deposit some layer insulatings 211 at silica-based die cavity 210 inwalls and bottom, the material of insulating barrier 211 can be inorganic insulating material or organic insulating materials such as silica gel, organic resin such as silica, silicon nitride.
As shown in Figure 3, adopt magnetron sputtering or electron beam evaporation method to form reflector 212 at silica-based die cavity 210 inwalls, open reflector opening 213 by the technology of photoetching and/or corrosion in the bottom of silica-based die cavity 210 again, and in reflector opening 213, form conductive electrode 300 by sputter, photoetching and/or electroplating technology.The material of conductive electrode 300 is copper/tin, gold/tin etc., and its shape, big I require to determine according to electrode 110 situations or the actual package of led chip 100.For improving reflectivity, can adopt material is the metallic reflector of metallic reflective material such as aluminium, titanium or silver.When adopting metallic reflector, for preventing led chip 100 short circuits, conductive electrode 300 does not contact with metallic reflector, can set up error-proof structure in case of necessity.
As shown in Figure 4, adopt the method for wafer bonding, silicon body 200 and carrier disk T1 are carried out interim bonding with bonding material T2.Carrier disk T1 can be transparent glass or common silicon chip; Bonding material T2 can be the organic gel class, also can be metal.
As shown in Figure 5, adopt to grind, etching method is at silicon body 200 back sides, several silicon through holes 220 are offered in the place of corresponding conductive electrode 300, silicon through hole 220 be shaped as straight hole, inclined hole or the shape of falling Y hole, illustrate with inclined hole among the figure.The top of silicon through hole 220 is the lower surface of conductive electrode 300, and 220 battle arrays of described silicon through hole are arranged and are covered with the back side of whole conductive electrode 300 corresponding silicon bodies 200; Adopt gluing or plasma enhanced chemical vapor deposition method deposition insulating protective layer 221 at silicon through hole 220 sidewalls and silicon body 200 back sides, the material of insulating protective layer 221 can be inorganic insulating material or organic insulating materials such as silica gel, organic resin such as silica, silicon nitride.
As shown in Figure 6; utilize the method for photoetching development, etching or laser drilling that the top insulating protective layer 221 of silicon through hole 220 is opened; expose conductive electrode 300; and then cover single or multiple lift metallic circuit layers 222 with sputter, photoetching and/or electric plating method at insulating protective layer 221; described metallic circuit layer 222 also covers the surface of the conductive electrode 300 that exposes; and disconnect in the below in the both positive and negative polarity gap of electrode 110, with positive and negative electrode 110 short circuits of avoiding led chip 100.Metallic circuit layer 222 transfers to the telecommunications breath of the led chip 100 on the conductive electrode 300 at the back side of silicon body 200.
As shown in Figure 7, at metallic circuit layer 222 surface-coated circuit sealer 223, and optionally form circuit sealer opening 224 by photoetching process.Circuit sealer 223 covers all silicon through hole 220 and peripheral spaces thereof, and circuit sealer opening 224 exposes the signal output part of metallic circuit layer 222, can realize welding according to the mode that attachment process is selected solder paste application or planted ball.Described metallic circuit layer 222 is the single or multiple lift metal, and its material is titanium/copper, titanium tungsten/copper, titanium tungsten/gold etc.
As shown in Figure 8, by disk solution bonding technology carrier disk T1 from silicon body 200 sur-face peelings; Adopt the mode of upside-down mounting backflow or thermocompression bonding that the electrode 110 on the led chip 100 is welded together with conductive electrode 300.
As shown in Figure 9, the technology that adopts mould that whole disk carried out the disk injection moulding, at the interior filling luminescence generated by light layer 400 of silica-based die cavity 210, luminescence generated by light layer 400 covers the exiting surface of led chip 100, and the exiting surface of luminescence generated by light layer 400 is plane, cambered surface or sphere.Described luminescence generated by light layer 400 is the mixed layer of organic silica gel and luminescence generated by light thing, and the bright dipping of concrete component after according to chip and encapsulation debugged, and purpose is to improve the light emission rate of LED.Wherein, the luminescence generated by light layer 400 of its protruding spherical shape beam angle of extending LED also especially, as shown in FIG..At last, the method by the wafer cutting and separating forms single wafer scale LED encapsulating structure.
The main technique of a kind of wafer scale LED method for packing proposed by the invention all realizes in the wafer scale mode, so production cost is lower, and package dimension can be littler, thereby can widen the application of LED effectively.
Claims (10)
1. wafer scale LED method for packing comprises step:
The have positive and negative electrode led chip (100) of (110) is provided;
Silicon body (200) is provided, a surface of described silicon body (200) arranges silica-based die cavity (210), described silica-based die cavity (210) inwall and bottom deposit some layer insulatings (211), the surface of described insulating barrier (211) forms reflector (212), the reflector (212) of described silica-based die cavity (210) bottom is gone up and is formed reflector opening (213), conductive electrode (300) is set in the described silica-based die cavity (210), and described conductive electrode (300) forms in the reflector opening (213);
Carrier disk (T1) is provided, and described carrier disk (T1) carries out bonding with the above-mentioned surface of silicon body (200) by bonding material (T2);
Another surface of described silica-based die cavity (210) is by grinding, etching method forms several silicon through holes (220), deposition some layers of insulating protective layer (221) in the described silicon through hole (220), described insulating protective layer (221) covers the above-mentioned surface of silicon body (200) simultaneously, utilize photoetching, develop, method such as etching and/or laser drilling is opened the insulating protective layer (221) at silicon through hole (220) top, expose conductive electrode (300), cover metallic circuit layer (222) at insulating protective layer (221), described metallic circuit layer (222) also covers the above-mentioned surface of the conductive electrode (300) that exposes, and disconnect in the corresponding below in the both positive and negative polarity gap of electrode (110), at metallic circuit layer (222) surface-coated circuit sealer (223), and optionally form circuit sealer opening (224) by photoetching process;
By disk solution bonding technology carrier disk (T1) from silicon body (200) sur-face peeling;
With led chip (100) upside-down mounting in silica-based die cavity (210), described electrode (110) is connected with conductive electrode (300), fill luminescence generated by light layer (400) in the described silica-based die cavity (210), described luminescence generated by light layer (400) covers the exiting surface of led chip (100), and the exiting surface of described luminescence generated by light layer (400) is plane, cambered surface or sphere;
Method by the wafer cutting and separating forms single wafer scale LED encapsulating structure.
2. a kind of wafer scale LED method for packing according to claim 1, it is characterized in that: described conductive electrode (300) is formed in the silica-based die cavity (210) by sputter, photoetching and/or electroplating technology.
3. a kind of wafer scale LED method for packing according to claim 1 and 2, it is characterized in that: described conductive electrode (300) does not contact with reflector (212).
4. a kind of wafer scale LED method for packing according to claim 1 is characterized in that: described silica-based die cavity (210) forms by photoetching process and/or etching process.
5. a kind of wafer scale LED method for packing according to claim 1 is characterized in that: described insulating barrier (211) adopts gluing or plasma enhanced chemical vapor deposition method to be deposited on silica-based die cavity (210) inwall and bottom.
6. a kind of wafer scale LED method for packing according to claim 1 is characterized in that: described reflector (212) adopt magnetron sputtering or electron beam evaporation method to be formed on the insulating barrier (211).
7. a kind of wafer scale LED method for packing according to claim 1 is characterized in that: the technology of described reflector opening (213) by photoetching and/or corrosion is in the formation of the reflector (212) of silica-based die cavity (210) bottom.
8. a kind of wafer scale LED method for packing according to claim 1 is characterized in that: described insulating protective layer (221) adopts gluing or plasma enhanced chemical vapor deposition method to be deposited on another surface of silicon body (200).
9. a kind of wafer scale LED method for packing according to claim 1, it is characterized in that: described metallic circuit layer (222) is covered on the insulating protective layer (221) by sputter, photoetching and/or electric plating method.
10. a kind of wafer scale LED method for packing according to claim 1, it is characterized in that: described upside-down mounting mode is the mode of upside-down mounting backflow or thermocompression bonding.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310197548.5A CN103280508B (en) | 2013-05-24 | 2013-05-24 | A kind of wafer scale LED encapsulation method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310197548.5A CN103280508B (en) | 2013-05-24 | 2013-05-24 | A kind of wafer scale LED encapsulation method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103280508A true CN103280508A (en) | 2013-09-04 |
| CN103280508B CN103280508B (en) | 2015-12-23 |
Family
ID=49062990
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310197548.5A Active CN103280508B (en) | 2013-05-24 | 2013-05-24 | A kind of wafer scale LED encapsulation method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103280508B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105720167A (en) * | 2014-08-08 | 2016-06-29 | 兆阳材料科技有限公司 | Packaging method of light emitting diode |
| CN110649142A (en) * | 2015-12-31 | 2020-01-03 | 晶元光电股份有限公司 | Light emitting device |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6531328B1 (en) * | 2001-10-11 | 2003-03-11 | Solidlite Corporation | Packaging of light-emitting diode |
| WO2007049938A1 (en) * | 2005-10-28 | 2007-05-03 | Amosense Co., Ltd. | Electronic parts packages and method for forming a cavity thereof |
| CN101807657A (en) * | 2009-02-18 | 2010-08-18 | Lg伊诺特有限公司 | Light emitting device package and lighting system including the same |
| CN102403413A (en) * | 2010-09-19 | 2012-04-04 | 常州普美电子科技有限公司 | LED (Light-Emitting Diode) heat dissipation base plate, LED packaging structure, and manufacturing method of LED heat dissipation base plate and LED packaging structure |
| CN102832331A (en) * | 2012-08-24 | 2012-12-19 | 江阴长电先进封装有限公司 | Wafer level LED packaging structure |
| CN103022307A (en) * | 2012-12-27 | 2013-04-03 | 江阴长电先进封装有限公司 | Wafer-level LED packaging method |
-
2013
- 2013-05-24 CN CN201310197548.5A patent/CN103280508B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6531328B1 (en) * | 2001-10-11 | 2003-03-11 | Solidlite Corporation | Packaging of light-emitting diode |
| WO2007049938A1 (en) * | 2005-10-28 | 2007-05-03 | Amosense Co., Ltd. | Electronic parts packages and method for forming a cavity thereof |
| CN101807657A (en) * | 2009-02-18 | 2010-08-18 | Lg伊诺特有限公司 | Light emitting device package and lighting system including the same |
| CN102403413A (en) * | 2010-09-19 | 2012-04-04 | 常州普美电子科技有限公司 | LED (Light-Emitting Diode) heat dissipation base plate, LED packaging structure, and manufacturing method of LED heat dissipation base plate and LED packaging structure |
| CN102832331A (en) * | 2012-08-24 | 2012-12-19 | 江阴长电先进封装有限公司 | Wafer level LED packaging structure |
| CN103022307A (en) * | 2012-12-27 | 2013-04-03 | 江阴长电先进封装有限公司 | Wafer-level LED packaging method |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105720167A (en) * | 2014-08-08 | 2016-06-29 | 兆阳材料科技有限公司 | Packaging method of light emitting diode |
| CN110649142A (en) * | 2015-12-31 | 2020-01-03 | 晶元光电股份有限公司 | Light emitting device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103280508B (en) | 2015-12-23 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105990265B (en) | The package module and its manufacturing method of circuit for power conversion | |
| CN201804913U (en) | Wafer-level light emitting diode (LED) packaging structure | |
| CN102339913B (en) | High-voltage LED (Light Emitting Diode) device and manufacturing method thereof | |
| CN103022307B (en) | Wafer-level LED packaging method | |
| TWI528508B (en) | Method for manufacturing ceramic package structure of high power light emitting diode | |
| CN102185091B (en) | Light-emitting diode device and manufacturing method thereof | |
| CN201412704Y (en) | Light source of integrated LED chip | |
| CN102610735B (en) | Light-emitting device with thermoelectric separated structure and manufacturing method of light-emitting device | |
| US8143080B2 (en) | Method for manufacturing LED package and substrate thereof | |
| CN101614333A (en) | High-efficiency radiating LED illumination light source and manufacture method | |
| CN201904369U (en) | LED (light emitting diode) surface-mounting package structure based on silicon substrate | |
| US20120043576A1 (en) | Led package structure | |
| CN101532612A (en) | Method for manufacturing integrated LED chip light source | |
| CN102832331B (en) | Wafer level LED packaging structure | |
| CN102693972A (en) | Light emitting diode package and manufacture method of lead frame of the light emitting diode package | |
| CN1702880A (en) | Semiconductive light-emitting diode (LED) through-hole flip chips and manufacturing technique thereof | |
| CN103354266B (en) | The encapsulating structure of a kind of slim wafer level LED and method for packing thereof | |
| CN103618041A (en) | ESD (electronic static discharge) protected LED (light-emitting diode) packaging structure as well as packaging method thereof | |
| US8716734B2 (en) | Light emitting diode package having a portion of reflection cup material covering electrode layer on side surfaces of substrate | |
| CN104037305A (en) | Packaging method and packaging structure of wafer-level LED with low heat resistance | |
| CN202871856U (en) | Wafer-level LED chip packaging structure | |
| CN103280508B (en) | A kind of wafer scale LED encapsulation method | |
| CN203071136U (en) | Wafer level LED packaging structure | |
| CN102136539A (en) | Wafer-level light emitting diode encapsulation structure and manufacturing method thereof | |
| CN103822143A (en) | LED (light emitting diode) street lamp light source module with silicon substrates |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |