CN103281472A - Detection device for faxing ANSam signal and detection method thereof - Google Patents

Abstract

The invention discloses a detection device for faxing an ANSam signal and a detection method thereof. The device comprises an SNR (Signal-Noise-Ratio) enhancing filter, a 2100Hz detector, a phase overturning detector, an amplitude modulation coefficient detector and a judging device, wherein the output end of the SNR enhancing filter is connected with the 2100Hz detector, the phase overturning detector and the amplitude modulation coefficient detector respectively; and the output ends of the 2100Hz detector, the phase overturning detector and the amplitude modulation coefficient detector are connected with the judging device respectively. The 2100Hz detector is used for partitioning a period (80 points) into four parts instead of directly calculating 2100Hz frequency spectrums, and is used for calculating 2100Hz frequency spectrums indirectly according to the spectrum relation between adjacent frames, so that the calculated amount is greatly reduced. Due to the adoption of the device and the method, the complexity of a system can be lowered, the influence of frequency deviation is eliminated, and the presence of overturning and amplitude modulation signals on the phase of an input signal still can be detected accurately under low SNR.

Description

A kind of checkout gear and detection method thereof of the ANSam signal of faxing

Technical field

The present invention relates to a kind of signal processing technology, particularly a kind of checkout gear and detection method thereof of the ANSam signal of faxing.

Background technology

In voice and low-rate data hybrid communication system, as media gateway, fax etc., data communication often uses the 2100Hz signal as the handshake between calling subscriber and the called subscriber, namely uses the 2100Hz signal of different modulating form to carry certain information and carries out protocol handshake [1].Adopt signal processing technology, the information that the 2100Hz signal is entrained is identified, can differentiate the user's communications state effectively, so that take different processing form, improve communication quality and efficient.

The portable information of 2100Hz signal has phase information and amplitude information, for phase information, continuous phase information is arranged, or per 450 millisecond period upset phase informations; For amplitude information, the amplitude information of constant amplitude is arranged, or use the amplitude information of 15Hz Sine Wave Amplitude Modulation.

The device that detects fax ANSam signal can detect the 2100Hz signal of the information of carrying, and carries out protocol handshake, namely detects whether to have the 2100Hz frequency component in the input signal, whether have phase overturn information and whether have the 15Hz Sine Wave Amplitude Modulation.

At present, use common time frequency analysis just can realize that amount of calculation is bigger to the detection of 2100Hz frequency.Detect for phase overturn, the method for employing has phase demodulating method, correlation method, phase-locked around-France.The phase demodulating method need produce local coherent carrier, and amount of calculation is bigger, the system complexity height; Correlation method can only be applicable to the frequency of accurate precognition, certain deviation occurs and the frequency of signal is normal in the reality, to this, it accurately detected phase whether upset is arranged; During the digital phase-locked loop detected phase, if no phase overturn, then output approaches input, if have phase overturn, output can depart from the input regular hour, the method is simpler, but its sideband noise can reduce the reliability of detection, if add band pass filter, in denoising, can reduce the sensitivity that detects the phase angle upset like this, reduce and detect performance.Amplitude modulation coefficient detects the normal amplitude that directly or indirectly detects the 15Hz amplitude-modulated signal, itself and fixed threshold are compared, obtain court verdict, but these methods are down-sampled to primary signal, cause the error of the amplitude-modulated signal average amplitude of surveying bigger, testing result is caused certain erroneous judgement.

Prior art related to the present invention is as follows:

Prior art scheme one:

T.Trump invented be used for network echo canceller forbid the audio signal detector, the patent No. is CN97193286.7.At first calculate first power estimated value from input signal, be about to input signal and send by two paths, calculate broadband power Ps and arrowband power P t respectively, then both are compared, if Pt Ps, then think to have the 2100Hz audio frequency.In addition, input signal is multiplied each other with sinusoidal wave sin (2 π 2100t) and cosine wave cos (2 π 2100t) respectively, it is divided into the component of in-phase component and 90 ° of phase shifts, then to its double sampling, the sampled value summation in succession realizes low-pass filtering.If reversing appears in phase place, the second dervative of its phase place comprises two adjacent pulses with opposite polarity, but does not comprise unknown constant; Otherwise the second dervative of phase place is near 0.Calculate second differnce and the result is transformed in (180 °, 180 °) interval, with its absolute value and threshold ratio, can judge whether phase place occurs reversing.

This scheme need be with signal respectively by broadband and narrowband systems when judging whether the 2100Hz audio frequency occurs, so amount of calculation is big.In addition, when phase overturn is judged, need to produce local coherent carrier, and will carry out double sampling, this has increased the computation complexity of system.Also have, this scheme can't detect whether there is 15Hz amplitude modulation.

Prior art scheme two:

" the tone signal phase overturn of band amplitude-frequency feedback detects " paper that Tian Yu etc. deliver considers that signal amplitude has than great dynamic range, has adopted adaptive threshold to adjudicate.This scheme comprises three parts: mixing, parameter Estimation, adjudicate according to estimating.Mixing is to be the frequency that input signal produces with this locality respectively that sine and the cosine signal of 2100Hz multiplies each other, and obtains the low frequency signal of two-way quadrature again after the filtering.Parameter Estimation is to utilize digital phase-locked loop that the two-way orthogonal signalling are handled, and obtains corresponding frequency departure and amplitude information.Judgement is frequency departure and the amplitude information that utilizes estimation to obtain, and input signal is compensated, and makes decision threshold carry out the self adaptation adjustment according to input.

The mixing of this scheme need produce local coherent carrier; Secondly, parameter Estimation needs digital phase-locked loop, and its sideband noise can reduce the reliability of detection, if add band pass filter, can reduce the sensitivity that detects the phase angle upset like this in denoising, reduces and detects performance.Also have, this invention can't detect whether there is 15Hz amplitude modulation.

Prior art scheme three:

R.L.Goodson etc. invented a kind of for detection of with the device of distinguishing the ANSam signal.This device at first passes through band pass filter with input signal, and adopt bearing calibration and the signal behind the bandpass filtering is carried out low-pass filtering again, dynamically arrange the pulse distortion threshold value of input signal, this threshold value is represented the excursion of low frequency amplitude-modulated signal average amplitude.By average amplitude and the threshold value of comparator input signal, be ANS signal or ANSam signal thereby detect input signal.

This device only can detect whether comprise the low frequency amplitude-modulated signal in the input signal, can't detect it and whether comprise the 2100Hz signal and whether have phase overturn.

Prior art scheme four:

Thanh Lam etc. invent a kind of device for detection of the ANSam signal.This installs at first demodulation input signal, with low pass signal filtering after the demodulation, obtains DC component wherein then; Then, deduct the range value of DC component with the range value of input signal, obtain detected value, i.e. the range value of 15Hz amplitude-modulated signal; At last, detected value and pre-set threshold are compared, if detected value, judges that input signal is the ANSam signal greater than threshold value; Otherwise, judge that input signal is the ANS signal.

This device judges that by comparing detected value and threshold value input signal is ANSam signal or ANS signal, whether does not comprise the 2100Hz signal and detect it, can't judge also whether it exists phase overturn.

Document related to the present invention is as follows:

[1]ITU-T Recommendation V.8,Procedures for Starting Sessions of Data Transmission over the Public Switched Telephone Network.2000.

What [2] T.Trump. was used for network echo canceller forbids the audio signal detector: China, CN1214818A.1999.

[3] Tian Yu, Li Shiju, gold are eastwards. and the tone signal phase overturn of band amplitude-frequency feedback detects. voice technology, 2004.

[4] R.L.Goodson, M.C.Rushing, G.D.Hunt.Apparatus and Method for Detecting and Discriminating Various Signal Types in the Presence of Impulse Distortions: the U.S., US5809085.1998.

[5] T.Lam, T.Lis, R.Haltmaier.Apparatus and Method for Detecting Amplitude Modulated Answer Back Toned Signals: the U.S., US5787116.1998.

[6]V.Bhatia,A.De,A.Gupta.A Robust Phase-reversed Tone Detection using Bispectrum and DFT-based Algorithms.20026th International Conference on Signal Processing Proceedings,2002.

Below be that the main title that the present invention relates to is explained:

The 2100Hz signal of ANSam:15Hz sinusoidal signal modulation, its phase place produces a phase overturn continuously or every 450 milliseconds.

ANS: single-tone 2100Hz signal, its phase place produces a phase overturn continuously or every 450 milliseconds.

DBm0: the absolute reference power of relative zero reference point.

Summary of the invention

For solving the problems referred to above that prior art exists, the present invention will design a kind of checkout gear and detection method thereof that can realize the fax ANSam signal of following purpose:

In voice and low-rate data hybrid communication system, for the digital signal that receives, can detect it simply and whether comprise the 2100Hz signal; If contain the 2100Hz signal, can judge exactly whether it exists phase overturn, not influenced by frequency shift (FS), still can detect when low signal-to-noise ratio; Simultaneously can correctly detect it and whether be modulated by the 15Hz sine amplitude, namely judge it is ANS signal or ANSam signal.

To achieve these goals, technical scheme of the present invention is as follows:

A kind of checkout gear of the ANSam signal of faxing comprises that SNR strengthens filter, 2100Hz detector, phase overturn detector, amplitude modulation coefficient detector and decision device; Described SNR strengthens the input input digital signal x (n) to be detected of filter, and its output is connected with 2100Hz detector, phase overturn detector and the input of amplitude modulation coefficient detector respectively; The input of described decision device connects the output of 2100Hz detector, phase overturn detector and amplitude modulation coefficient detector respectively, the output output testing result of decision device;

It is a band pass filter that centre frequency is 2100Hz that described SNR strengthens filter, its effect is the signal to noise ratio that improves input signal, improve follow-up detection performance, the Reference Design index of described band pass filter is: passband frequency range: 2.05KHz～2.15KHz, stop-band frequency scope: 0～1.1KHz and 3.1～4KHz, stopband attenuation is greater than 60dB, the Reference Design result that described SNR strengthens filter is 10 rank Finite Impulse Response filters, and it is as shown in table 1 that SNR strengthens filter coefficient bpf2100 (0)～bpf2100 (9):

Table 1 SNR strengthens filter coefficient table

Described SNR strengthens filter and comprises nine unit delay devices, ten multipliers and nine adders, digital signal x to be detected (n) is input to first unit delay device and first multiplier respectively, the output signal of first unit delay device is input to second unit delay device and second multiplier respectively, the output signal of second unit delay device is input to the 3rd unit delay device and the 3rd multiplier respectively, the rest may be inferred, the output signal of the 8th unit delay device is input to the 9th unit delay device and the 9th multiplier respectively, and the output signal of the 9th unit delay device is input to the tenth multiplier at last; Simultaneously, the coefficient bpf2100 (0) that SNR strengthens filter is input to first multiplier, and bpf2100 (1) is input to second multiplier, and the rest may be inferred, and bpf2100 (9) is input to the tenth multiplier; The output signal of first multiplier is input to first adder, the output signal of second multiplier is input to first adder, the output signal of the 3rd multiplier is input to second adder, the output signal of the 4th multiplier is input to the 3rd adder, the rest may be inferred, and the output signal of the tenth multiplier is input to the 9th adder; The output signal of first adder is input to second adder; The output signal of second adder is input to the 3rd adder, and the rest may be inferred, and the output signal of the 8th adder is input to the 9th adder, and the output signal of the 9th adder is filtering u (n) as a result;

Described 2100Hz detector comprises present frame cosine component estimator, present frame sinusoidal component estimator, present frame energy estimator A, this cosine sinusoidal component estimator, there are decision device in this energy estimator and 2100Hz signal, described present frame cosine component estimator, the input of present frame sinusoidal component estimator and present frame energy estimator A inserts filtering u (n) as a result simultaneously, the input of described this cosine sinusoidal component estimator connects present frame cosine component estimator and present frame sinusoidal component estimator respectively, there is decision device in its output termination 2100Hz signal, the input termination present frame energy estimator A of described this energy estimator, there is decision device in its output termination 2100Hz signal, the 2100Hz signal exists decision device directly to export court verdict, is 1 or 0;

Described present frame cosine component estimator comprises 20 multipliers, nineteen adder, present frame filtering u (m*20) as a result are input to first multiplier, and u (m*20+1) is input to second multiplier, the rest may be inferred, and u (m*20+19) is input to the 20 multiplier; Simultaneously, cosine signal

Be input to first multiplier,

Be input to second multiplier, and the like,

Be input to the 20 multiplier; The output signal of first multiplier is input to first adder, the output signal of second multiplier is input to first adder, the output signal of the 3rd multiplier is input to second adder, the output signal of the 4th multiplier is input to the 3rd adder, the rest may be inferred, and the output signal of the 20 multiplier is input to the nineteen adder; The output signal of first adder is input to second adder; The output signal of second adder is input to the 3rd adder, and the rest may be inferred, and the output signal of the 18 adder is input to the nineteen adder, and the output signal of nineteen adder is present frame cosine component d21_c (m);

Described present frame sinusoidal component estimator comprises 20 multipliers, nineteen adder, present frame filtering u (m*20) as a result are input to first multiplier, and u (m*20+1) is input to second multiplier, the rest may be inferred, and u (m*20+19) is input to the 20 multiplier; Simultaneously, sinusoidal signal

Be input to first multiplier,

Be input to second multiplier, and the like,

Be input to the 20 multiplier; The output signal of first multiplier is input to first adder, the output signal of second multiplier is input to first adder, the output signal of the 3rd multiplier is input to second adder, the output signal of the 4th multiplier is input to the 3rd adder, the rest may be inferred, and the output signal of the 20 multiplier is input to the nineteen adder; The output signal of first adder is input to second adder; The output signal of second adder is input to the 3rd adder, and the rest may be inferred, and the output signal of the 18 adder is input to the nineteen adder, and the output signal of nineteen adder is present frame sinusoidal component d21_s (m);

Described present frame energy estimator A comprises 20 multipliers, nineteen adder, present frame filtering u (m*20) as a result are input to first multiplier, and u (m*20+1) is input to second multiplier, the rest may be inferred, and u (m*20+19) is input to the 20 multiplier; Two input end signals of each multiplier are identical; The output signal of first multiplier is input to first adder, the output signal of second multiplier is input to first adder, the output signal of the 3rd multiplier is input to second adder, the output signal of the 4th multiplier is input to the 3rd adder, the rest may be inferred, and the output signal of the 20 multiplier is input to the nineteen adder; The output signal of first adder is input to second adder; The output signal of second adder is input to the 3rd adder, and the rest may be inferred, and the output signal of the 18 adder is input to the nineteen adder, and the output signal of nineteen adder is the energy d21_e (m) of present frame;

Described this cosine sinusoidal component estimator (204) comprises 6 unit delay devices, 2 multipliers and 6 adders, by the left-right symmetric structural configuration, present frame cosine component d21_c (m) is input to left upper portion unit delay device and the left side first exclusive side adder respectively, and present frame sinusoidal component d21_s (m) is input to right upper portion unit delay device and the right side first exclusive side adder respectively; The output of left upper portion unit delay device is connected with the right side inboard adder of first row with left side central portion unit delay device respectively, the output of left side central portion unit delay device is connected with the left side inboard adder of first row with bottom, left side unit delay device respectively, and the output of bottom, left side unit delay device is connected with the right side first exclusive side adder; The output of the inboard adder of left side first row is connected with the left side multiplier, and the output of left side multiplier is connected with the left side second exclusive side adder; The input termination right upper portion unit delay device of the left side first exclusive side adder, its output termination left side second exclusive side adder; The left side second exclusive side adder is output as the cosine component re (m) of this detection; The output of right upper portion unit delay device is connected with the left side first exclusive side adder with right side central unit delay device respectively, the output of right side central unit delay device is connected with the right side inboard adder of first row with lower right side unit delay device respectively, and the output of lower right side unit delay device is connected with the left side inboard adder of first row; The output of the inboard adder of right side first row is connected with the right side multiplier, and the output of right side multiplier is connected with the right side second exclusive side adder; The output termination right side second exclusive side adder of the right side first exclusive side adder; The right side second exclusive side adder is output as the sinusoidal component im (m) of this detection;

Described this energy estimator comprises 3 unit delay devices and 3 adders, the energy d21_e (m) of present frame is input to first unit delay device and first adder respectively, the output of first unit delay device is connected with first adder with second unit delay device respectively, the output of second unit delay device is connected with second adder with the 3rd unit delay device respectively, the output of the 3rd unit delay device is connected with the 3rd adder, the output of first adder is connected to second adder, the output of second adder is connected to the 3rd adder, and the 3rd adder is output as the energy ener (m) of this detection;

Described 2100Hz signal exist decision device comprise multiplier A, multiplier B, multiplier C, adder, comparator A, comparator B and and gate, two inputs of multiplier A all meet the cosine component re (m) of this detection, two inputs of the B of multiplier all meet the sinusoidal component im (m) of this detection, and the energy ener (m) of this detection meets multiplier C and comparator B respectively; The input of described adder meets multiplier A and multiplier B respectively, the output termination comparator A of adder; Another input termination multiplier C of described comparator A, output termination and the gate of comparator A, another input termination comparator B of described and gate is output as with gate and judges whether the 2100Hz component exists the result;

Described phase overturn detector comprises Hilbert transformer, present frame phase angle sinusoidal component estimator, present frame phase angle cosine component estimator, present frame energy estimator B and phase overturn decision device, and filtering u (n) as a result is linked into Hilbert transformer, present frame phase angle sinusoidal component estimator, present frame phase angle cosine component estimator, present frame energy estimator B respectively; Described Hilbert transformer, output connects present frame phase angle sinusoidal component estimator, the input of described phase overturn decision device connects present frame phase angle sinusoidal component estimator, present frame phase angle cosine component estimator and present frame energy estimator B respectively, and the phase overturn decision device is output as phase detection result;

Described Hilbert transformer comprises 18 unit delay devices, ten multipliers and nine adders, filtering signal u (n) is input to first unit delay device and first multiplier respectively, the output signal of first unit delay device is input to second unit delay device, second unit delay device output signal is input to the 3rd unit delay device and second multiplier respectively, the output signal of the 3rd unit delay device is input to the 4th unit delay device, the 4th unit delay device output signal is input to the 5th unit delay device and the 3rd multiplier respectively, the rest may be inferred, the output signal of the 17 unit delay device is input to the 18 unit delay device, and the output signal of the 18 unit delay device is input to the tenth multiplier at last; Simultaneously, the coefficient h of Hilbert transformer (0) is input to first multiplier, and h (2) is input to second multiplier, and h (4) is input to the 3rd multiplier, and the rest may be inferred, and h (18) is input to the tenth multiplier; The output signal of first multiplier is input to first adder, the output signal of second multiplier is input to first adder, the output signal of the 3rd multiplier is input to second adder, the output signal of the 4th multiplier is input to the 3rd adder, the rest may be inferred, and the output signal of the tenth multiplier is input to the 9th adder; The output signal of first adder is input to second adder; The output signal of second adder is input to the 3rd adder, and the rest may be inferred, and the output signal of the 8th adder is input to the 9th adder, the output signal of the 9th adder be after 90 ° of filtering signal u (n) phase shifts orthogonal signalling u ' (n);

Described present frame phase angle sinusoidal component estimator is divided into two parts, first comprises that M gets 240 among M(the present invention) individual unit delay device, present frame filtering u (m*20)～u (m*20+19) as a result is input to first unit delay device, the output signal of first unit delay device is input to second unit delay device, the output signal of second unit delay device is input to the 3rd unit delay device, the rest may be inferred, the output signal of M-1 unit delay device is input to M unit delay device, and M unit delay device is output as inhibit signal u (m*20-M)～u (m*20+19-M) of present frame filtering result; Second portion comprises M/20 unit delay device, 21 multipliers and 21 adders, the input of first multiplier connect respectively after 90 ° of the present frame filtering phase shifts as a result orthogonal signalling u ' (m*20) and present frame filtering result's inhibit signal u (m*20-M), the input of second multiplier connect respectively after 90 ° of the present frame filtering phase shifts as a result orthogonal signalling u ' (m*20+1) and present frame filtering result's inhibit signal u (m*20+1-M), the rest may be inferred, the input of the 20 multiplier connect respectively after 90 ° of the present frame filtering phase shifts as a result orthogonal signalling u ' (m*20+19) and present frame filtering result's inhibit signal u (m*20+19-M); The output signal of first multiplier is input to first adder, the output signal of second multiplier is input to first adder, the output signal of the 3rd multiplier is input to second adder, the output signal of the 4th multiplier is input to the 3rd adder, the rest may be inferred, and the output signal of the 20 multiplier is input to the nineteen adder; The output signal of first adder is input to second adder; The output signal of second adder is input to the 3rd adder, the rest may be inferred, the output signal of the 18 adder is input to the nineteen adder, and the output signal of nineteen adder is input to first unit delay device and the 20 adder respectively; The output signal of first unit delay device is input to second unit delay device, the output signal of second unit delay device is input to the 3rd unit delay device, the rest may be inferred, and the output signal of M/20-1 unit delay device is input to M/20 unit delay device; The output signal of M/20 unit delay device is input to the 21 multiplier, the output signal of the 21 multiplier is input to the 20 adder, the input signal of the 21 adder meets the output signal of the 20 adder and the sinusoidal sv (m-1) of m-1 frame signal phase angle respectively, and the 21 adder is output as the sinusoidal sv (m) of m frame signal phase angle;

Described present frame phase angle cosine component estimator comprises M/20 unit delay device, 21 multipliers and 21 adders, the input of first multiplier meets present frame filtering u (m*20) and its inhibit signal u (m*20-M) as a result respectively, the input of second multiplier meets present frame filtering u (m*20+1) and its inhibit signal u (m*20+1-M) as a result respectively, the rest may be inferred, and the input of the 20 multiplier meets present frame filtering u (m*20+19) and its inhibit signal u (m*20+19-M) as a result respectively; The output signal of first multiplier is input to first adder, the output signal of second multiplier is input to first adder, the output signal of the 3rd multiplier is input to second adder, the output signal of the 4th multiplier is input to the 3rd adder, the rest may be inferred, and the output signal of the 20 multiplier is input to the nineteen adder; The output signal of first adder is input to second adder; The output signal of second adder is input to the 3rd adder, the rest may be inferred, the output signal of the 18 adder is input to the nineteen adder, and the output signal of nineteen adder is input to first unit delay device and the 20 adder respectively; The output signal of first unit delay device is input to second unit delay device, the output signal of second unit delay device is input to the 3rd unit delay device, the rest may be inferred, and the output signal of M/20-1 unit delay device is input to M/20 unit delay device; The output signal of M/20 unit delay device is input to the 21 multiplier, the output signal of the 21 multiplier is input to the 20 adder, the output signal that the input signal of the 21 adder connects the 20 adder respectively and m-1 frame signal be cosine of an angle cv (m-1) mutually, and the 21 adder is output as m frame signal phase cosine of an angle cv (m);

Described present frame energy estimator B comprises 40 unit delay devices, 41 multipliers and three nineteen adders, present frame filtering result's inhibit signal u (m*20-M) is input to first unit delay device and second unit delay device respectively, present frame filtering result's inhibit signal u (m*20+1-M) is input to the 3rd unit delay device and the 4th unit delay device respectively, by that analogy, present frame filtering result's inhibit signal u (m*20+19-M) is input to the 3rd nineteen unit delay device and the 40 unit delay device respectively; The input of first multiplier connects the output of first unit delay device and second unit delay device respectively, the input of second multiplier connects the output of the 3rd unit delay device and the 4th unit delay device respectively, by that analogy, the input of the 20 multiplier connects the output of the 3rd nineteen unit delay device and the 40 unit delay device respectively; The input of the 21 multiplier all meets present frame filtering u (m*20) as a result, the input of the 22 multiplier all meets present frame filtering u (m*20+1) as a result, by that analogy, the input of the 40 multiplier all meets present frame filtering u (m*20+19) as a result; The output signal of first multiplier is input to first adder, the output signal of second multiplier is input to first adder, the output signal of the 3rd multiplier is input to second adder, the output signal of the 4th multiplier is input to the 3rd adder, the rest may be inferred, and the output signal of the 20 multiplier is input to the nineteen adder; The output signal of the 21 multiplier is input to the 20 adder, the output signal of the 22 multiplier is input to the 20 adder, the output signal of the 23 multiplier is input to the 21 adder, the output signal of the 24 multiplier is input to the 22 adder, the rest may be inferred, and the output signal of the 40 multiplier is input to the 38 adder; The output signal of nineteen adder is input to the 41 multiplier, the input of the 3rd nineteen adder connects the 41 multiplier and the 38 adder respectively, and the output signal of the 3rd nineteen adder is the energy difference ener2 (m) of m frame signal and its corresponding inhibit signal;

Described phase overturn decision device comprises (M/20-1) individual unit delay device, four multipliers, an adder and two comparators, the input signal of first multiplier all meets m frame signal phase cosine of an angle cv (m), the input signal of second multiplier all meets m frame signal phase cosine of an angle sv (m), the input signal of the 3rd multiplier all meets the energy difference ener2 (m) of m frame signal and its corresponding inhibit signal, and the output signal of the 3rd multiplier is input to the 4th multiplier; The input signal of first adder connects the output signal of first multiplier and the output signal of second multiplier respectively; The input signal of first comparator connects the output signal of first adder and the output signal of the 4th multiplier respectively; The output signal of first comparator is input to first unit delay device and second comparator respectively; The output signal of first unit delay device is input to second unit delay device, the output signal of second unit delay device is input to the 3rd unit delay device, by that analogy, the output signal of (M/20-2) individual unit delay device is input to (M/20-1) individual unit delay device, the output signal of (M/20-1) individual unit delay device is input to second comparator, and second comparator is output as the phase overturn court verdict;

Described amplitude modulation coefficient detector comprises the down-sampled device of present frame and amplitude modulation coefficient decision device, filtering signal u (n) is input to the down-sampled device of present frame, the output of the down-sampled device of present frame is connected with the amplitude modulation coefficient decision device, and the amplitude modulation coefficient decision device is output as the judgement amplitude-modulated signal and whether has the result;

The down-sampled device of described present frame comprises three unit delay devices and 22 adders, present frame filtering is amplitude as a result | u (m*20) | be input to first adder, present frame filtering is amplitude as a result | u (m*20+1) | be input to first adder, present frame filtering is amplitude as a result | u (m*20+2) | be input to second adder, present frame filtering is amplitude as a result | u (m*20+3) | be input to the 3rd adder, by that analogy, present frame filtering is amplitude as a result | u (m*20+19) | and be input to the nineteen adder, the output signal of nineteen adder is input to first unit delay device and the 20 adder respectively; The output signal of first unit delay device is input to second unit delay device and the 20 adder respectively, the output signal of second unit delay device is input to the 3rd unit delay device and the 21 adder, and the output signal of the 3rd unit delay device is input to the 22 adder; The output signal of the 20 adder is input to the 21 adder, the output signal of the 21 adder is input to the 22 adder, and the 22 adder is output as minimum value min, maximum max and the amplitude modulation coefficient am in the each point amplitude of down-sampled back;

Described amplitude modulation coefficient decision device comprises 3 comparators and 2 and gate; The input signal of first comparator meets minimum value min and the threshold value THRES4 in the each point amplitude of down-sampled back respectively, the input signal of second comparator meets amplitude modulation coefficient am and threshold value THRES5 respectively, and the input signal of the 3rd comparator meets amplitude modulation coefficient am and threshold value THRES6 respectively; First is connected first comparator and second comparator respectively with the input of gate, its output connects second and gate, the output of the 3rd comparator connects second and gate, and second is output as the judgement amplitude-modulated signal with gate and whether has the result;

Described decision device comprises one and gate, a multiplier and an adder; Be respectively 2100Hz detector output result and phase overturn detector output result with the input signal of gate, be input to multiplier with the output signal of gate; The input signal of adder is respectively output signal and the amplitude modulation coefficient detector output result of multiplier, and adder is output as the court verdict to input signal x (n).

A kind of detection method of checkout gear of the ANSam signal of faxing may further comprise the steps:

A, input signal is carried out filtering

SNR strengthens filter the digital signal x to be detected (n) that imports is carried out filtering, and exports filtering u (n) as a result, namely

$u\left(n\right)=\underset{k=0}{\overset{9}{\mathrm{\Σ}}}\mathrm{bpf}2100\left(k\right)\·x(n-k)---\left(1\right)$

Wherein, x (n-k) is n-k input signal constantly, and u (n) is n filtering result constantly, and bpf2100 (k) is k filter coefficient;

B, the filtering result is adjudicated

Whether B1, detection filter result comprise the 2100Hz signal

Whether the 2100Hz detector contains the 2100Hz component for detection of digital signal x to be detected (n), the input signal of 2100Hz detector is the filtering u (n) as a result that SNR strengthens filter, the output of 2100Hz detector is to detect the result whether 2100Hz exists, if the result is 0, there is not the 2100Hz signal in expression; If the result is 1, then there is the 2100Hz signal in expression;

The per 2.5 milliseconds of detections of 2100Hz detector once, when the input signal sample frequency was 8KHz, equivalence was 20 sampled points, namely data frame length is 20; If present frame is the m frame, then the data of present frame are u (m*20)～u (m*20+19); The method of estimation of the cosine component d21_c (m) of present frame, sinusoidal component d21_s (m) and energy d21_e (m) is respectively:

$d21\_c\left(m\right)=\underset{n=0}{\overset{19}{\mathrm{\&Sigma;}}}u(m*20+n)\mathrm{<figure-callout\; id="2"\; label="cos"\; filenames="HDA00003254595000012.png,HDA00003254595000051.png"\; state="\{\{state\}\}">cos</figure-callout>}\frac{2\mathrm{\&pi;}\&CenterDot;2100n}{8000}---\left(2\right)$

$d21\_s\left(m\right)=-\underset{n=0}{\overset{19}{\mathrm{\&Sigma;}}}u(m*20+n)\mathrm{<figure-callout\; id="2"\; label="sin"\; filenames="HDA00003254595000012.png,HDA00003254595000051.png"\; state="\{\{state\}\}">sin</figure-callout>}\frac{2\mathrm{\&pi;}\&CenterDot;2100n}{8000}---\left(3\right)$

$d21\_e\left(m\right)=\underset{n=0}{\overset{19}{\mathrm{\&Sigma;}}}{u}^2(m*20+n)---\left(4\right)$

The method of estimation of the cosine component re (m) of this detection, sinusoidal component im (m) and energy ener (m) is respectively:

re(m)＝d21_c[m]+d21_s[m-1]-d21_c[m-2]-d21_s[m-3] (5)

im(m)＝d21_s[m]-d21_c[m-1]-d21_s[m-2]+d21_c[m-3] (6)

ener(m)＝d21_e[m]+d21_e[m-1]+d21_e[m-2]+d21_e[m-3] (7)

Judge that the method whether the 2100Hz signal exists is:

Work as re ²(m)+im ²(m)＞and THRES1ener (m), during and ener (m)＞THRES2, be judged to the 2100Hz signal and exist; Otherwise being judged to the 2100Hz signal does not exist; The THRES1 here, THRES2 are decision threshold, are THRES1=20 with reference to value, THRES2=5242880;

Whether B2, detection filter result phase overturn

The effect of phase overturn detector is to detect input signal whether phase overturn is arranged, and can estimate the phase overturn angle; The input signal of phase overturn detector is the output signal u (n) that SNR strengthens filter, and the output of phase overturn detector is the result whether phase place overturns, if the result is 0, expression does not have upset; If the result is 1, then expression has upset;

At first filtering u (n) phase shift is as a result obtained u ' (n) for 90 °.90 ° of phase shifts realize that by Hilbert transformer its coefficient h (0)～h (18) is as shown in table 2:

Table 2 Hilbert transformer coefficient table

Hilbert transform is:

$u^{\&prime;}\left(n\right)=\underset{k=0}{\overset{9}{\mathrm{\&Sigma;}}}h\left(2k\right)u(n-2k)---\left(8\right)$

Wherein, u ' is the output of 90 ° of n phase shifts constantly (n), and u (n-2k) is n-2k input constantly, and h (2k) is 2k Hilbert transformer coefficient;

The phase overturn detector module remains per 2.5 milliseconds of detections once, and data frame length is that the filtering result data of 20, the m frames is u (m*20)～u (m*20+19), after 90 ° of its phase shifts data be u ' (m*20)～u ' (m*20+19); For time delayed signal u (m*20-M)～u (m*20+19-M) of m frame filtering result, M is time of delay (M is constant, and the present invention gets M=240); With its respectively with 90 ° of m frame filtering result data u (m*20)～u (m*20+19), m frame filtering phase shift as a result after data u ' (m*20)～u ' (m*20+19) multiplies each other, product signal is carried out low-pass filtering respectively, and the method for estimation that obtains det_c (m), det_s (m) is:

$\det \_c\left(m\right)=\underset{n=0}{\overset{19}{\mathrm{\&Sigma;}}}u(m*20+n)\&CenterDot;u(m*20+n-M)---\left(9\right)$

$\det \_s\left(m\right)=\underset{n=0}{\overset{19}{\mathrm{\&Sigma;}}}{u}^{\&prime;}(m*20+n)\&CenterDot;u(m*20+n-M)---\left(10\right)$

M frame signal phase cosine of an angle cv, sinusoidal sv divide amount estimation method to be:

cv(m)＝cv(m-1)+det_c(m)-det_c(m-M/20) (11)

sv(m)＝sv(m-1)+det_s(m)-det_s(m-M/20) (12)

The m frame signal with the energy difference ener2 (m) of its corresponding inhibit signal is:

$\mathrm{ener}2\left(m\right)=\mathrm{ener}2(m-1)+\underset{n=0}{\overset{19}{\mathrm{\&Sigma;}}}{\left[u(m*20+n)\right]}^2-u{(m*20+n-M-1)}^2]---\left(13\right)$

Detection method is: as [cv ²(m)+sv ²(m)]＞THRES3[ener2 (m)] ²The time, with its phase angle of arctangent computation

Here THRES3 is decision threshold, and value of the present invention is THRES3=0.25;

If when the phase difference before and after the upset satisfies formula (15), judge that then phase place has upset, be output as 1 this moment; Otherwise the judgement phase place does not have upset, and be output as 0 this moment:

Whether B3, detection filter result be by amplitude modulation

The effect of amplitude modulation coefficient detector is whether to detect input signal by amplitude modulation; Whether in the setting threshold scope, whether differentiate input signal by amplitude modulation by the amplitude modulation coefficient that relatively calculates; The input signal of amplitude modulation detector is the output u (n) that SNR strengthens filter, and it is output as 1, and then there is amplitude-modulated signal in expression; Be output as 0, there is not amplitude-modulated signal in expression;

At first to input signal down-sampled 80 times, method is to m frame filtering result data u (m*20)～u (m*20+19), calculates its amplitude absolute value sum:

$\mathrm{sum}20\left(m\right)=\underset{n=0}{\overset{19}{\mathrm{\&Sigma;}}}\left|u(m*20+n)\right|---\left(16\right)$

Then, calculate the amplitude absolute value sum of continuous 4 frame data, the amplitude absolute value sum equivalence of described continuous 4 frame data is 80 sampled points, is down-sampled back each point amplitude:

sum80(m)＝sum20(m)+sum20(m-1)+sum20(m-2)+sum20(m-3) (17)

Use the comparison search method, find out maximum max and minimum value min in the each point amplitude;

max=maximum{sum80(m),sum80(m-1),…,sum80(m-26)} (18)

min=minimum{sum80(m),sum80(m-1),…,sum80(m-26)} (19)

Then amplitude modulation coefficient am is:

$\mathrm{am}=\frac{\max -\min }{\max +\min }---\left(20\right)$

Work as min〉THRES4, during and THRES5＜am＜THRES6, judge there is the 15Hz modulation that be output as 1 this moment; Otherwise, be output as 0; Wherein, THRES4, THRES5, THRES6 are decision threshold, are THRES4=20480 with reference to value, THRES5=0.08, THRES6=0.26;

C, judgement input signal x (n) are the ANSam signals, or the ANS signal

The output of calculating decision device result formula as a result is

result=(result1&result2)×2+result3 (21)

Wherein, “ ﹠amp; " represent logical AND operation; Result1, result2 and result3 are respectively the output result of 2100Hz detector, phase overturn detector and amplitude modulation coefficient detector; The output of decision device result as a result is 0 or 1, represents input signal x (n) neither the ANSam signal, neither the ANS signal; Output result as a result is 2, and representing x (n) is the ANS signal; Output result as a result is 3, and representing x (n) is the ANSam signal.

Compared with prior art, the present invention has following beneficial effect:

1,2100Hz detector of the present invention is not directly to calculate the 2100Hz frequency spectrum, but one-period (80 point) is divided into 4 parts, and according to the Spectrum Relationship of consecutive frame, indirect calculation 2100Hz frequency spectrum reduces amount of calculation significantly.

2, phase overturn detector of the present invention adopts feed-forward structure, the low pass filter that has homophase and quadrature phase passage, calculates phase angle, and difference and the preset threshold of phase angle before and after upset place compared, and has judged whether phase overturn.By code book is in reason, can obtain the signal of homophase and quadrature phase angle, do not need to produce local coherent carrier, therefore can reduce the complexity of system, be not subjected to the influence of frequency shift (FS) simultaneously, under low signal-to-noise ratio, still can detect accurately.

3, amplitude modulation coefficient detector of the present invention is at first down-sampled, indirect calculation amplitude modulation coefficient then, and the accuracy that can the raising system detects reduces error.

Description of drawings

20 in the total accompanying drawing of the present invention, wherein:

Fig. 1 is ANSam signal supervisory instrument block diagram.

Fig. 2 is that SNR strengthens the filter block diagram.

Fig. 3 is 2100Hz detector block diagram.

Fig. 4 is present frame cosine component estimator block diagram.

Fig. 5 is present frame sinusoidal component estimator block diagram.

Fig. 6 is present frame energy estimator A block diagram.

Fig. 7 is this cosine, sinusoidal component estimator block diagram.

Fig. 8 is this energy estimator block diagram.

Fig. 9 is that the 2100Hz signal exists the decision device block diagram.

Figure 10 is phase overturn detector block diagram.

Figure 11 is the Hilbert transformer block diagram.

Figure 12 is present frame phase angle sinusoidal component estimator block diagram.

Figure 13 is present frame phase angle cosine component estimator block diagram.

Figure 14 is present frame energy estimator B block diagram.

Figure 15 is phase overturn decision device device block diagram.

Figure 16 is amplitude modulation coefficient detector block diagram.

Figure 17 is the down-sampled device block diagram of present frame.

Figure 18 is amplitude modulation coefficient decision device block diagram.

Figure 19 is the decision device block diagram.

Figure 20 is the detection method block diagram of fax ANSam signal.

Among the figure: 10, SNR strengthens filter, 20, the 2100Hz detector, 30, the phase overturn detector, 40, the amplitude modulation coefficient detector, 50, decision device, 201, present frame cosine component estimator, 202, present frame sinusoidal component estimator, 203, present frame energy estimator, 204, this cosine sinusoidal component estimator, 205, this energy estimator, 206, there is decision device in the 2100Hz signal, 301, Hilbert transformer, 302, present frame phase angle sinusoidal component estimator, 303, present frame phase angle cosine component estimator, 304, present frame energy estimator, 305, the phase overturn decision device, 401, the down-sampled device of present frame, 402, the amplitude modulation coefficient decision device.

Embodiment

Below in conjunction with accompanying drawing the present invention is described further.Shown in Fig. 1-18, a kind of checkout gear of the ANSam signal of faxing comprises that SNR strengthens filter 10,2100Hz detector 20, phase overturn detector 30, amplitude modulation coefficient detector 40 and decision device 50; Described SNR strengthens the input input digital signal x (n) to be detected of filter 10, and its output is connected with 2100Hz detector 20, phase overturn detector 30 and the input of amplitude modulation coefficient detector 40 respectively; The input of described decision device 50 connects the output of 2100Hz detector 20, phase overturn detector 30 and amplitude modulation coefficient detector 40 respectively, the output output testing result of decision device 50;

It is the band pass filters that centre frequency is 2100Hz that described SNR strengthens filter 10, its effect is the signal to noise ratio that improves input signal, improve follow-up detection performance, the Reference Design index of described band pass filter is: passband frequency range: 2.05KHz～2.15KHz, stop-band frequency scope: 0～1.1KHz and 3.1～4KHz, stopband attenuation is greater than 60dB, the Reference Design result that described SNR strengthens filter 10 is 10 rank Finite Impulse Response filters, and SNR strengthens filter, and 10 coefficient bpf2100 (0)～bpf2100 (9) is as shown in table 1.

Described 2100Hz detector 20 comprises present frame cosine component estimator 201, present frame sinusoidal component estimator 202, present frame energy estimator A203, this cosine sinusoidal component estimator 204, there are decision device 206 in this energy estimator 205 and 2100Hz signal, described accent present frame cosine component estimator 201, the input of present frame sinusoidal component estimator 202 and present frame energy estimator A203 inserts filtering u (n) as a result simultaneously, the input of described this cosine sinusoidal component estimator 204 connects respectively transfers present frame cosine component estimator 201 and present frame sinusoidal component estimator 202, there is decision device 206 in its output termination 2100Hz signal, the input termination present frame energy estimator A203 of described this energy estimator 205, there is decision device 206 in its output termination 2100Hz signal, there is directly output court verdict of decision device 206 in the 2100Hz signal, is 1 or 0;

Described phase overturn detector 30 comprises Hilbert transformer 301, present frame phase angle sinusoidal component estimator 302, present frame phase angle cosine component estimator 303, present frame energy estimator B304 and phase overturn decision device 305, and filtering u (n) as a result is linked into Hilbert transformer 301, present frame phase angle sinusoidal component estimator 302, present frame phase angle cosine component estimator 303, present frame energy estimator B304 respectively; Described Hilbert transformer 301, output connects present frame phase angle sinusoidal component estimator 302, the input of described phase overturn decision device 305 connects present frame phase angle sinusoidal component estimator 302, present frame phase angle cosine component estimator 303 and present frame energy estimator B304 respectively, and phase overturn decision device 305 is output as phase detection result;

Described amplitude modulation coefficient detector 40 comprises the down-sampled device 401 of present frame and amplitude modulation coefficient decision device 402, filtering signal u (n) is input to the down-sampled device 401 of present frame, the output of the down-sampled device 401 of present frame is connected with amplitude modulation coefficient decision device 402, and amplitude modulation coefficient decision device 402 is output as the judgement amplitude-modulated signal and whether has the result;

Described decision device 50 comprises one and gate, a multiplier and an adder; Be respectively 2100Hz detector 20 output results and phase overturn detector 30 output results with the input signal of gate, be input to multiplier with the output signal of gate; The input signal of adder is respectively output signal and the amplitude modulation coefficient detector 40 output results of multiplier, and adder is output as the court verdict to input signal x (n).

Shown in Fig. 1-19, a kind of detection method of checkout gear of the ANSam signal of faxing may further comprise the steps:

A, input signal is carried out filtering

The digital signal x to be detected (n) that SNR strengthens 10 pairs of inputs of filter carries out filtering, and exports filtering u (n) as a result, namely

$u\left(n\right)=\underset{k=0}{\overset{9}{\mathrm{\&Sigma;}}}\mathrm{bpf}2100\left(k\right)\&CenterDot;x(n-k)---\left(1\right)$

Wherein, x (n-k) is n-k input signal constantly, and u (n) is n filtering result constantly, and bpf2100 (k) is k filter coefficient;

B, the filtering result is adjudicated

Whether B1, detection filter result comprise the 2100Hz signal

Whether B2, detection filter result phase overturn

Whether B3, detection filter result be by amplitude modulation

C, judgement input signal x (n) are the ANSam signals, or the ANS signal

The output of calculating decision device 50 result formula as a result is

result=(result1&result2)×2+result3 (21)

Wherein, “ ﹠amp; " represent logical AND operation; Result1, result2 and result3 are respectively the output result of 2100Hz detector 20, phase overturn detector 30 and amplitude modulation coefficient detector 40; The output of decision device 50 result as a result is 0 or 1, represents input signal x (n) neither the ANSam signal, neither the ANS signal; Output result as a result is 2, and representing x (n) is the ANS signal; Output result as a result is 3, and representing x (n) is the ANSam signal.

In order to verify validity of the present invention, some tests have been carried out.Under different signal to noise ratios (additive white Gaussian noise) situation, the frequency range of input measured signal is 2040Hz～2160Hz, and the phase overturn angular range is 140 °～220 °, and the amplitude modulation coefficient scope is 0.05～0.30.The scope of detection effective frequency of the present invention, phase overturn angle, amplitude modulation coefficient etc. is as shown in table 3.By test result as seen: under common signal to noise ratio condition, detection range is constant substantially; Under low signal-to-noise ratio (5dB) condition very, detecting performance has by a small margin and descends, but still can satisfy application request.The testing result explanation, the present invention has good detection performance and good operation robustness.

Table 3 detection performance of the present invention

Claims (2)

1. the checkout gear of ANSam signal of faxing is characterized in that: comprise that SNR strengthens filter (10), 2100Hz detector (20), phase overturn detector (30), amplitude modulation coefficient detector (40) and decision device (50); Described SNR strengthens the input input digital signal x (n) to be detected of filter (10), and its output is connected with 2100Hz detector (20), phase overturn detector (30) and the input of amplitude modulation coefficient detector (40) respectively; The input of described decision device (50) connects the output of 2100Hz detector (20), phase overturn detector (30) and amplitude modulation coefficient detector (40) respectively, the output output testing result of decision device (50);

It is a band pass filter that centre frequency is 2100Hz that described SNR strengthens filter (10), its effect is the signal to noise ratio that improves input signal, improve follow-up detection performance, the Reference Design index of described band pass filter is: passband frequency range: 2.05KHz～2.15KHz, stop-band frequency scope: 0～1.1KHz and 3.1～4KHz, stopband attenuation is greater than 60dB, the Reference Design result that described SNR strengthens filter (10) is 10 rank Finite Impulse Response filters, and it is as shown in table 1 that SNR strengthens filter (10) coefficient bpf2100 (0)～bpf2100 (9):

Table 1SNR strengthens filter coefficient table

Described SNR strengthens filter (10) and comprises nine unit delay devices, ten multipliers and nine adders, digital signal x to be detected (n) is input to first unit delay device and first multiplier respectively, the output signal of first unit delay device is input to second unit delay device and second multiplier respectively, the output signal of second unit delay device is input to the 3rd unit delay device and the 3rd multiplier respectively, the rest may be inferred, the output signal of the 8th unit delay device is input to the 9th unit delay device and the 9th multiplier respectively, and the output signal of the 9th unit delay device is input to the tenth multiplier at last; Simultaneously, the coefficient bpf2100 (0) that SNR strengthens filter (10) is input to first multiplier, and bpf2100 (1) is input to second multiplier, and the rest may be inferred, and bpf2100 (9) is input to the tenth multiplier; The output signal of first multiplier is input to first adder, the output signal of second multiplier is input to first adder, the output signal of the 3rd multiplier is input to second adder, the output signal of the 4th multiplier is input to the 3rd adder, the rest may be inferred, and the output signal of the tenth multiplier is input to the 9th adder; The output signal of first adder is input to second adder; The output signal of second adder is input to the 3rd adder, and the rest may be inferred, and the output signal of the 8th adder is input to the 9th adder, and the output signal of the 9th adder is filtering u (n) as a result;

Described 2100Hz detector (20) comprises present frame cosine component estimator (201), present frame sinusoidal component estimator (202), present frame energy estimator A(203), this cosine sinusoidal component estimator (204), there are decision device (206) in this energy estimator (205) and 2100Hz signal, described present frame cosine component estimator (201), present frame sinusoidal component estimator (202) and present frame energy estimator A(203) input insert filtering u (n) as a result simultaneously, the input of described this cosine sinusoidal component estimator (204) connects present frame cosine component estimator (201) and present frame sinusoidal component estimator (202) respectively, there is decision device (206) in its output termination 2100Hz signal, the input termination present frame energy estimator A(203 of described this energy estimator (205)), there is decision device (206) in its output termination 2100Hz signal, the 2100Hz signal exists decision device (206) directly to export court verdict, is 1 or 0;

Described present frame cosine component estimator (201) comprises 20 multipliers, nineteen adder, present frame filtering u (m*20) as a result are input to first multiplier, and u (m*20+1) is input to second multiplier, the rest may be inferred, and u (m*20+19) is input to the 20 multiplier; Simultaneously, cosine signal

Be input to first multiplier,

Be input to second multiplier, and the like,

Be input to the 20 multiplier; The output signal of first multiplier is input to first adder, the output signal of second multiplier is input to first adder, the output signal of the 3rd multiplier is input to second adder, the output signal of the 4th multiplier is input to the 3rd adder, the rest may be inferred, and the output signal of the 20 multiplier is input to the nineteen adder; The output signal of first adder is input to second adder; The output signal of second adder is input to the 3rd adder, and the rest may be inferred, and the output signal of the 18 adder is input to the nineteen adder, and the output signal of nineteen adder is present frame cosine component d21_c (m);

Described present frame sinusoidal component estimator (202) comprises 20 multipliers, nineteen adder, present frame filtering u (m*20) as a result are input to first multiplier, and u (m*20+1) is input to second multiplier, the rest may be inferred, and u (m*20+19) is input to the 20 multiplier; Simultaneously, sinusoidal signal

Be input to first multiplier,

Be input to second multiplier, and the like, Be input to the 20 multiplier; The output signal of first multiplier is input to first adder, the output signal of second multiplier is input to first adder, the output signal of the 3rd multiplier is input to second adder, the output signal of the 4th multiplier is input to the 3rd adder, the rest may be inferred, and the output signal of the 20 multiplier is input to the nineteen adder; The output signal of first adder is input to second adder; The output signal of second adder is input to the 3rd adder, and the rest may be inferred, and the output signal of the 18 adder is input to the nineteen adder, and the output signal of nineteen adder is present frame sinusoidal component d21_s (m);

Described present frame energy estimator A(203) comprises 20 multipliers, nineteen adder, present frame filtering u (m*20) as a result are input to first multiplier, and u (m*20+1) is input to second multiplier, the rest may be inferred, and u (m*20+19) is input to the 20 multiplier; Two input end signals of each multiplier are identical; The output signal of first multiplier is input to first adder, the output signal of second multiplier is input to first adder, the output signal of the 3rd multiplier is input to second adder, the output signal of the 4th multiplier is input to the 3rd adder, the rest may be inferred, and the output signal of the 20 multiplier is input to the nineteen adder; The output signal of first adder is input to second adder; The output signal of second adder is input to the 3rd adder, and the rest may be inferred, and the output signal of the 18 adder is input to the nineteen adder, and the output signal of nineteen adder is the energy d21_e (m) of present frame;

Described this cosine sinusoidal component estimator (204) comprises 6 unit delay devices, 2 multipliers and 6 adders, by the left-right symmetric structural configuration, present frame cosine component d21_c (m) is input to left upper portion unit delay device and the left side first exclusive side adder respectively, and present frame sinusoidal component d21_s (m) is input to right upper portion unit delay device and the right side first exclusive side adder respectively; The output of left upper portion unit delay device is connected with the right side inboard adder of first row with left side central portion unit delay device respectively, the output of left side central portion unit delay device is connected with the left side inboard adder of first row with bottom, left side unit delay device respectively, and the output of bottom, left side unit delay device is connected with the right side first exclusive side adder; The output of the inboard adder of left side first row is connected with the left side multiplier, and the output of left side multiplier is connected with the left side second exclusive side adder; The input termination right upper portion unit delay device of the left side first exclusive side adder, its output termination left side second exclusive side adder; The left side second exclusive side adder is output as the cosine component re (m) of this detection; The output of right upper portion unit delay device is connected with the left side first exclusive side adder with right side central unit delay device respectively, the output of right side central unit delay device is connected with the right side inboard adder of first row with lower right side unit delay device respectively, and the output of lower right side unit delay device is connected with the left side inboard adder of first row; The output of the inboard adder of right side first row is connected with the right side multiplier, and the output of right side multiplier is connected with the right side second exclusive side adder; The output termination right side second exclusive side adder of the right side first exclusive side adder; The right side second exclusive side adder is output as the sinusoidal component im (m) of this detection;

Described this energy estimator (205) comprises 3 unit delay devices and 3 adders, the energy d21_e (m) of present frame is input to first unit delay device and first adder respectively, the output of first unit delay device is connected with first adder with second unit delay device respectively, the output of second unit delay device is connected with second adder with the 3rd unit delay device respectively, the output of the 3rd unit delay device is connected with the 3rd adder, the output of first adder is connected to second adder, the output of second adder is connected to the 3rd adder, and the 3rd adder is output as the energy ener (m) of this detection;

Described 2100Hz signal exist decision device (206) comprise multiplier A, multiplier B, multiplier C, adder, comparator A, comparator B and and gate, two inputs of multiplier A all meet the cosine component re (m) of this detection, two inputs of the B of multiplier all meet the sinusoidal component im (m) of this detection, and the energy ener (m) of this detection meets multiplier C and comparator B respectively; The input of described adder meets multiplier A and multiplier B respectively, the output termination comparator A of adder; Another input termination multiplier C of described comparator A, output termination and the gate of comparator A, another input termination comparator B of described and gate is output as with gate and judges whether the 2100Hz component exists the result;

Described phase overturn detector (30) comprises Hilbert transformer (301), present frame phase angle sinusoidal component estimator (302), present frame phase angle cosine component estimator (303), present frame energy estimator B(304) and phase overturn decision device (305), filtering u (n) as a result is linked into Hilbert transformer (301), present frame phase angle sinusoidal component estimator (302), present frame phase angle cosine component estimator (303), present frame energy estimator B(304 respectively); Described Hilbert transformer (301), output connects present frame phase angle sinusoidal component estimator (302), the input of described phase overturn decision device (305) connects present frame phase angle sinusoidal component estimator (302), present frame phase angle cosine component estimator (303) and present frame energy estimator B(304 respectively), phase overturn decision device (305) is output as phase detection result;

Described Hilbert transformer (301) comprises 18 unit delay devices, ten multipliers and nine adders, filtering signal u (n) is input to first unit delay device and first multiplier respectively, the output signal of first unit delay device is input to second unit delay device, second unit delay device output signal is input to the 3rd unit delay device and second multiplier respectively, the output signal of the 3rd unit delay device is input to the 4th unit delay device, the 4th unit delay device output signal is input to the 5th unit delay device and the 3rd multiplier respectively, the rest may be inferred, the output signal of the 17 unit delay device is input to the 18 unit delay device, and the output signal of the 18 unit delay device is input to the tenth multiplier at last; Simultaneously, the coefficient h (0) of Hilbert transformer (301) is input to first multiplier, and h (2) is input to second multiplier, and h (4) is input to the 3rd multiplier, and the rest may be inferred, and h (18) is input to the tenth multiplier; The output signal of first multiplier is input to first adder, the output signal of second multiplier is input to first adder, the output signal of the 3rd multiplier is input to second adder, the output signal of the 4th multiplier is input to the 3rd adder, the rest may be inferred, and the output signal of the tenth multiplier is input to the 9th adder; The output signal of first adder is input to second adder; The output signal of second adder is input to the 3rd adder, and the rest may be inferred, and the output signal of the 8th adder is input to the 9th adder, the output signal of the 9th adder be after 90 ° of filtering signal u (n) phase shifts orthogonal signalling u ' (n);

Described present frame phase angle sinusoidal component estimator (302) is divided into two parts, first comprises that M gets 240 among M(the present invention) individual unit delay device, present frame filtering u (m*20)～u (m*20+19) as a result is input to first unit delay device, the output signal of first unit delay device is input to second unit delay device, the output signal of second unit delay device is input to the 3rd unit delay device, the rest may be inferred, the output signal of M-1 unit delay device is input to M unit delay device, and M unit delay device is output as inhibit signal u (m*20-M)～u (m*20+19-M) of present frame filtering result; Second portion comprises M/20 unit delay device, 21 multipliers and 21 adders, the input of first multiplier connect respectively after 90 ° of the present frame filtering phase shifts as a result orthogonal signalling u ' (m*20) and present frame filtering result's inhibit signal u (m*20-M), the input of second multiplier connect respectively after 90 ° of the present frame filtering phase shifts as a result orthogonal signalling u ' (m*20+1) and present frame filtering result's inhibit signal u (m*20+1-M), the rest may be inferred, the input of the 20 multiplier connect respectively after 90 ° of the present frame filtering phase shifts as a result orthogonal signalling u ' (m*20+19) and present frame filtering result's inhibit signal u (m*20+19-M); The output signal of first multiplier is input to first adder, the output signal of second multiplier is input to first adder, the output signal of the 3rd multiplier is input to second adder, the output signal of the 4th multiplier is input to the 3rd adder, the rest may be inferred, and the output signal of the 20 multiplier is input to the nineteen adder; The output signal of first adder is input to second adder; The output signal of second adder is input to the 3rd adder, the rest may be inferred, the output signal of the 18 adder is input to the nineteen adder, and the output signal of nineteen adder is input to first unit delay device and the 20 adder respectively; The output signal of first unit delay device is input to second unit delay device, the output signal of second unit delay device is input to the 3rd unit delay device, the rest may be inferred, and the output signal of M/20-1 unit delay device is input to M/20 unit delay device; The output signal of M/20 unit delay device is input to the 21 multiplier, the output signal of the 21 multiplier is input to the 20 adder, the input signal of the 21 adder meets the output signal of the 20 adder and the sinusoidal sv (m-1) of m-1 frame signal phase angle respectively, and the 21 adder is output as the sinusoidal sv (m) of m frame signal phase angle;

Described present frame phase angle cosine component estimator (303) comprises M/20 unit delay device, 21 multipliers and 21 adders, the input of first multiplier meets present frame filtering u (m*20) and its inhibit signal u (m*20-M) as a result respectively, the input of second multiplier meets present frame filtering u (m*20+1) and its inhibit signal u (m*20+1-M) as a result respectively, the rest may be inferred, and the input of the 20 multiplier meets present frame filtering u (m*20+19) and its inhibit signal u (m*20+19-M) as a result respectively; The output signal of first multiplier is input to first adder, the output signal of second multiplier is input to first adder, the output signal of the 3rd multiplier is input to second adder, the output signal of the 4th multiplier is input to the 3rd adder, the rest may be inferred, and the output signal of the 20 multiplier is input to the nineteen adder; The output signal of first adder is input to second adder; The output signal of second adder is input to the 3rd adder, the rest may be inferred, the output signal of the 18 adder is input to the nineteen adder, and the output signal of nineteen adder is input to first unit delay device and the 20 adder respectively; The output signal of first unit delay device is input to second unit delay device, the output signal of second unit delay device is input to the 3rd unit delay device, the rest may be inferred, and the output signal of M/20-1 unit delay device is input to M/20 unit delay device; The output signal of M/20 unit delay device is input to the 21 multiplier, the output signal of the 21 multiplier is input to the 20 adder, the output signal that the input signal of the 21 adder connects the 20 adder respectively and m-1 frame signal be cosine of an angle cv (m-1) mutually, and the 21 adder is output as m frame signal phase cosine of an angle cv (m);

Described present frame energy estimator B(304) comprises 40 unit delay devices, 41 multipliers and three nineteen adders, present frame filtering result's inhibit signal u (m*20-M) is input to first unit delay device and second unit delay device respectively, present frame filtering result's inhibit signal u (m*20+1-M) is input to the 3rd unit delay device and the 4th unit delay device respectively, by that analogy, present frame filtering result's inhibit signal u (m*20+19-M) is input to the 3rd nineteen unit delay device and the 40 unit delay device respectively; The input of first multiplier connects the output of first unit delay device and second unit delay device respectively, the input of second multiplier connects the output of the 3rd unit delay device and the 4th unit delay device respectively, by that analogy, the input of the 20 multiplier connects the output of the 3rd nineteen unit delay device and the 40 unit delay device respectively; The input of the 21 multiplier all meets present frame filtering u (m*20) as a result, the input of the 22 multiplier all meets present frame filtering u (m*20+1) as a result, by that analogy, the input of the 40 multiplier all meets present frame filtering u (m*20+19) as a result; The output signal of first multiplier is input to first adder, the output signal of second multiplier is input to first adder, the output signal of the 3rd multiplier is input to second adder, the output signal of the 4th multiplier is input to the 3rd adder, the rest may be inferred, and the output signal of the 20 multiplier is input to the nineteen adder; The output signal of the 21 multiplier is input to the 20 adder, the output signal of the 22 multiplier is input to the 20 adder, the output signal of the 23 multiplier is input to the 21 adder, the output signal of the 24 multiplier is input to the 22 adder, the rest may be inferred, and the output signal of the 40 multiplier is input to the 38 adder; The output signal of nineteen adder is input to the 41 multiplier, the input of the 3rd nineteen adder connects the 41 multiplier and the 38 adder respectively, and the output signal of the 3rd nineteen adder is the energy difference ener2 (m) of m frame signal and its corresponding inhibit signal;

Described phase overturn decision device (305) comprises (M/20-1) individual unit delay device, four multipliers, an adder and two comparators, the input signal of first multiplier all meets m frame signal phase cosine of an angle cv (m), the input signal of second multiplier all meets m frame signal phase cosine of an angle sv (m), the input signal of the 3rd multiplier all meets the energy difference ener2 (m) of m frame signal and its corresponding inhibit signal, and the output signal of the 3rd multiplier is input to the 4th multiplier; The input signal of first adder connects the output signal of first multiplier and the output signal of second multiplier respectively; The input signal of first comparator connects the output signal of first adder and the output signal of the 4th multiplier respectively; The output signal of first comparator is input to first unit delay device and second comparator respectively; The output signal of first unit delay device is input to second unit delay device, the output signal of second unit delay device is input to the 3rd unit delay device, by that analogy, the output signal of (M/20-2) individual unit delay device is input to (M/20-1) individual unit delay device, the output signal of (M/20-1) individual unit delay device is input to second comparator, and second comparator is output as the phase overturn court verdict;

Described amplitude modulation coefficient detector (40) comprises the down-sampled device of present frame (401) and amplitude modulation coefficient decision device (402), filtering signal u (n) is input to the down-sampled device of present frame (401), the output of the down-sampled device of present frame (401) is connected with amplitude modulation coefficient decision device (402), and amplitude modulation coefficient decision device (402) is output as the judgement amplitude-modulated signal and whether has the result;

The down-sampled device of described present frame (401) comprises three unit delay devices and 22 adders, present frame filtering is amplitude as a result | u (m*20) | be input to first adder, present frame filtering is amplitude as a result | u (m*20+1) | be input to first adder, present frame filtering is amplitude as a result | u (m*20+2) | be input to second adder, present frame filtering is amplitude as a result | u (m*20+3) | be input to the 3rd adder, by that analogy, present frame filtering is amplitude as a result | u (m*20+19) | and be input to the nineteen adder, the output signal of nineteen adder is input to first unit delay device and the 20 adder respectively; The output signal of first unit delay device is input to second unit delay device and the 20 adder respectively, the output signal of second unit delay device is input to the 3rd unit delay device and the 21 adder, and the output signal of the 3rd unit delay device is input to the 22 adder; The output signal of the 20 adder is input to the 21 adder, the output signal of the 21 adder is input to the 22 adder, and the 22 adder is output as minimum value min, maximum max and the amplitude modulation coefficient am in the each point amplitude of down-sampled back;

Described amplitude modulation coefficient decision device (402) comprises 3 comparators and 2 and gate; The input signal of first comparator meets minimum value min and the threshold value THRES4 in the each point amplitude of down-sampled back respectively, the input signal of second comparator meets amplitude modulation coefficient am and threshold value THRES5 respectively, and the input signal of the 3rd comparator meets amplitude modulation coefficient am and threshold value THRES6 respectively; First is connected first comparator and second comparator respectively with the input of gate, its output connects second and gate, the output of the 3rd comparator connects second and gate, and second is output as the judgement amplitude-modulated signal with gate and whether has the result;

Described decision device (50) comprises one and gate, a multiplier and an adder; Be respectively 2100Hz detector (20) output result and phase overturn detector (30) output result with the input signal of gate, be input to multiplier with the output signal of gate; The input signal of adder is respectively output signal and amplitude modulation coefficient detector (40) the output result of multiplier, and adder is output as the court verdict to input signal x (n).

2. the detection method of the checkout gear of the ANSam signal of faxing is characterized in that: may further comprise the steps:

A, input signal is carried out filtering

SNR strengthens filter (10) the digital signal x to be detected (n) that imports is carried out filtering, and exports filtering u (n) as a result, namely

$u\left(n\right)=\underset{k=0}{\overset{9}{\mathrm{\&Sigma;}}}\mathrm{bpf}2100\left(k\right)\&CenterDot;x(n-k)---\left(1\right)$

Wherein, x (n-k) is n-k input signal constantly, and u (n) is n filtering result constantly, and bpf2100 (k) is k filter coefficient;

B, the filtering result is adjudicated

Whether B1, detection filter result comprise the 2100Hz signal

Whether 2100Hz detector (20) contains the 2100Hz component for detection of digital signal x to be detected (n), the input signal of 2100Hz detector (20) is the filtering u (n) as a result that SNR strengthens filter (10), the output of 2100Hz detector (20) is to detect the result whether 2100Hz exists, if the result is 0, there is not the 2100Hz signal in expression; If the result is 1, then there is the 2100Hz signal in expression;

The per 2.5 milliseconds of detections of 2100Hz detector (20) once, when the input signal sample frequency was 8KHz, equivalence was 20 sampled points, namely data frame length is 20; If present frame is the m frame, then the data of present frame are u (m*20)～u (m*20+19); The method of estimation of the cosine component d21_c (m) of present frame, sinusoidal component d21_s (m) and energy d21_e (m) is respectively:

$d21\_c\left(m\right)=\underset{n=0}{\overset{19}{\mathrm{\&Sigma;}}}u(m*20+n)\cos \frac{2\mathrm{\&pi;}\&CenterDot;2100n}{8000}---\left(2\right)$

$d21\_s\left(m\right)=-\underset{n=0}{\overset{19}{\mathrm{\&Sigma;}}}u(m*20+n)\sin \frac{2\mathrm{\&pi;}\&CenterDot;2100n}{8000}---\left(3\right)$

$d21\_e\left(m\right)=\underset{n=0}{\overset{19}{\mathrm{\&Sigma;}}}{u}^2(m*20+n)---\left(4\right)$

Wherein, n=0,1 ..., 19.

The method of estimation of the cosine component re (m) of this detection, sinusoidal component im (m) and energy ener (m) is respectively:

re(m)＝d21_c[m]+d21_s[m-1]-d21_c[m-2]-d21_s[m-3] (5)

im(m)＝d21_s[m]-d21_c[m-1]-d21_s[m-2]+d21_c[m-3] (6)

ener(m)＝d21_e[m]+d21_e[m-1]+d21_e[m-2]+d21_e[m-3] (7)

Judge that the method whether the 2100Hz signal exists is:

Work as re ²(m)+im ²(m)＞and THRES1ener (m), during and ener (m)＞THRES2, be judged to the 2100Hz signal and exist; Otherwise being judged to the 2100Hz signal does not exist; The THRES1 here, THRES2 are decision threshold, are THRES1=20 with reference to value, THRES2=5242880;

Whether B2, detection filter result phase overturn

The effect of phase overturn detector (30) is to detect input signal whether phase overturn is arranged, and can estimate the phase overturn angle; The input signal of phase overturn detector (30) is the output signal u (n) that SNR strengthens filter (10), and the output of phase overturn detector (30) is the result whether phase place overturns, if the result is 0, expression does not have upset; If the result is 1, then expression has upset;

At first filtering u (n) phase shift is as a result obtained u ' (n) for 90 °.90 ° of phase shifts realize that by Hilbert transformer (301) its coefficient h (0)～h (18) is as shown in table 2:

Table 2 Hilbert transformer coefficient table

Hilbert transform is:

$u\&prime;\left(n\right)\underset{k=0}{\overset{9}{\mathrm{\&Sigma;}}}h\left(2k\right)u(n-2k)---\left(8\right)$

Wherein, u ' is the output of 90 ° of n phase shifts constantly (n), and u (n-2k) is n-2k input constantly, and h (2k) is 2k Hilbert transformer coefficient;

Phase overturn detector (30) module remains per 2.5 milliseconds of detections once, and data frame length is that the filtering result data of 20, the m frames is u (m*20)～u (m*20+19), after 90 ° of its phase shifts data be u ' (m*20)～u ' (m*20+19); For time delayed signal u (m*20-M)～u (m*20+19-M) of m frame filtering result, M is time of delay (M is constant, and the present invention gets M=240); With its respectively with 90 ° of m frame filtering result data u (m*20)～u (m*20+19), m frame filtering phase shift as a result after data u ' (m*20)～u ' (m*20+19) multiplies each other, product signal is carried out low-pass filtering respectively, and the method for estimation that obtains det_c (m), det_s (m) is:

$\det \_c\left(m\right)=\underset{n=0}{\overset{9}{\mathrm{\&Sigma;}}}u(m*20+n)\&CenterDot;u(m*20+n-M)---\left(9\right)$

$\det \_s\left(m\right)=\underset{n=0}{\overset{19}{\mathrm{\&Sigma;}}}u\&prime;(m*20+n)\&CenterDot;u(m*20+n-M)---\left(10\right)$

M frame signal phase cosine of an angle cv, sinusoidal sv divide amount estimation method to be:

cv(m)＝cv(m-1)+det_c(m)-det_c(m-M/20) (11)

sv(m)＝sv(m-1)+det_s(m)-det_s(m-M/20) (12)

The m frame signal with the energy difference ener2 (m) of its corresponding inhibit signal is:

$\mathrm{ener}2\left(m\right)=\mathrm{ener}2(m-1)+\underset{n=0}{\stackrel{19}{\mathrm{\&Sigma;}}}[{u(m*20+n)]}^2-u{(m*20+n-M-1)}^2]---\left(13\right)$

Detection method is: as (cv (m) ²+ sv (m) ²)＞THRES3ener2 (m) ²The time, with its phase angle of arctangent computation

Here THRES3 is decision threshold, and value of the present invention is THRES3=0.25;

If when the phase difference before and after the upset satisfies formula (15), judge that then phase place has upset, be output as 1 this moment; Otherwise the judgement phase place does not have upset, and be output as 0 this moment:

Whether B3, detection filter result be by amplitude modulation

The effect of amplitude modulation coefficient detector (40) is whether to detect input signal by amplitude modulation; Whether in the setting threshold scope, whether differentiate input signal by amplitude modulation by the amplitude modulation coefficient that relatively calculates; The input signal of amplitude modulation detector is the output u (n) that SNR strengthens filter (10), and it is output as 1, and then there is amplitude-modulated signal in expression; Be output as 0, there is not amplitude-modulated signal in expression;

At first to input signal down-sampled 80 times, method is to m frame filtering result data u (m*20)～u (m*20+19), calculates its amplitude absolute value sum:

$\mathrm{sum}20\left(m\right)=\underset{n=0}{\overset{19}{\mathrm{\&Sigma;}}}\left|u(m*20+n)\right|---\left(16\right)$

Then, calculate the amplitude absolute value sum of continuous 4 frame data, the amplitude absolute value sum equivalence of described continuous 4 frame data is 80 sampled points, is down-sampled back each point amplitude:

sum80(m)＝sum20(m)+sum20(m-1)+sum20(m-2)+sum20(m-3) (17)

Use the comparison search method, find out maximum max and minimum value min in the each point amplitude;

max=maximum{sum80(m),sum80(m-1),…,sum80(m-26)} (18)

min=minimum{sum80(m),sum80(m-1),…,sum80(m-26)} (19)

Then amplitude modulation coefficient am is:

$\mathrm{am}=\frac{\max -\min }{\max +\min }---\left(20\right)$

Work as min〉THRES4, during and THRES5＜am＜THRES6, judge there is the 15Hz modulation that be output as 1 this moment; Otherwise, be output as 0; Wherein, THRES4, THRES5, THRES6 are decision threshold, are THRES4=20480 with reference to value, THRES5=0.08, THRES6=0.26;

C, judgement input signal x (n) are the ANSam signals, or the ANS signal

The output of calculating decision device (50) result formula as a result is

result=(result1&result2)×2+result3 (21)

Wherein, “ ﹠amp; " represent logical AND operation; Result1, result2 and result3 are respectively the output result of 2100Hz detector (20), phase overturn detector (30) and amplitude modulation coefficient detector (40); The output of decision device (50) result as a result is 0 or 1, represents input signal x (n) neither the ANSam signal, neither the ANS signal; Output result as a result is 2, and representing x (n) is the ANS signal; Output result as a result is 3, and representing x (n) is the ANSam signal.

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