CN103281472B - Detection device for faxing ANSam signal and detection method thereof - Google Patents

Abstract

The invention discloses a detection device for faxing an ANSam signal and a detection method thereof. The device comprises an SNR (Signal-Noise-Ratio) enhancing filter, a 2100Hz detector, a phase overturning detector, an amplitude modulation coefficient detector and a judging device, wherein the output end of the SNR enhancing filter is connected with the 2100Hz detector, the phase overturning detector and the amplitude modulation coefficient detector respectively; and the output ends of the 2100Hz detector, the phase overturning detector and the amplitude modulation coefficient detector are connected with the judging device respectively. The 2100Hz detector is used for partitioning a period (80 points) into four parts instead of directly calculating 2100Hz frequency spectrums, and is used for calculating 2100Hz frequency spectrums indirectly according to the spectrum relation between adjacent frames, so that the calculated amount is greatly reduced. Due to the adoption of the device and the method, the complexity of a system can be lowered, the influence of frequency deviation is eliminated, and the presence of overturning and amplitude modulation signals on the phase of an input signal still can be detected accurately under low SNR.

Description

A kind of checkout gear of ANSam signal of faxing and detection method thereof

Technical field

The present invention relates to a kind of signal processing technology, particularly a kind of checkout gear of ANSam signal of faxing and detection method thereof.

Background technology

In voice and low-rate data hybrid communication system, as media gateway, fax etc., data communication often uses 2100Hz signal as the handshake between calling subscriber and called subscriber, namely uses the 2100Hz signal of different modulating form to carry certain information and carries out protocol handshake [1].Adopt signal processing technology, the information entrained by 2100Hz signal is identified, effectively can differentiate the communications status of user, so that take different processing form, improve communication quality and efficiency.

The portable information of 2100Hz signal has phase information and amplitude information, for phase information, has continuous phase information, or every 450 millisecond period upset phase informations; For amplitude information, there is the amplitude information of constant amplitude, or use the amplitude information of 15Hz Sine Wave Amplitude Modulation.

The device detecting fax ANSam signal can detect the 2100Hz signal of carry information, and carries out protocol handshake, namely whether there is 2100Hz frequency component in detection input signal, whether there is phase overturn information and whether there is 15Hz Sine Wave Amplitude Modulation.

At present, use common time frequency analysis just can realize to the detection of 2100Hz frequency, amount of calculation is larger.Detect for phase overturn, the method for employing has phase demodulating method, correlation method, phase-locked around-France.Phase demodulating method needs to produce local coherent carrier, and amount of calculation is comparatively large, and system complexity is high; Correlation method can only be applicable to the frequency of accurately precognition, and in reality, certain deviation often appears in the frequency of signal, and to this, whether it accurately detected phase can not have upset; During digital phase-locked loop detected phase, if without phase overturn, then export close to input, if there is phase overturn, output can depart from the input regular hour, and the method is simpler, but its sideband noise can reduce the reliability of detection, if add band pass filter, the sensitivity detecting phase angle upset can be reduced like this while denoising, reduce detection perform.Amplitude modulation coefficient detects the normal amplitude directly or indirectly detecting 15Hz amplitude-modulated signal, it is compared with fixed threshold, obtains court verdict, but these methods are not down-sampled to primary signal, cause the error of surveyed amplitude-modulated signal average amplitude comparatively large, certain erroneous judgement is caused to testing result.

Prior art related to the present invention is as follows:

Prior art one:

T.Trump has invented and has forbidden audio signal detector for network echo canceller, and the patent No. is CN97193286.7.First calculate first power estimation value from input signal, sent by two paths by input signal, calculate broadband power Ps and narrow band power Pt respectively, then both are compared, if Pt>Ps, then think to there is 2100Hz audio frequency.In addition, input signal is multiplied with cosine wave cos (2 π 2100t) with sinusoidal wave sin (2 π 2100t) respectively, is divided into the component of in-phase component and 90 ° of phase shifts, then to its double sampling, to sampled value summation in succession, realize low-pass filtering.If reversing appears in phase place, the second dervative of its phase place comprises two adjacent pulses with opposite polarity, but does not comprise unknown constant; Otherwise the second dervative of phase place is close to 0.Calculate second differnce and by results conversion in (-180 °, 180 °) interval, its absolute value compared with threshold value, can judge whether phase place occurs reversion.

The program is when judging whether 2100Hz audio frequency occurs, need by signal respectively by broadband and narrowband systems, therefore amount of calculation is large.In addition, when phase overturn judges, need to produce local coherent carrier, and will double sampling be carried out, which increase the computation complexity of system.Further, the program cannot detect whether there is 15Hz amplitude modulation.

Prior art two:

" the tone signal phase overturn of band amplitude-frequency feedback detects " paper that Tian Yu etc. deliver, considers that signal amplitude has comparatively great dynamic range, have employed adaptive threshold and adjudicate.The program comprises three parts: mixing, parameter Estimation, according to estimation adjudicate.Mixing is that the sine being 2100Hz the frequency that input signal produces with this locality is respectively multiplied with cosine signal, then obtains the orthogonal low frequency signal of two-way after filtering.Parameter Estimation utilizes digital phase-locked loop to process two-way orthogonal signalling, obtains corresponding frequency departure and amplitude information.Judgement utilizes the frequency departure and amplitude information estimating to obtain, compensates, enable decision threshold carry out self-adaptative adjustment according to input to input signal.

The mixing of the program needs to produce local coherent carrier; Secondly, parameter Estimation needs digital phase-locked loop, and its sideband noise can reduce the reliability of detection, if add band pass filter, can reduce the sensitivity detecting phase angle upset like this while denoising, reduce detection perform.Further, this invention cannot detect whether there is 15Hz amplitude modulation.

Prior art three:

R.L.Goodson etc. have invented a kind of device for detecting and distinguish ANSam signal.First input signal is passed through band pass filter by this device, and adopt bearing calibration and the signal after bandpass filtering is carried out low-pass filtering again, dynamically arrange the pulse distortion threshold value of input signal, this threshold value represents the excursion of low frequency amplitude-modulated signal average amplitude.By average amplitude and the threshold value of comparator input signal, thus detect that input signal is ANS signal or ANSam signal.

This device only can detect in input signal whether comprise low frequency amplitude-modulated signal, cannot detect it and whether comprises 2100Hz signal and whether there is phase overturn.

Prior art four:

Thanh Lam etc. invent a kind of device for detecting ANSam signal.This device is demodulation input signal first, then by low pass signal filtering after demodulation, obtains DC component wherein; Then, deduct the range value of DC component with the range value of input signal, obtain detected value, be i.e. the range value of 15Hz amplitude-modulated signal; Finally, detected value and the threshold value preset are compared, if detected value is greater than threshold value, judges that input signal is ANSam signal; Otherwise, judge that input signal is ANS signal.

This device by comparing detected value and threshold value judges that input signal is ANSam signal or ANS signal, and does not detect it and whether comprises 2100Hz signal, cannot judge whether it exists phase overturn yet.

Document related to the present invention is as follows:

[1]ITU-T Recommendation V.8,Procedures for Starting Sessions of DataTransmission over the Public Switched Telephone Network.2000.

[2] T.Trump. be used for network echo canceller forbid audio signal detector: China, CN1214818A.1999.

[3] Tian Yu, Li Shiju, gold is eastwards. and the tone signal phase overturn of band amplitude-frequency feedback detects. voice technology, 2004.

[4] R.L.Goodson, M.C.Rushing, G.D.Hunt.Apparatus and Method for Detectingand Discriminating Various Signal Types in the Presence of Impulse Distortions: the U.S., US 5809085.1998.

[5] T.Lam, T.Lis, R.Haltmaier.Apparatus and Method for Detecting AmplitudeModulated Answer Back Toned Signals: the U.S., US 5787116.1998.

[6]V.Bhatia,A.De,A.Gupta.A Robust Phase-reversed Tone Detection usingBispectrum and DFT-based Algorithms.20026th International Conference on SignalProcessing Proceedings,2002.

Below that the main title that the present invention relates to is explained:

The 2100Hz signal of ANSam:15Hz sinusoidal signal modulation, its Phase Continuation or every 450 milliseconds produce a phase overturn.

ANS: single-tone 2100Hz signal, its Phase Continuation or every 450 milliseconds produce a phase overturn.

DBm0: the absolute reference power of zero reference point relatively.

Summary of the invention

For solving the problems referred to above that prior art exists, the present invention will design a kind of checkout gear and the detection method thereof that can realize the fax ANSam signal of following object:

In voice and low-rate data hybrid communication system, for the digital signal received, can be detected it simply and whether comprise 2100Hz signal; If containing 2100Hz signal, can judge that whether it exists phase overturn, does not affect by frequency shift (FS), still can detect when low signal-to-noise ratio exactly; Whether correctly can detect it by 15Hz sinusoidal amplitude modulation simultaneously, namely judge it is ANS signal or ANSam signal.

To achieve these goals, technical scheme of the present invention is as follows:

To fax the checkout gear of ANSam signal, comprise SNR boostfiltering device, 2100Hz detector, phase overturn detector, amplitude modulation coefficient detector and decision device; The input of described SNR boostfiltering device inputs digital signal x (n) to be detected, and its output is connected with the input of 2100Hz detector, phase overturn detector and amplitude modulation coefficient detector respectively; The input of described decision device connects the output of 2100Hz detector, phase overturn detector and amplitude modulation coefficient detector respectively, the output output detections result of decision device;

Described SNR boostfiltering device is a centre frequency is the band pass filter of 2100Hz, its effect is the signal to noise ratio improving input signal, improve follow-up detection perform, the Reference Design index of described band pass filter is: passband frequency range: 2.05KHz ~ 2.15KHz, stop band frequency range: 0 ~ 1.1KHz and 3.1 ~ 4KHz, stopband attenuation is greater than 60dB, the Reference Design result of described SNR boostfiltering device is 10 rank Finite Impulse Response filters, and SNR boostfiltering device coefficient bpf2100 (0) ~ bpf2100 (9) is as shown in table 1:

Table 1SNR boostfiltering device coefficient table

Described SNR boostfiltering device comprises nine unit delay devices, ten multipliers and nine adders, digital signal x (n) to be detected is input to first unit delay device and first multiplier respectively, the output signal of first unit delay device is input to second unit delay device and second multiplier respectively, the output signal of second unit delay device is input to the 3rd unit delay device and the 3rd multiplier respectively, the rest may be inferred, the output signal of the 8th unit delay device is input to the 9th unit delay device and the 9th multiplier respectively, the output signal of the 9th unit delay device is finally input to the tenth multiplier, meanwhile, the coefficient bpf2100 (0) of SNR boostfiltering device is input to first multiplier, and bpf2100 (1) is input to second multiplier, and the rest may be inferred, and bpf2100 (9) is input to the tenth multiplier, the output signal of first multiplier is input to first adder, the output signal of second multiplier is input to first adder, the output signal of the 3rd multiplier is input to second adder, the output signal of the 4th multiplier is input to the 3rd adder, the rest may be inferred, and the output signal of the tenth multiplier is input to the 9th adder, the output signal of first adder is input to second adder, the output signal of second adder is input to the 3rd adder, and the rest may be inferred, and the output signal of the 8th adder is input to the 9th adder, and the output signal of the 9th adder is filter result u (n),

Described 2100Hz detector comprises present frame cosine component estimator, present frame sinusoidal component estimator, current energy estimator A, this cosine sinusoidal component estimator, there is decision device in this energy estimator and 2100Hz signal, described present frame cosine component estimator, the input of present frame sinusoidal component estimator and current energy estimator A accesses filter result u (n) simultaneously, the input of this described cosine sinusoidal component estimator connects present frame cosine component estimator and present frame sinusoidal component estimator respectively, it exports termination 2100Hz signal and there is decision device, the input termination current energy estimator A of this described energy estimator, it exports termination 2100Hz signal and there is decision device, there is decision device and directly export court verdict in 2100Hz signal, be 1 or 0,

Described present frame cosine component estimator comprises 20 multipliers, nineteen adder, present frame filter result u (m*20) is input to first multiplier, u (m*20+1) is input to second multiplier, the rest may be inferred, and u (m*20+19) is input to the 20 multiplier; Meanwhile, cosine signal be input to first multiplier, be input to second multiplier, the like, be input to the 20 multiplier; The output signal of first multiplier is input to first adder, the output signal of second multiplier is input to first adder, the output signal of the 3rd multiplier is input to second adder, the output signal of the 4th multiplier is input to the 3rd adder, the rest may be inferred, and the output signal of the 20 multiplier is input to nineteen adder; The output signal of first adder is input to second adder; The output signal of second adder is input to the 3rd adder, and the rest may be inferred, and the output signal of the 18 adder is input to nineteen adder, and the output signal of nineteen adder is present frame cosine component d21_c (m); Described m is the sequence number of present frame;

Described present frame sinusoidal component estimator comprises 20 multipliers, nineteen adder, present frame filter result u (m*20) is input to first multiplier, u (m*20+1) is input to second multiplier, the rest may be inferred, and u (m*20+19) is input to the 20 multiplier; Meanwhile, sinusoidal signal be input to first multiplier, be input to second multiplier, the like, be input to the 20 multiplier; The output signal of first multiplier is input to first adder, the output signal of second multiplier is input to first adder, the output signal of the 3rd multiplier is input to second adder, the output signal of the 4th multiplier is input to the 3rd adder, the rest may be inferred, and the output signal of the 20 multiplier is input to nineteen adder; The output signal of first adder is input to second adder; The output signal of second adder is input to the 3rd adder, and the rest may be inferred, and the output signal of the 18 adder is input to nineteen adder, and the output signal of nineteen adder is present frame sinusoidal component d21_s (m);

Described current energy estimator A comprises 20 multipliers, nineteen adder, present frame filter result u (m*20) is input to first multiplier, u (m*20+1) is input to second multiplier, the rest may be inferred, and u (m*20+19) is input to the 20 multiplier; Two input end signals of each multiplier are identical; The output signal of first multiplier is input to first adder, the output signal of second multiplier is input to first adder, the output signal of the 3rd multiplier is input to second adder, the output signal of the 4th multiplier is input to the 3rd adder, the rest may be inferred, and the output signal of the 20 multiplier is input to nineteen adder; The output signal of first adder is input to second adder; The output signal of second adder is input to the 3rd adder, and the rest may be inferred, and the output signal of the 18 adder is input to nineteen adder, and the output signal of nineteen adder is energy d21_e (m) of present frame;

This described cosine sinusoidal component estimator (204) comprises 6 unit delay devices, 2 multipliers and 6 adders, arrange by bilateral symmetry, present frame cosine component d21_c (m) is input to adder outside left upper portion unit delay device and left side first row respectively, and present frame sinusoidal component d21_s (m) is input to adder outside right upper portion unit delay device and right side first row respectively; The output of left upper portion unit delay device is connected with adder inside left side central portion unit delay device and right side first row respectively, the output of left side central portion unit delay device is connected with adder inside left lower unit delay device and left side first row respectively, and the output of left lower unit delay device is connected with adder outside the first row of right side; Inside the first row of left side, the output of adder is connected with left side multiplier, and the output of left side multiplier is connected with adder outside the second row of left side; The input termination right upper portion unit delay device of adder outside the first row of left side, adder outside second row on the left of its output termination; Outside the second row of left side, adder exports cosine component re (m) for this detects; The output of right upper portion unit delay device is connected with adder outside right side central unit delay device and left side first row respectively, the output of right side central unit delay device is connected with adder inside lower right side unit delay device and right side first row respectively, and the output of lower right side unit delay device is connected with adder inside the first row of left side; Inside the first row of right side, the output of adder is connected with right side multiplier, and the output of right side multiplier is connected with adder outside the second row of right side; Outside the first row of right side adder output termination on the right side of adder outside second row; Outside the second row of right side, adder exports sinusoidal component im (m) for this detects;

This described energy estimator comprises 3 unit delay devices and 3 adders, energy d21_e (m) of present frame is input to first unit delay device and first adder respectively, the output of first unit delay device is connected with second unit delay device and first adder respectively, the output of second unit delay device is connected with the 3rd unit delay device and second adder respectively, the output of the 3rd unit delay device is connected with the 3rd adder, the output of first adder is connected to second adder, the output of second adder is connected to the 3rd adder, energy ener (m) that 3rd adder output detects for this,

Described 2100Hz signal exist decision device comprise multiplier A, multiplier B, multiplier C, adder, comparator A, comparator B and and gate, two inputs of multiplier A all connect this cosine component re (m) detected, two inputs of the B of multiplier all connect this sinusoidal component im (m) detected, and this energy ener (m) detected meets multiplier C and comparator B respectively; The input of described adder meets multiplier A and multiplier B respectively, the output termination comparator A of adder; Another input termination multiplier C of described comparator A, the output termination of comparator A and gate, described and gate another inputs termination comparator B, exports as to judge whether 2100Hz component exists result with gate;

Described phase overturn detector comprises Hilbert transformer, present frame phase angle sinusoidal component estimator, present frame phase angle cosine component estimator, current energy estimator B and phase overturn decision device, and filter result u (n) is linked into Hilbert transformer, present frame phase angle sinusoidal component estimator, present frame phase angle cosine component estimator, current energy estimator B respectively; Described Hilbert transformer, output connects present frame phase angle sinusoidal component estimator, the input of described phase overturn decision device connects present frame phase angle sinusoidal component estimator, present frame phase angle cosine component estimator and current energy estimator B respectively, and phase overturn decision device exports as phase detection result;

Described Hilbert transformer comprises 18 unit delay devices, ten multipliers and nine adders, filtering signal u (n) is input to first unit delay device and first multiplier respectively, the output signal of first unit delay device is input to second unit delay device, second unit delay device output signal is input to the 3rd unit delay device and second multiplier respectively, the output signal of the 3rd unit delay device is input to the 4th unit delay device, 4th unit delay device output signal is input to the 5th unit delay device and the 3rd multiplier respectively, the rest may be inferred, the output signal of the 17 unit delay device is input to the 18 unit delay device, the output signal of the 18 unit delay device is finally input to the tenth multiplier, simultaneously, the coefficient h (0) of Hilbert transformer is input to first multiplier, and h (2) is input to second multiplier, and h (4) is input to the 3rd multiplier, the rest may be inferred, and h (18) is input to the tenth multiplier, the output signal of first multiplier is input to first adder, the output signal of second multiplier is input to first adder, the output signal of the 3rd multiplier is input to second adder, the output signal of the 4th multiplier is input to the 3rd adder, the rest may be inferred, and the output signal of the tenth multiplier is input to the 9th adder, the output signal of first adder is input to second adder, the output signal of second adder is input to the 3rd adder, the rest may be inferred, the output signal of the 8th adder is input to the 9th adder, and the output signal of the 9th adder is the orthogonal signalling u ' (n) after filtering signal u (n) phase shift 90 °,

Described present frame phase angle sinusoidal component estimator is divided into two parts, Part I comprises the individual unit delay device of M (in the present invention, M gets 240), present frame filter result u (m*20) ~ u (m*20+19) is input to first unit delay device, the output signal of first unit delay device is input to second unit delay device, the output signal of second unit delay device is input to the 3rd unit delay device, the rest may be inferred, the output signal of M-1 unit delay device is input to M unit delay device, inhibit signal u (m*20-M) ~ u (m*20+19-M) that M unit delay device output is present frame filter result, Part II comprises M/20 unit delay device, 21 multipliers and 21 adders, the input of first multiplier meets the inhibit signal u (m*20-M) of the orthogonal signalling u ' (m*20) after present frame filter result phase shift 90 ° and present frame filter result respectively, the input of second multiplier meets the inhibit signal u (m*20+1-M) of the orthogonal signalling u ' (m*20+1) after present frame filter result phase shift 90 ° and present frame filter result respectively, the rest may be inferred, the input of the 20 multiplier meets the inhibit signal u (m*20+19-M) of the orthogonal signalling u ' (m*20+19) after present frame filter result phase shift 90 ° and present frame filter result respectively, the output signal of first multiplier is input to first adder, the output signal of second multiplier is input to first adder, the output signal of the 3rd multiplier is input to second adder, the output signal of the 4th multiplier is input to the 3rd adder, the rest may be inferred, and the output signal of the 20 multiplier is input to nineteen adder, the output signal of first adder is input to second adder, the output signal of second adder is input to the 3rd adder, the rest may be inferred, the output signal of the 18 adder is input to nineteen adder, and the output signal of nineteen adder is input to first unit delay device and the 20 adder respectively, the output signal of first unit delay device is input to second unit delay device, the output signal of second unit delay device is input to the 3rd unit delay device, the rest may be inferred, and the output signal of M/20-1 unit delay device is input to M/20 unit delay device, the output signal of M/20 unit delay device is input to the 21 multiplier, the output signal of the 21 multiplier is input to the 20 adder, the input signal of the 21 adder meets the output signal of the 20 adder and the sinusoidal sv (m-1) of m-1 frame signal phase angle respectively, and the 21 adder output is the sinusoidal sv (m) of m frame signal phase angle,

Described present frame phase angle cosine component estimator comprises M/20 unit delay device, 21 multipliers and 21 adders, the input of first multiplier meets present frame filter result u (m*20) and its inhibit signal u (m*20-M) respectively, the input of second multiplier meets present frame filter result u (m*20+1) and its inhibit signal u (m*20+1-M) respectively, the rest may be inferred, and the input of the 20 multiplier meets present frame filter result u (m*20+19) and its inhibit signal u (m*20+19-M) respectively; The output signal of first multiplier is input to first adder, the output signal of second multiplier is input to first adder, the output signal of the 3rd multiplier is input to second adder, the output signal of the 4th multiplier is input to the 3rd adder, the rest may be inferred, and the output signal of the 20 multiplier is input to nineteen adder; The output signal of first adder is input to second adder; The output signal of second adder is input to the 3rd adder, the rest may be inferred, the output signal of the 18 adder is input to nineteen adder, and the output signal of nineteen adder is input to first unit delay device and the 20 adder respectively; The output signal of first unit delay device is input to second unit delay device, the output signal of second unit delay device is input to the 3rd unit delay device, the rest may be inferred, and the output signal of M/20-1 unit delay device is input to M/20 unit delay device; The output signal of M/20 unit delay device is input to the 21 multiplier, the output signal of the 21 multiplier is input to the 20 adder, the input signal of the 21 adder connects output signal and m-1 frame signal phase cosine of an angle cv (m-1) of the 20 adder respectively, and it is m frame signal phase cosine of an angle cv (m) that the 21 adder exports;

Described current energy estimator B comprises 40 unit delay devices, 41 multipliers and three nineteen adders, the inhibit signal u (m*20-M) of present frame filter result is input to first unit delay device and second unit delay device respectively, the inhibit signal u (m*20+1-M) of present frame filter result is input to the 3rd unit delay device and the 4th unit delay device respectively, by that analogy, the inhibit signal u (m*20+19-M) of present frame filter result is input to the 3rd nineteen unit delay device and the 40 unit delay device respectively; The input of first multiplier connects the output of first unit delay device and second unit delay device respectively, the input of second multiplier connects the output of the 3rd unit delay device and the 4th unit delay device respectively, by that analogy, the input of the 20 multiplier connects the output of the 3rd nineteen unit delay device and the 40 unit delay device respectively; The input of the 21 multiplier all meets present frame filter result u (m*20), the input of the 22 multiplier all meets present frame filter result u (m*20+1), by that analogy, the input of the 40 multiplier all meets present frame filter result u (m*20+19); The output signal of first multiplier is input to first adder, the output signal of second multiplier is input to first adder, the output signal of the 3rd multiplier is input to second adder, the output signal of the 4th multiplier is input to the 3rd adder, the rest may be inferred, and the output signal of the 20 multiplier is input to nineteen adder; The output signal of the 21 multiplier is input to the 20 adder, the output signal of the 22 multiplier is input to the 20 adder, the output signal of the 23 multiplier is input to the 21 adder, the output signal of the 24 multiplier is input to the 22 adder, the rest may be inferred, and the output signal of the 40 multiplier is input to the 38 adder; The output signal of nineteen adder is input to the 41 multiplier, the input of the 3rd nineteen adder connects the 41 multiplier and the 38 adder respectively, and the output signal of the 3rd nineteen adder is energy difference ener2 (m) of m frame signal and its corresponding inhibit signal;

Described phase overturn decision device comprises (M/20-1) individual unit delay device, four multipliers, an adder and two comparators, the input signal of first multiplier all meets m frame signal phase cosine of an angle cv (m), the input signal of second multiplier all meets m frame signal phase cosine of an angle sv (m), the input signal of the 3rd multiplier all connects energy difference ener2 (m) of m frame signal and its corresponding inhibit signal, and the output signal of the 3rd multiplier is input to the 4th multiplier; The input signal of first adder connects the output signal of first multiplier and the output signal of second multiplier respectively; The input signal of first comparator connects the output signal of first adder and the output signal of the 4th multiplier respectively; The output signal of first comparator is input to first unit delay device and second comparator respectively; The output signal of first unit delay device is input to second unit delay device, the output signal of second unit delay device is input to the 3rd unit delay device, by that analogy, the output signal of (M/20-2) individual unit delay device is input to (M/20-1) individual unit delay device, the output signal of (M/20-1) individual unit delay device is input to second comparator, and the output of second comparator is phase overturn court verdict;

Described amplitude modulation coefficient detector comprises present frame decimator and amplitude modulation coefficient decision device, filtering signal u (n) is input to present frame decimator, the output of present frame decimator is connected with amplitude modulation coefficient decision device, and whether the output of amplitude modulation coefficient decision device exists result for adjudicating amplitude-modulated signal;

Described present frame decimator comprises three unit delay devices and 22 adders, present frame filter result amplitude | u (m*20) | be input to first adder, present frame filter result amplitude | u (m*20+1) | be input to first adder, present frame filter result amplitude | u (m*20+2) | be input to second adder, present frame filter result amplitude | u (m*20+3) | be input to the 3rd adder, by that analogy, present frame filter result amplitude | u (m*20+19) | be input to nineteen adder, the output signal of nineteen adder is input to first unit delay device and the 20 adder respectively, the output signal of first unit delay device is input to second unit delay device and the 20 adder respectively, the output signal of second unit delay device is input to the 3rd unit delay device and the 21 adder, and the output signal of the 3rd unit delay device is input to the 22 adder, the output signal of the 20 adder is input to the 21 adder, the output signal of the 21 adder is input to the 22 adder, and the output of the 22 adder is minimum value min, maximum max in down-sampled rear each point amplitude and amplitude modulation coefficient am,

Described amplitude modulation coefficient decision device comprises 3 comparators and 2 and gate; The input signal of first comparator meets minimum value min in down-sampled rear each point amplitude and threshold value THRES4 respectively, the input signal of second comparator meets amplitude modulation coefficient am and threshold value THRES5 respectively, and the input signal of the 3rd comparator meets amplitude modulation coefficient am and threshold value THRES6 respectively; First is connected first comparator and second comparator respectively with the input of gate, its output connects second and gate, the output of the 3rd comparator connects second and gate, and whether second exist result with the output of gate for adjudicating amplitude-modulated signal;

Described decision device comprises one and gate, a multiplier and an adder; Be respectively 2100Hz detector Output rusults and phase overturn detector Output rusults with the input signal of gate, be input to multiplier with the output signal of gate; The input signal of adder is respectively output signal and the amplitude modulation coefficient detector Output rusults of multiplier, and the output of adder is the court verdict to input signal x (n).

To fax the detection method of checkout gear of ANSam signal, comprise the following steps:

A, filtering is carried out to input signal

The to be detected digital signal x (n) of SNR boostfiltering device to input carries out filtering, and output filtering result u (n), namely

$u\left(n\right)=\underset{k=0}{\overset{9}{\mathrm{\Σ}}}\mathrm{bpf}2100\left(k\right)\·x(n-k)---\left(1\right)$

Wherein, x (n-k) is the input signal in the n-th-k moment, and u (n) is the filter result in n moment, and bpf2100 (k) is a kth filter coefficient;

B, filter result to be adjudicated

Whether B1, detection filter result comprise 2100Hz signal

Whether 2100Hz detector is for detecting digital signal x (n) to be detected containing 2100Hz component, the input signal of 2100Hz detector is filter result u (n) of SNR boostfiltering device, the output of 2100Hz detector is the result whether detection 2100Hz exists, if result is 0, represent there is not 2100Hz signal; If result is 1, then represent to there is 2100Hz signal;

Every 2.5 milliseconds of 2100Hz detector detects once, and when input signal sample frequency is 8KHz, be equivalent to 20 sampled points, namely data frame length is 20; If present frame is m frame, then the data of present frame are u (m*20) ~ u (m*20+19); Cosine component d21_c (m), sinusoidal component d21_s (m) of present frame are respectively with the method for estimation of energy d21_e (m):

$d21\_c\left(m\right)=\underset{n=0}{\overset{19}{\mathrm{\Σ}}}u(m*20+n)\cos \frac{2\mathrm{\π}\·2100n}{8000}---\left(2\right)$

$d21\_s\left(m\right)=-\underset{n=0}{\overset{19}{\mathrm{\Σ}}}u(m*20+n)\sin \frac{2\mathrm{\π}\·2100n}{8000}---\left(3\right)$

$d21\_e\left(m\right)=\underset{n=0}{\overset{19}{\mathrm{\Σ}}}{u}^2(m*20+n)---\left(4\right)$

The method of estimation of this cosine component re (m) detected, sinusoidal component im (m) and energy ener (m) is respectively:

re(m)＝d21_c[m]+d21_s[m-1]-d21_c[m-2]-d21_s[m-3] (5)

im(m)＝d21_s[m]-d21_c[m-1]-d21_s[m-2]+d21_c[m-3] (6)

ener(m)＝d21_e[m]+d21_e[m-1]+d21_e[m-2]+d21_e[m-3] (7)

Judge that the method whether 2100Hz signal exists is:

Work as re ²(m)+im ²(m) >THRES1ener (m), and during ener (m) >THRES2, be judged to 2100Hz signal and exist; Otherwise be judged to 2100Hz signal not exist; Here THRES1, THRES2 are decision threshold, are THRES1=20, THRES2=5242880 with reference to value;

B2, detection filter result whether phase overturn

The effect of phase overturn detector detects input signal whether to have phase overturn, and can estimate phase overturn angle; The input signal of phase overturn detector is the output signal u (n) of SNR boostfiltering device, and the output of phase overturn detector is the result whether phase place overturns, if result is 0, indicates without upset; If result is 1, then indicate upset;

First filter result u (n) phase shift 90 ° is obtained u ' (n).90 ° of phase shifts are realized by Hilbert transformer, and its coefficient h (0) ~ h (18) is as shown in table 2:

Table 2 Hilbert transformer coefficient table

h(0)	-0.070735530263065		h(10)	0.636619772367581
					h(1)	0		h(11)	0
h(2)	-0.090945681766797		h(12)	0.212206590789194
					h(3)	0		h(13)	0
h(4)	-0.127323954473516		h(14)	0.127323954473516
					h(5)	0		h(15)	0
h(6)	-0.212206590789194		h(16)	0.090945681766797
					h(7)	0		h(17)	0
h(8)	-0.636619772367581		h(18)	0.070735530263065
					h(9)	0

Hilbert transform is:

$u^{\′}\left(n\right)=\underset{k=0}{\overset{9}{\mathrm{\Σ}}}h\left(2k\right)u(n-2k)---\left(8\right)$

Wherein, u ' (n) is the output of n moment phase shift 90 °, the input that u (n-2k) is the n-2k moment, and h (2k) is 2k Hilbert transformer coefficient;

Phase overturn detector module remains every 2.5 milliseconds and detects once, data frame length is 20, the filter result data of m frame are u (m*20) ~ u (m*20+19), and after its phase shift 90 °, data are u ' (m*20) ~ u ' (m*20+19); For m frame filter result time delayed signal u (m*20-M) ~ u (m*20+19-M), M are time of delay (M is constant, and the present invention gets M=240); It is multiplied with data u ' (m*20) ~ u ' (m*20+19) after m frame filter result data u (m*20) ~ u (m*20+19), m frame filter result phase shift 90 ° respectively, respectively low-pass filtering is carried out to product signal, obtains det_c (m), the method for estimation of det_s (m) is:

$\det \_c\left(m\right)=\underset{n=0}{\overset{19}{\mathrm{\Σ}}}u(m*20+n)\·u(m*20+n-M)---\left(9\right)$

$d21\_c\left(m\right)=\underset{n=0}{\overset{19}{\mathrm{\Σ}}}{u}^{\′}(m*20+n)\·u(m*20+n-M)---\left(10\right)$

M frame signal phase cosine of an angle cv, sinusoidal sv divide amount estimation method to be:

cv(m)＝cv(m-1)+det_c(m)-det_c(m-M/20) (11)

sv(m)＝sv(m-1)+det_s(m)-det_s(m-M/20) (12)

Energy difference ener2 (m) of m frame signal inhibit signal corresponding to it is:

$\mathrm{ener}2\left(m\right)=\mathrm{ener}2(m-1)+\underset{n=0}{\overset{19}{\mathrm{\Σ}}}{\left[u(m*20+n)\right]}^2-u{(m*20+n-M-1)}^2]---\left(13\right)$

Detection method is: as [cv ²(m)+sv ²(m)] >THRES3 [ener2 (m)] ²time, with its phase angle of arctangent computation

Here THRES3 is decision threshold, and value of the present invention is THRES3=0.25;

If when the phase difference before and after upset meets formula (15), then judge that phase place has upset, now exporting is 1; Otherwise judge that phase place is without upset, now exporting is 0:

Whether B3, detection filter result be by amplitude modulation

The effect of amplitude modulation coefficient detector whether detects input signal by amplitude modulation; By comparing the amplitude modulation coefficient that calculates whether within the scope of setting threshold, differentiate that whether input signal is by amplitude modulation; The input signal of amplitude modulation detector is output u (n) of SNR boostfiltering device, and its output is 1, then represent to there is amplitude-modulated signal; Output is 0, represents to there is not amplitude-modulated signal;

First to input signal down-sampled 80 times, method is to m frame filter result data u (m*20) ~ u (m*20+19), calculates its amplitude absolute value sum:

$\mathrm{sum}20\left(m\right)=\underset{n=0}{\overset{19}{\mathrm{\Σ}}}\left|u(m*20+n)\right|---\left(16\right)$

Then, calculate the amplitude absolute value sum of continuous 4 frame data, the amplitude absolute value sum of described continuous 4 frame data is equivalent to 80 sampled points, is down-sampled rear each point amplitude:

sum 80(m)＝sum 20(m)+sum20(m-1)+sum 20(m-2)+sum20(m-3) (17)

Use comparison search method, find out the maximum max in each point amplitude and minimum value min;

max＝maximum{sum80(m),sum80(m-1),…,sum80(m-26)} (18)

min＝minimum{sum80(m),sum80(m-1),…,sum80(m-26)} (19)

Then amplitude modulation coefficient am is:

$\mathrm{am}=\frac{\max -\min }{\max +\min }---\left(20\right)$

Work as min>THRES4, and during THRES5<am<THRES6, judge to there is 15Hz modulation, now exporting is 1; Otherwise output is 0; Wherein, THRES4, THRES5, THRES6 are decision threshold, are THRES4=20480, THRES5=0.08, THRES6=0.26 with reference to value;

C, judgement input signal x (n) are ANSam signals, or ANS signal

The Output rusults result formula calculating decision device is

result＝(result1&result2)×2+result3 (21)

Wherein, " & " represents logical AND operation; Result1, result2 and result3 are respectively the Output rusults of 2100Hz detector, phase overturn detector and amplitude modulation coefficient detector; The Output rusults result of decision device is 0 or 1, represents input signal x (n) neither ANSam signal, neither ANS signal; Output rusults result is 2, and representing x (n) is ANS signal; Output rusults result is 3, and representing x (n) is ANSam signal.

Compared with prior art, the present invention has following beneficial effect:

1,2100Hz detector of the present invention is not directly calculate 2100Hz frequency spectrum, but one-period (80 point) is divided into 4 parts, and according to the Spectrum Relationship of consecutive frame, indirect calculation 2100Hz frequency spectrum, reduces amount of calculation significantly.

2, phase overturn detector of the present invention adopts feed-forward structure, the low pass filter with homophase and quadrature phase passage, calculates phase angle, the difference of phase angle before and after upset place and the threshold value of setting is compared, judged whether phase overturn.By being in reason to code book, homophase and the signal of orthogonal phase angle can being obtained, do not need to produce local coherent carrier, therefore, it is possible to reduce the complexity of system, simultaneously not by the impact of frequency shift (FS), under low signal-to-noise ratio, still can detect accurately.

3, amplitude modulation coefficient detector of the present invention is first down-sampled, then indirect calculation amplitude modulation coefficient, can improve the accuracy of systems axiol-ogy, reduces error.

Accompanying drawing explanation

The present invention has 20, accompanying drawing, wherein:

Fig. 1 is ANSam signal supervisory instrument block diagram.

Fig. 2 is SNR boostfiltering device block diagram.

Fig. 3 is 2100Hz detector block diagram.

Fig. 4 is present frame cosine component estimator block diagram.

Fig. 5 is present frame sinusoidal component estimator block diagram.

Fig. 6 is current energy estimator A block diagram.

Fig. 7 is this cosine, sinusoidal component estimator block diagram.

Fig. 8 is this energy estimator block diagram.

Fig. 9 is that 2100Hz signal exists decision device block diagram.

Figure 10 is phase overturn detector block diagram.

Figure 11 is Hilbert transformer block diagram.

Figure 12 is present frame phase angle sinusoidal component estimator block diagram.

Figure 13 is present frame phase angle cosine component estimator block diagram.

Figure 14 is current energy estimator B block diagram.

Figure 15 is phase overturn decision device device block diagram.

Figure 16 is amplitude modulation coefficient detector block diagram.

Figure 17 is present frame decimator block diagram.

Figure 18 is amplitude modulation coefficient decision device block diagram.

Figure 19 is decision device block diagram.

Figure 20 is the detection method block diagram of fax ANSam signal.

In figure: 10, SNR boostfiltering device, 20, 2100Hz detector, 30, phase overturn detector, 40, amplitude modulation coefficient detector, 50, decision device, 201, present frame cosine component estimator, 202, present frame sinusoidal component estimator, 203, current energy estimator, 204, this cosine sinusoidal component estimator, 205, this energy estimator, 206, there is decision device in 2100Hz signal, 301, Hilbert transformer, 302, present frame phase angle sinusoidal component estimator, 303, present frame phase angle cosine component estimator, 304, current energy estimator, 305, phase overturn decision device, 401, present frame decimator, 402, amplitude modulation coefficient decision device.

Embodiment

Below in conjunction with accompanying drawing, the present invention is described further.As shown in Fig. 1-18, a kind of checkout gear of ANSam signal of faxing, comprises SNR boostfiltering device 10,2100Hz detector 20, phase overturn detector 30, amplitude modulation coefficient detector 40 and decision device 50; The input of described SNR boostfiltering device 10 inputs digital signal x (n) to be detected, and its output is connected with the input of 2100Hz detector 20, phase overturn detector 30 and amplitude modulation coefficient detector 40 respectively; The input of described decision device 50 connects the output of 2100Hz detector 20, phase overturn detector 30 and amplitude modulation coefficient detector 40 respectively, the output output detections result of decision device 50;

Described SNR boostfiltering device 10 is centre frequencies is the band pass filter of 2100Hz, its effect is the signal to noise ratio improving input signal, improve follow-up detection perform, the Reference Design index of described band pass filter is: passband frequency range: 2.05KHz ~ 2.15KHz, stop band frequency range: 0 ~ 1.1KHz and 3.1 ~ 4KHz, stopband attenuation is greater than 60dB, the Reference Design result of described SNR boostfiltering device 10 is 10 rank Finite Impulse Response filters, and SNR boostfiltering device 10 coefficient bpf2100 (0) ~ bpf2100 (9) is as shown in table 1.

Described 2100Hz detector 20 comprises present frame cosine component estimator 201, present frame sinusoidal component estimator 202, current energy estimator A203, this cosine sinusoidal component estimator 204, there is decision device 206 in this energy estimator 205 and 2100Hz signal, described tune present frame cosine component estimator 201, the input of present frame sinusoidal component estimator 202 and current energy estimator A203 accesses filter result u (n) simultaneously, the input of this described cosine sinusoidal component estimator 204 connects respectively adjusts present frame cosine component estimator 201 and present frame sinusoidal component estimator 202, it exports termination 2100Hz signal and there is decision device 206, the input termination current energy estimator A203 of this described energy estimator 205, it exports termination 2100Hz signal and there is decision device 206, there is decision device 206 and directly export court verdict in 2100Hz signal, be 1 or 0,

Described phase overturn detector 30 comprises Hilbert transformer 301, present frame phase angle sinusoidal component estimator 302, present frame phase angle cosine component estimator 303, current energy estimator B304 and phase overturn decision device 305, and filter result u (n) is linked into Hilbert transformer 301, present frame phase angle sinusoidal component estimator 302, present frame phase angle cosine component estimator 303, current energy estimator B304 respectively; Described Hilbert transformer 301, output connects present frame phase angle sinusoidal component estimator 302, the input of described phase overturn decision device 305 connects present frame phase angle sinusoidal component estimator 302, present frame phase angle cosine component estimator 303 and current energy estimator B304 respectively, and phase overturn decision device 305 exports as phase detection result;

Described amplitude modulation coefficient detector 40 comprises present frame decimator 401 and amplitude modulation coefficient decision device 402, filtering signal u (n) is input to present frame decimator 401, the output of present frame decimator 401 is connected with amplitude modulation coefficient decision device 402, and whether the output of amplitude modulation coefficient decision device 402 exists result for adjudicating amplitude-modulated signal;

Described decision device 50 comprises one and gate, a multiplier and an adder; Be respectively 2100Hz detector 20 Output rusults and phase overturn detector 30 Output rusults with the input signal of gate, be input to multiplier with the output signal of gate; The input signal of adder is respectively output signal and amplitude modulation coefficient detector 40 Output rusults of multiplier, and the output of adder is the court verdict to input signal x (n).

As shown in figures 1-19, a kind of detection method of checkout gear of ANSam signal of faxing, comprises the following steps:

A, filtering is carried out to input signal

The to be detected digital signal x (n) of SNR boostfiltering device 10 to input carries out filtering, and output filtering result u (n), namely

$u\left(n\right)=\underset{k=0}{\overset{9}{\mathrm{\&Sigma;}}}\mathrm{bpf}2100\left(k\right)\&CenterDot;x(n-k)---\left(1\right)$

Wherein, x (n-k) is the input signal in the n-th-k moment, and u (n) is the filter result in n moment, and bpf2100 (k) is a kth filter coefficient;

B, filter result to be adjudicated

Whether B1, detection filter result comprise 2100Hz signal

B2, detection filter result whether phase overturn

Whether B3, detection filter result be by amplitude modulation

C, judgement input signal x (n) are ANSam signals, or ANS signal

The Output rusults result formula calculating decision device 50 is

result＝(result1&result2)×2+result3 (21)

Wherein, " & " represents logical AND operation; Result1, result2 and result3 are respectively the Output rusults of 2100Hz detector 20, phase overturn detector 30 and amplitude modulation coefficient detector 40; The Output rusults result of decision device 50 is 0 or 1, represents input signal x (n) neither ANSam signal, neither ANS signal; Output rusults result is 2, and representing x (n) is ANS signal; Output rusults result is 3, and representing x (n) is ANSam signal.

In order to verify validity of the present invention, some tests are carried out.In different signal to noise ratio (additive white Gaussian noise) situation, the frequency range of input measured signal is 2040Hz ~ 2160Hz, and phase overturn angular range is 140 ° ~ 220 °, and amplitude modulation coefficient scope is 0.05 ~ 0.30.The scope of detection effective frequency of the present invention, phase overturn angle, amplitude modulation coefficient etc. is as shown in table 3.From test result: under usual signal to noise ratio condition, detection range is substantially constant; Under very low signal-to-noise ratio (5dB) condition, detection perform has and declines by a small margin, but still can meet application request.Testing result illustrates, the present invention has good detection perform and good working robust.

Table 3 detection perform of the present invention

Claims (2)

1. to fax the checkout gear of ANSam signal, it is characterized in that: comprise SNR boostfiltering device (10), 2100Hz detector (20), phase overturn detector (30), amplitude modulation coefficient detector (40) and decision device (50); The input of described SNR boostfiltering device (10) inputs digital signal x (n) to be detected, and its output is connected with the input of 2100Hz detector (20), phase overturn detector (30) and amplitude modulation coefficient detector (40) respectively; The input of described decision device (50) connects the output of 2100Hz detector (20), phase overturn detector (30) and amplitude modulation coefficient detector (40) respectively, the output output detections result of decision device (50);

Described SNR boostfiltering device (10) is a centre frequency is the band pass filter of 2100Hz, its effect is the signal to noise ratio improving input signal, improve follow-up detection perform, the Reference Design index of described band pass filter is: passband frequency range: 2.05KHz ~ 2.15KHz, stop band frequency range: 0 ~ 1.1KHz and 3.1 ~ 4KHz, stopband attenuation is greater than 60dB, the Reference Design result of described SNR boostfiltering device (10) is 10 rank Finite Impulse Response filters, SNR boostfiltering device (10) coefficient bpf2100 (0) ~ bpf2100 (9) value is as follows:

bpf2100(0)＝0.003591632534094；bpf2100(5)＝0.2927317757571；

bpf2100(1)＝0.05416798502494；bpf2100(6)＝-0.2523686814106；

bpf2100(2)＝-0.09780767260372；bpf2100(7)＝-0.09780767260372；

bpf2100(3)＝-0.2523686814106；bpf2100(8)＝0.05416798502494；

bpf2100(4)＝0.2927317757571；bpf2100(9)＝0.003591632534094；

Described SNR boostfiltering device (10) comprises nine unit delay devices, ten multipliers and nine adders, digital signal x (n) to be detected is input to first unit delay device and first multiplier respectively, the output signal of first unit delay device is input to second unit delay device and second multiplier respectively, the output signal of second unit delay device is input to the 3rd unit delay device and the 3rd multiplier respectively, the rest may be inferred, the output signal of the 8th unit delay device is input to the 9th unit delay device and the 9th multiplier respectively, the output signal of the 9th unit delay device is finally input to the tenth multiplier, simultaneously, the coefficient bpf2100 (0) of SNR boostfiltering device (10) is input to first multiplier, bpf2100 (1) is input to second multiplier, and the rest may be inferred, and bpf2100 (9) is input to the tenth multiplier, the output signal of first multiplier is input to first adder, the output signal of second multiplier is input to first adder, the output signal of the 3rd multiplier is input to second adder, the output signal of the 4th multiplier is input to the 3rd adder, the rest may be inferred, and the output signal of the tenth multiplier is input to the 9th adder, the output signal of first adder is input to second adder, the output signal of second adder is input to the 3rd adder, and the rest may be inferred, and the output signal of the 8th adder is input to the 9th adder, and the output signal of the 9th adder is filter result u (n),

Described 2100Hz detector (20) comprises present frame cosine component estimator (201), present frame sinusoidal component estimator (202), current energy estimator A (203), this cosine sinusoidal component estimator (204), there is decision device (206) in this energy estimator (205) and 2100Hz signal, described present frame cosine component estimator (201), the input of present frame sinusoidal component estimator (202) and current energy estimator A (203) accesses filter result u (n) simultaneously, the input of this described cosine sinusoidal component estimator (204) connects present frame cosine component estimator (201) and present frame sinusoidal component estimator (202) respectively, it exports termination 2100Hz signal and there is decision device (206), input termination current energy estimator A (203) of described this energy estimator (205), it exports termination 2100Hz signal and there is decision device (206), there is decision device (206) and directly export court verdict in 2100Hz signal, be 1 or 0,

Described present frame cosine component estimator (201) comprises 20 multipliers, nineteen adder, present frame filter result u (m*20) is input to first multiplier, u (m*20+1) is input to second multiplier, the rest may be inferred, and u (m*20+19) is input to the 20 multiplier; Meanwhile, cosine signal be input to first multiplier, be input to second multiplier, the like, be input to the 20 multiplier; The output signal of first multiplier is input to first adder, the output signal of second multiplier is input to first adder, the output signal of the 3rd multiplier is input to second adder, the output signal of the 4th multiplier is input to the 3rd adder, the rest may be inferred, and the output signal of the 20 multiplier is input to nineteen adder; The output signal of first adder is input to second adder; The output signal of second adder is input to the 3rd adder, and the rest may be inferred, and the output signal of the 18 adder is input to nineteen adder, and the output signal of nineteen adder is present frame cosine component d21_c (m); Described m is the sequence number of present frame;

Described present frame sinusoidal component estimator (202) comprises 20 multipliers, nineteen adder, present frame filter result u (m*20) is input to first multiplier, u (m*20+1) is input to second multiplier, the rest may be inferred, and u (m*20+19) is input to the 20 multiplier; Meanwhile, sinusoidal signal be input to first multiplier, be input to second multiplier, the like, be input to the 20 multiplier; The output signal of first multiplier is input to first adder, the output signal of second multiplier is input to first adder, the output signal of the 3rd multiplier is input to second adder, the output signal of the 4th multiplier is input to the 3rd adder, the rest may be inferred, and the output signal of the 20 multiplier is input to nineteen adder; The output signal of first adder is input to second adder; The output signal of second adder is input to the 3rd adder, and the rest may be inferred, and the output signal of the 18 adder is input to nineteen adder, and the output signal of nineteen adder is present frame sinusoidal component d21_s (m);

Described current energy estimator A (203) comprises 20 multipliers, nineteen adder, present frame filter result u (m*20) is input to first multiplier, u (m*20+1) is input to second multiplier, the rest may be inferred, and u (m*20+19) is input to the 20 multiplier; Two input end signals of each multiplier are identical; The output signal of first multiplier is input to first adder, the output signal of second multiplier is input to first adder, the output signal of the 3rd multiplier is input to second adder, the output signal of the 4th multiplier is input to the 3rd adder, the rest may be inferred, and the output signal of the 20 multiplier is input to nineteen adder; The output signal of first adder is input to second adder; The output signal of second adder is input to the 3rd adder, and the rest may be inferred, and the output signal of the 18 adder is input to nineteen adder, and the output signal of nineteen adder is energy d21_e (m) of present frame;

This described cosine sinusoidal component estimator (204) comprises 6 unit delay devices, 2 multipliers and 6 adders, arrange by bilateral symmetry, present frame cosine component d21_c (m) is input to adder outside left upper portion unit delay device and left side first row respectively, and present frame sinusoidal component d21_s (m) is input to adder outside right upper portion unit delay device and right side first row respectively; The output of left upper portion unit delay device is connected with adder inside left side central portion unit delay device and right side first row respectively, the output of left side central portion unit delay device is connected with adder inside left lower unit delay device and left side first row respectively, and the output of left lower unit delay device is connected with adder outside the first row of right side; Inside the first row of left side, the output of adder is connected with left side multiplier, and the output of left side multiplier is connected with adder outside the second row of left side; The input termination right upper portion unit delay device of adder outside the first row of left side, adder outside second row on the left of its output termination; Outside the second row of left side, adder exports cosine component re (m) for this detects; The output of right upper portion unit delay device is connected with adder outside right side central unit delay device and left side first row respectively, the output of right side central unit delay device is connected with adder inside lower right side unit delay device and right side first row respectively, and the output of lower right side unit delay device is connected with adder inside the first row of left side; Inside the first row of right side, the output of adder is connected with right side multiplier, and the output of right side multiplier is connected with adder outside the second row of right side; Outside the first row of right side adder output termination on the right side of adder outside second row; Outside the second row of right side, adder exports sinusoidal component im (m) for this detects;

Described this energy estimator (205) comprises 3 unit delay devices and 3 adders, energy d21_e (m) of present frame is input to first unit delay device and first adder respectively, the output of first unit delay device is connected with second unit delay device and first adder respectively, the output of second unit delay device is connected with the 3rd unit delay device and second adder respectively, the output of the 3rd unit delay device is connected with the 3rd adder, the output of first adder is connected to second adder, the output of second adder is connected to the 3rd adder, energy ener (m) that 3rd adder output detects for this,

Described 2100Hz signal exist decision device (206) comprise multiplier A, multiplier B, multiplier C, adder, comparator A, comparator B and and gate, two inputs of multiplier A all connect this cosine component re (m) detected, two inputs of the B of multiplier all connect this sinusoidal component im (m) detected, and this energy ener (m) detected meets multiplier C and comparator B respectively; The input of described adder meets multiplier A and multiplier B respectively, the output termination comparator A of adder; Another input termination multiplier C of described comparator A, the output termination of comparator A and gate, described and gate another inputs termination comparator B, exports as to judge whether 2100Hz component exists result with gate;

Described phase overturn detector (30) comprises Hilbert transformer (301), present frame phase angle sinusoidal component estimator (302), present frame phase angle cosine component estimator (303), current energy estimator B (304) and phase overturn decision device (305), and filter result u (n) is linked into Hilbert transformer (301), present frame phase angle sinusoidal component estimator (302), present frame phase angle cosine component estimator (303), current energy estimator B (304) respectively; Described Hilbert transformer (301), output connects present frame phase angle sinusoidal component estimator (302), the input of described phase overturn decision device (305) connects present frame phase angle sinusoidal component estimator (302), present frame phase angle cosine component estimator (303) and current energy estimator B (304) respectively, and phase overturn decision device (305) exports as phase detection result;

Described Hilbert transformer (301) comprises 18 unit delay devices, ten multipliers and nine adders, filtering signal u (n) is input to first unit delay device and first multiplier respectively, the output signal of first unit delay device is input to second unit delay device, second unit delay device output signal is input to the 3rd unit delay device and second multiplier respectively, the output signal of the 3rd unit delay device is input to the 4th unit delay device, 4th unit delay device output signal is input to the 5th unit delay device and the 3rd multiplier respectively, the rest may be inferred, the output signal of the 17 unit delay device is input to the 18 unit delay device, the output signal of the 18 unit delay device is finally input to the tenth multiplier, simultaneously, the coefficient h (0) of Hilbert transformer (301) is input to first multiplier, and h (2) is input to second multiplier, and h (4) is input to the 3rd multiplier, the rest may be inferred, and h (18) is input to the tenth multiplier, the output signal of first multiplier is input to first adder, the output signal of second multiplier is input to first adder, the output signal of the 3rd multiplier is input to second adder, the output signal of the 4th multiplier is input to the 3rd adder, the rest may be inferred, and the output signal of the tenth multiplier is input to the 9th adder, the output signal of first adder is input to second adder, the output signal of second adder is input to the 3rd adder, the rest may be inferred, the output signal of the 8th adder is input to the 9th adder, and the output signal of the 9th adder is the orthogonal signalling u ' (n) after filtering signal u (n) phase shift 90 °,

Described present frame phase angle sinusoidal component estimator (302) is divided into two parts, Part I comprises M unit delay device, described M value 240, present frame filter result u (m*20) ~ u (m*20+19) is input to first unit delay device, the output signal of first unit delay device is input to second unit delay device, the output signal of second unit delay device is input to the 3rd unit delay device, the rest may be inferred, the output signal of M-1 unit delay device is input to M unit delay device, inhibit signal u (m*20-M) ~ u (m*20+19-M) that M unit delay device output is present frame filter result, Part II comprises M/20 unit delay device, 21 multipliers and 21 adders, the input of first multiplier meets the inhibit signal u (m*20-M) of the orthogonal signalling u ' (m*20) after present frame filter result phase shift 90 ° and present frame filter result respectively, the input of second multiplier meets the inhibit signal u (m*20+1-M) of the orthogonal signalling u ' (m*20+1) after present frame filter result phase shift 90 ° and present frame filter result respectively, the rest may be inferred, the input of the 20 multiplier meets the inhibit signal u (m*20+19-M) of the orthogonal signalling u ' (m*20+19) after present frame filter result phase shift 90 ° and present frame filter result respectively, the output signal of first multiplier is input to first adder, the output signal of second multiplier is input to first adder, the output signal of the 3rd multiplier is input to second adder, the output signal of the 4th multiplier is input to the 3rd adder, the rest may be inferred, and the output signal of the 20 multiplier is input to nineteen adder, the output signal of first adder is input to second adder, the output signal of second adder is input to the 3rd adder, the rest may be inferred, the output signal of the 18 adder is input to nineteen adder, and the output signal of nineteen adder is input to first unit delay device and the 20 adder respectively, the output signal of first unit delay device is input to second unit delay device, the output signal of second unit delay device is input to the 3rd unit delay device, the rest may be inferred, and the output signal of M/20-1 unit delay device is input to M/20 unit delay device, the output signal of M/20 unit delay device is input to the 21 multiplier, the output signal of the 21 multiplier is input to the 20 adder, the input signal of the 21 adder meets the output signal of the 20 adder and the sinusoidal sv (m-1) of m-1 frame signal phase angle respectively, and the 21 adder output is the sinusoidal sv (m) of m frame signal phase angle,

Described present frame phase angle cosine component estimator (303) comprises M/20 unit delay device, 21 multipliers and 21 adders, the input of first multiplier meets present frame filter result u (m*20) and its inhibit signal u (m*20-M) respectively, the input of second multiplier meets present frame filter result u (m*20+1) and its inhibit signal u (m*20+1-M) respectively, the rest may be inferred, and the input of the 20 multiplier meets present frame filter result u (m*20+19) and its inhibit signal u (m*20+19-M) respectively; The output signal of first multiplier is input to first adder, the output signal of second multiplier is input to first adder, the output signal of the 3rd multiplier is input to second adder, the output signal of the 4th multiplier is input to the 3rd adder, the rest may be inferred, and the output signal of the 20 multiplier is input to nineteen adder; The output signal of first adder is input to second adder; The output signal of second adder is input to the 3rd adder, the rest may be inferred, the output signal of the 18 adder is input to nineteen adder, and the output signal of nineteen adder is input to first unit delay device and the 20 adder respectively; The output signal of first unit delay device is input to second unit delay device, the output signal of second unit delay device is input to the 3rd unit delay device, the rest may be inferred, and the output signal of M/20-1 unit delay device is input to M/20 unit delay device; The output signal of M/20 unit delay device is input to the 21 multiplier, the output signal of the 21 multiplier is input to the 20 adder, the input signal of the 21 adder connects output signal and m-1 frame signal phase cosine of an angle cv (m-1) of the 20 adder respectively, and it is m frame signal phase cosine of an angle cv (m) that the 21 adder exports;

Described current energy estimator B (304) comprises 40 unit delay devices, 41 multipliers and three nineteen adders, the inhibit signal u (m*20-M) of present frame filter result is input to first unit delay device and second unit delay device respectively, the inhibit signal u (m*20+1-M) of present frame filter result is input to the 3rd unit delay device and the 4th unit delay device respectively, by that analogy, the inhibit signal u (m*20+19-M) of present frame filter result is input to the 3rd nineteen unit delay device and the 40 unit delay device respectively, the input of first multiplier connects the output of first unit delay device and second unit delay device respectively, the input of second multiplier connects the output of the 3rd unit delay device and the 4th unit delay device respectively, by that analogy, the input of the 20 multiplier connects the output of the 3rd nineteen unit delay device and the 40 unit delay device respectively, the input of the 21 multiplier all meets present frame filter result u (m*20), the input of the 22 multiplier all meets present frame filter result u (m*20+1), by that analogy, the input of the 40 multiplier all meets present frame filter result u (m*20+19), the output signal of first multiplier is input to first adder, the output signal of second multiplier is input to first adder, the output signal of the 3rd multiplier is input to second adder, the output signal of the 4th multiplier is input to the 3rd adder, the rest may be inferred, and the output signal of the 20 multiplier is input to nineteen adder, the output signal of the 21 multiplier is input to the 20 adder, the output signal of the 22 multiplier is input to the 20 adder, the output signal of the 23 multiplier is input to the 21 adder, the output signal of the 24 multiplier is input to the 22 adder, the rest may be inferred, and the output signal of the 40 multiplier is input to the 38 adder, the output signal of nineteen adder is input to the 41 multiplier, the input of the 3rd nineteen adder connects the 41 multiplier and the 38 adder respectively, and the output signal of the 3rd nineteen adder is energy difference ener2 (m) of m frame signal and its corresponding inhibit signal,

Described phase overturn decision device (305) comprises (M/20-1) individual unit delay device, four multipliers, an adder and two comparators, the input signal of first multiplier all meets m frame signal phase cosine of an angle cv (m), the input signal of second multiplier all meets m frame signal phase cosine of an angle sv (m), the input signal of the 3rd multiplier all connects energy difference ener2 (m) of m frame signal and its corresponding inhibit signal, and the output signal of the 3rd multiplier is input to the 4th multiplier; The input signal of first adder connects the output signal of first multiplier and the output signal of second multiplier respectively; The input signal of first comparator connects the output signal of first adder and the output signal of the 4th multiplier respectively; The output signal of first comparator is input to first unit delay device and second comparator respectively; The output signal of first unit delay device is input to second unit delay device, the output signal of second unit delay device is input to the 3rd unit delay device, by that analogy, the output signal of (M/20-2) individual unit delay device is input to (M/20-1) individual unit delay device, the output signal of (M/20-1) individual unit delay device is input to second comparator, and the output of second comparator is phase overturn court verdict;

Described amplitude modulation coefficient detector (40) comprises present frame decimator (401) and amplitude modulation coefficient decision device (402), filtering signal u (n) is input to present frame decimator (401), the output of present frame decimator (401) is connected with amplitude modulation coefficient decision device (402), and whether the output of amplitude modulation coefficient decision device (402) exists result for adjudicating amplitude-modulated signal;

Described present frame decimator (401) comprises three unit delay devices and 22 adders, present frame filter result amplitude | u (m*20) | be input to first adder, present frame filter result amplitude | u (m*20+1) | be input to first adder, present frame filter result amplitude | u (m*20+2) | be input to second adder, present frame filter result amplitude | u (m*20+3) | be input to the 3rd adder, by that analogy, present frame filter result amplitude | u (m*20+19) | be input to nineteen adder, the output signal of nineteen adder is input to first unit delay device and the 20 adder respectively, the output signal of first unit delay device is input to second unit delay device and the 20 adder respectively, the output signal of second unit delay device is input to the 3rd unit delay device and the 21 adder, and the output signal of the 3rd unit delay device is input to the 22 adder, the output signal of the 20 adder is input to the 21 adder, the output signal of the 21 adder is input to the 22 adder, and the output of the 22 adder is minimum value min, maximum max in down-sampled rear each point amplitude and amplitude modulation coefficient am,

Described amplitude modulation coefficient decision device (402) comprises 3 comparators and 2 and gate; The input signal of first comparator meets minimum value min in down-sampled rear each point amplitude and threshold value THRES4 respectively, the input signal of second comparator meets amplitude modulation coefficient am and threshold value THRES5 respectively, and the input signal of the 3rd comparator meets amplitude modulation coefficient am and threshold value THRES6 respectively; First is connected first comparator and second comparator respectively with the input of gate, its output connects second and gate, the output of the 3rd comparator connects second and gate, and whether second exist result with the output of gate for adjudicating amplitude-modulated signal;

Described decision device (50) comprises one and gate, a multiplier and an adder; Be respectively 2100Hz detector (20) Output rusults and phase overturn detector (30) Output rusults with the input signal of gate, be input to multiplier with the output signal of gate; The input signal of adder is respectively output signal and amplitude modulation coefficient detector (40) Output rusults of multiplier, and the output of adder is the court verdict to input signal x (n).

2. to fax the detection method of checkout gear of ANSam signal, it is characterized in that: comprise the following steps:

A, filtering is carried out to input signal

The to be detected digital signal x (n) of SNR boostfiltering device (10) to input carries out filtering, and output filtering result u (n), namely

$u\left(n\right)=\underset{k=0}{\overset{9}{\mathrm{\&Sigma;}}}\mathrm{bpf}2100\left(k\right)\&CenterDot;x(n-k)---\left(1\right)$

Wherein, x (n-k) is the input signal in the n-th-k moment, and u (n) is the filter result in n moment, and bpf2100 (k) is a kth filter coefficient;

B, filter result to be adjudicated

Whether B1, detection filter result comprise 2100Hz signal

Whether 2100Hz detector (20) is for detecting digital signal x (n) to be detected containing 2100Hz component, the input signal of 2100Hz detector (20) is filter result u (n) of SNR boostfiltering device (10), the output of 2100Hz detector (20) is the result whether detection 2100Hz exists, if result is 0, represent there is not 2100Hz signal; If result is 1, then represent to there is 2100Hz signal;

Every 2.5 milliseconds of 2100Hz detector (20) detects once, and when input signal sample frequency is 8KHz, be equivalent to 20 sampled points, namely data frame length is 20; If present frame is m frame, then the data of present frame are u (m*20) ~ u (m*20+19); Cosine component d21_c (m), sinusoidal component d21_s (m) of present frame are respectively with the method for estimation of energy d21_e (m):

$d21\_c\left(m\right)=\underset{n=0}{\overset{19}{\mathrm{\&Sigma;}}}u(m*20+n)\cos \frac{2\mathrm{\&pi;}\&CenterDot;2100n}{8000}---\left(2\right)$

$d21\_s\left(m\right)=-\underset{n=0}{\overset{19}{\mathrm{\&Sigma;}}}u(m*20+n)\sin \frac{2\mathrm{\&pi;}\&CenterDot;2100n}{8000}---\left(3\right)$

$d21\_e\left(m\right)=\underset{n=0}{\overset{19}{\mathrm{\&Sigma;}}}{u}^2(m*20+n)---\left(4\right)$

Wherein, n=0,1 ..., 19;

The method of estimation of this cosine component re (m) detected, sinusoidal component im (m) and energy ener (m) is respectively:

re(m)＝d21_c[m]+d21_s[m-1]-d21_c[m-2]-d21_s[m-3] (5)

im(m)＝d21_s[m]-d21_c[m-1]-d21_s[m-2]+d21_c[m-3] (6)

ener(m)＝d21_e[m]+d21_e[m-1]+d21_e[m-2]+d21_e[m-3] (7)

Judge that the method whether 2100Hz signal exists is:

Work as re ²(m)+im ²(m) > THRES1ener (m), and during ener (m) > THRES2, be judged to 2100Hz signal and exist; Otherwise be judged to 2100Hz signal not exist; Here THRES1, THRES2 are decision threshold, are THRES1=20, THRES2=5242880 with reference to value;

B2, detection filter result whether phase overturn

The effect of phase overturn detector (30) detects input signal whether to have phase overturn, and can estimate phase overturn angle; The input signal of phase overturn detector (30) is the output signal u (n) of SNR boostfiltering device (10), the output of phase overturn detector (30) is the result whether phase place overturns, if result is 0, indicate without upset; If result is 1, then indicate upset;

First filter result u (n) phase shift 90 ° is obtained u ' (n); 90 ° of phase shifts are realized by Hilbert transformer (301), and its coefficient h (0) ~ h (18) value is as follows:

h(0)＝-0.070735530263065；h(10)＝0.636619772367581；

h(1)＝0；h(11)＝0；

h(2)＝-0.090945681766797；h(12)＝0.212206590789194；

h(3)＝0；h(13)＝0；

h(4)＝-0.127323954473516；h(14)＝0.127323954473516；

h(5)＝0；h(15)＝0；

h(6)＝-0.212206590789194；h(16)＝0.090945681766797；

h(7)＝0；h(17)＝0；

h(8)＝-0.636619772367581；h(18)＝0.070735530263065；

h(9)＝0；

Hilbert transform is:

$u^{\text{'}}\left(n\right)=\underset{k=0}{\overset{9}{\mathrm{\&Sigma;}}}h\left(2k\right)u(n-2k)---\left(8\right)$

Wherein, u ' (n) is the output of n moment phase shift 90 °, the input that u (n-2k) is the n-2k moment, and h (2k) is 2k Hilbert transformer coefficient;

Phase overturn detector (30) module remains every 2.5 milliseconds and detects once, data frame length is 20, the filter result data of m frame are u (m*20) ~ u (m*20+19), and after its phase shift 90 °, data are u ' (m*20) ~ u ' (m*20+19); For m frame filter result time delayed signal u (m*20-M) ~ u (m*20+19-M), M are time of delay (M is constant, and the present invention gets M=240); It is multiplied with data u ' (m*20) ~ u ' (m*20+19) after m frame filter result data u (m*20) ~ u (m*20+19), m frame filter result phase shift 90 ° respectively, respectively low-pass filtering is carried out to product signal, obtains det_c (m), the method for estimation of det_s (m) is:

$\det \_c\left(m\right)=\underset{n=0}{\overset{19}{\mathrm{\&Sigma;}}}u(m*20+n)\&CenterDot;u(m*20+n-M)---\left(9\right)$

$\det \_s\left(m\right)=\underset{n=0}{\overset{19}{\mathrm{\&Sigma;}}}{u}^{\&prime;}(m*20+n)\&CenterDot;u(m*20+n-M)---\left(10\right)$

M frame signal phase cosine of an angle cv, sinusoidal sv divide amount estimation method to be:

cv(m)＝cv(m-1)+det_c(m)-det_c(m-M/20) (11)

sv(m)＝sv(m-1)+det_s(m)-det_s(m-M/20) (12)

Energy difference ener2 (m) of m frame signal inhibit signal corresponding to it is:

$\mathrm{ener}2\left(m\right)=\mathrm{ener}2(m-1)+\underset{n=0}{\overset{19}{\mathrm{\&Sigma;}}}{\left[u(m*20+n)\right]}^2-u{(m*20+n-M-1)}^2]---\left(13\right)$

Detection method is: as (cv (m) ²+ sv (m) ²) > THRES3ener2 (m) ²time, with its phase angle of arctangent computation

Here THRES3 is decision threshold, and value of the present invention is THRES3=0.25;

If when the phase difference before and after upset meets formula (15), then judge that phase place has upset, now exporting is 1; Otherwise judge that phase place is without upset, now exporting is 0:

Whether B3, detection filter result be by amplitude modulation

The effect of amplitude modulation coefficient detector (40) whether detects input signal by amplitude modulation; By comparing the amplitude modulation coefficient that calculates whether within the scope of setting threshold, differentiate that whether input signal is by amplitude modulation; The input signal of amplitude modulation detector is output u (n) of SNR boostfiltering device (10), and its output is 1, then represent to there is amplitude-modulated signal; Output is 0, represents to there is not amplitude-modulated signal;

First to input signal down-sampled 80 times, method is to m frame filter result data u (m*20) ~ u (m*20+19), calculates its amplitude absolute value sum:

$\mathrm{sum}20\left(m\right)=\underset{n=0}{\overset{19}{\mathrm{\&Sigma;}}}\left|u(m*20+n)\right|---\left(16\right)$

Then, calculate the amplitude absolute value sum of continuous 4 frame data, the amplitude absolute value sum of described continuous 4 frame data is equivalent to 80 sampled points, is down-sampled rear each point amplitude:

sum80(m)＝sum20(m)+sum20(m-1)+sum20(m-2)+sum20(m-3) (17)

Use comparison search method, find out the maximum max in each point amplitude and minimum value min;

max＝maximum{sum80(m),sum80(m-1),…,sum80(m-26)} (18)

min＝minimum{sum80(m),sum80(m-1),…,sum80(m-26)} (19)

Then amplitude modulation coefficient am is:

$\mathrm{am}=\frac{\max -\min }{\max +\min }---\left(20\right)$

Work as min>THRES4, and during THRES5<am<THRES6, judge to there is 15Hz modulation, now exporting is 1; Otherwise output is 0; Wherein, THRES4, THRES5, THRES6 are decision threshold, are THRES4=20480, THRES5=0.08, THRES6=0.26 with reference to value;

C, judgement input signal x (n) are ANSam signals, or ANS signal

The Output rusults result formula calculating decision device (50) is

result＝(result1&result2)×2+result3 (21)

Wherein, " & " represents logical AND operation; Result1, result2 and result3 are respectively the Output rusults of 2100Hz detector (20), phase overturn detector (30) and amplitude modulation coefficient detector (40); The Output rusults result of decision device (50) is 0 or 1, represents input signal x (n) neither ANSam signal, neither ANS signal; Output rusults result is 2, and representing x (n) is ANS signal; Output rusults result is 3, and representing x (n) is ANSam signal.