CN103325773A - Packing structure for integrated circuit - Google Patents

Packing structure for integrated circuit Download PDF

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Publication number
CN103325773A
CN103325773A CN2012100784895A CN201210078489A CN103325773A CN 103325773 A CN103325773 A CN 103325773A CN 2012100784895 A CN2012100784895 A CN 2012100784895A CN 201210078489 A CN201210078489 A CN 201210078489A CN 103325773 A CN103325773 A CN 103325773A
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CN
China
Prior art keywords
chip unit
integrated circuit
chip
encapsulating structure
unit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN2012100784895A
Other languages
Chinese (zh)
Inventor
陈声寰
王曙民
韩肇伟
李威侬
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
MAXI-AMP Inc
Original Assignee
MAXI-AMP Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by MAXI-AMP Inc filed Critical MAXI-AMP Inc
Priority to CN2012100784895A priority Critical patent/CN103325773A/en
Publication of CN103325773A publication Critical patent/CN103325773A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Abstract

The invention relates to a packing structure for an integrated circuit. The packing structure comprises a first chip unit and a second chip unit tightly combined with the first chip unit. The second chip unit comprises at least one semiconductor layer and at least one metal layer, the second chip unit comprises a plurality of apertures penetrating through the semiconductor layer and the metal layer, and each aperture respectively penetrates through the second chip unit. In addition, the first chip unit is electrically connected with an output/input joint element. The packing structure for the integrated circuit can test the first chip unit through the output/input joint element and can directly cut the first chip unit into a plurality of grains without a general packing procedure. Thus, packing testing cost is effectively reduced, and the size of a packed chip can be reduced.

Description

The encapsulating structure of integrated circuit
Technical field
The present invention relates to a kind of encapsulating structure of integrated circuit, refer to especially a kind of with the encapsulating structure of a chip unit as the integrated circuit of substrate.
Background technology
The mode summary of a chip package is described below now: after upward the arrangement position of most crystal grain (Die) cuts according to a wafer (Wafer), each crystal grain is respectively installed on the corresponding lead frame (Lead frame) or a substrate (Substrate), so that most conductive feet positions (Pin) in the crystal grain are electrically connected with lead frame or substrate, receive one group of test voltage signal, to carry out chip testing.
In addition, crystal grain and substrate juncture are done further observation from encapsulation technology now, be broadly divided into routing maqting type (Wire bond, WB), automatic pressure welding type (Tape automatic bonding, TAB), flip chip type (Flip chip, FC) packaged type, if observe with the substrate connection pin type, be broadly divided into pin insert type (Pin-through-hole, PTH), surface adhesion type (Surface mount technology, SMT), peripheral type (Peripheral package) and digit group type (Array area) etc., yet, along with electronic product continues towards gently, thin, short, little trend evolution, the technology of chip package also becomes take flip chip type as main from early stage routing maqting type gradually, and the substrate connection pin type is also become take digit group type as main (as: tin ball lattice array encapsulation (Ball Grid Array, BGA) by the pin insert type.
For instance, one covers brilliant tin ball lattice array encapsulation (FC BGA) as shown in Figure 1, a crystal grain 910 utilizes most tin balls 991 and a substrate 920 to link, described tin ball 991 effectively is electrically connected with the substrate pin 992 of leypewter material simultaneously, and Fig. 2 shows that a routing engages tin ball lattice array encapsulation (Wire bond BGA), and wherein crystal grain 810 is to link with metal wire 892 and substrate 820.
From the said chip encapsulation technology, whichever all must and all must link with tin ball or the mode of metal wire between crystal grain and the substrate with the device of a substrate (or a lead frame) as carrying crystal grain, is one of main way of current chip encapsulation technology.
Summary of the invention
In view of this, the object of the present invention is to provide a kind of encapsulating structure of integrated circuit.
For achieving the above object, the invention provides a kind of encapsulating structure of integrated circuit, the encapsulating structure of described integrated circuit comprises:
One first chip unit; And
One second chip unit, itself and described the first chip unit are electrically connected, and described the second chip unit has at least one semiconductor layer and at least one metal level, and the second chip unit has most the apertures of running through described semiconductor layer and metal level; Wherein, the second chip unit is run through respectively in each aperture, and the first chip unit and an output input joint element electric connection.
As preferred version, wherein said the second chip unit also has a jointing metal layer, and according to semiconductor technology described jointing metal layer is produced most output input joint elements.
As preferred version, the encapsulating structure of wherein said integrated circuit also comprises a knitting layer unit, and according to semiconductor technology most output input joint elements is produced in described knitting layer unit.
As preferred version, wherein said the first chip unit, the second chip unit and knitting layer unit package become an integrated circuit module.
As preferred version, the area of wherein said the second chip unit is greater than the area of the first chip unit.
As preferred version, the area of wherein said the second chip unit equals the area of the first chip unit.
As preferred version, wherein said the first chip unit and the second chip unit are packaged into an integrated circuit module.
As preferred version, the material of wherein said semiconductor layer is silicon.
As preferred version, the material of wherein said semiconductor layer is GaAs.
The encapsulating structure of integrated circuit provided by the present invention, via this output input joint element this first chip unit is tested, and need not can directly this first chip unit be cut into most crystal grain through general canned program, therefore, can effectively reduce packaging and testing cost and the size of reduction behind the chip package.
Description of drawings
Fig. 1 is a schematic side view of covering the encapsulation of brilliant tin ball lattice array in the prior art;
Fig. 2 is the schematic side view that a routing engages the encapsulation of tin ball lattice array in the prior art;
Fig. 3 is the schematic side view of the first preferred embodiment among the present invention;
Fig. 4 is the schematic side view of the first preferred embodiment after semiconductor technology obtains majority circuit element and output input joint element among the present invention;
Fig. 5 is the schematic top plan view of the first preferred embodiment after semiconductor technology obtains majority circuit element and output input joint element among the present invention;
Fig. 6 is the schematic side view of the second preferred embodiment among the present invention;
Fig. 7 is the schematic top plan view of the 3rd preferred embodiment among the present invention.
[main element symbol description]
Wafer-10; The first chip unit-11; Conductive feet position-110; Semiconductor layer-111; Metal level-112; The second chip unit-12; Aperture-121; Knitting layer unit-13; Output input joint element-131;
Crystal grain-810; Substrate-820; Metal wire-892;
Crystal grain-910; Substrate-920; Tin ball-991; Substrate pin-992;
Circuit element-CKT1 ~ CKTn;
Crystal grain-D1 ~ Dm.
Embodiment
About feature of the present invention and technology contents, below cooperate three preferred embodiments with reference to the accompanying drawings to be described in detail as follows.
Because the present invention has most preferred embodiments, therefore before describing in detail, the similar element in following preferred embodiment is to represent with identical numbering.
1. the first preferred embodiment of the encapsulating structure of integrated circuit
Consult Fig. 3, a preferred embodiment of the present invention comprises: first chip unit 11, second chip unit 12 and a knitting layer unit 13.The first chip unit 11, the second chip unit 12 comprise respectively at least one semiconductor layer 111 and at least one metal level 112, and the material of semiconductor layer 111 is semiconductor material (as: silicon (Si), GaAs (GaAs) etc.), and knitting layer unit 13 is metal levels.
What deserves to be explained is, the first chip unit 11, the second chip unit 12, knitting layer unit 13 sequentially engage between between the first chip unit 11 and the knitting layer unit 13 with the second chip unit 12, and the area of the second chip unit 12 is more than or equal to the area of the first chip unit 11, in addition, because knitting layer unit 13 is a metal level, therefore also can utilize the bottom in the second chip unit 12 to implement according to this.
The first chip unit 11, the second chip unit 12 are the modes (as: exposure, oxide deposition, etching, development etc.) with semiconductor technology, make associated circuit components in wherein, because a circuit element production method of using semiconductor technology is not principal character of the present invention, please consider the explanation of related content in " Principles of CMOS VLSI Design " book that the people such as Neil H. E. Weste and Kamran Eshraghian show in light of actual conditions, no longer add to give unnecessary details at this.
Then, most apertures 121 are set in the second chip unit 12, wherein, the second chip unit 12 is run through respectively in each aperture 121.
At last, in knitting layer unit 13, utilize the mode of semiconductor technology to make most output input joint element 131(I/O Pad).
Unite and consult Fig. 4,5, suppose to have in the first chip unit 11 n circuit element CKT1 ~ CKTn that produces with semiconductor technology, and each circuit element CKT1 ~ CKTn has respectively its corresponding conductive feet position 110, each conductive feet 110 is electrically connected on the output input joint element 131 of a correspondence via the aperture 121 of a correspondence respectively, so that each circuit element CKT1 ~ CKTn is able to via one group of reference voltage (not shown) of reception on the output input joint element 131 of its correspondence.
After the circuit element in the first chip unit 11 receives this group reference voltage and finishes test, can be via the wafer cutting mode, obtain each the circuit element CKT1 ~ CKTn in the first chip unit 11, since described circuit element CKT1 ~ CKTn with the second chip unit 12 as the support, and can be by corresponding output input joint element 131, to transmit or to receive signal, therefore, do not need through such as conventional package flow processing such as routing, fillers, so can reduce the production cost of this circuit element.
2. the second preferred embodiment of the encapsulating structure of integrated circuit
Consult Fig. 6, the difference of the second preferred embodiment and the first preferred embodiment maximum is: when the orlop of the second chip unit 12 is a metal level, this metal level namely can be considered knitting layer unit 13, and make most outputs at this metal level and input joint elements, that is to say, knitting layer unit 13 and the second chip 12 also can integrated mode be made, and are not limited in the first preferred embodiment the mode of making respectively and implement.
3. the 3rd preferred embodiment of the encapsulating structure of integrated circuit
Consult Fig. 7, because the first chip unit 11 that comprises described circuit element CKT1 ~ CKTn does not need such as being arranged at respectively on a lead frame or the substrate as the prior art, therefore, in this preferred embodiment, that majority first chip unit 1 is arranged at a wafer 10(Wafer simultaneously) in, and cooperate the second chip unit 12 of a correspondence, via the aperture of the second chip unit 12 the knitting layer unit 13 that the conductive feet position (Pin) and of each the first chip unit 1 has most output input joint elements 131 are electrically connected, so, if in the time of need to encapsulating, each first chip unit 11 and corresponding the second chip unit 12, and knitting layer unit 13 can directly encapsulate jointly, then after the program via the wafer cutting, can obtain most the crystal grain D1 ~ Dm that have respectively described circuit element CKT1 ~ CKTn, in other words, this preferred embodiment can effectively reduce the area that each has the crystal grain of described circuit element CKT1 ~ CKTn.
The difference of the present invention and prior art maximum is, the present invention is with after this first chip unit and the applying of this second chip unit, this first chip unit is able to receive one group of reference voltage to test via the aperture in these the second chip units, therefore, be not as prior art, after wafer cut into most crystal grain, again crystal grain is placed on lead frame or the substrate to carry out packaging and testing, therefore, compared to existing technologies, the present invention integrates this first chip unit, the second chip unit, the knitting layer unit is in this integrated circuit, can test this first and second chip unit and use via this output input joint element, and need not pass through general canned program and (as: surface adhesion type (SMT) pin is set, or carry out chip package with routing maqting type (WB)), can directly this first chip unit be cut into most crystal grain, therefore, compared to existing technologies, size after can effectively reducing the packaging and testing cost and reducing chip package is therefore really can reach purpose of the present invention.
The above is preferred embodiment of the present invention only, is not to limit claim of the present invention in order to this, and the equivalence of such as doing according to patent spirit of the present invention changes and modifies etc., all in like manner belongs in the scope of patent protection of the present invention.

Claims (9)

1. the encapsulating structure of an integrated circuit is characterized in that, the encapsulating structure of described integrated circuit comprises:
One first chip unit; And
One second chip unit, itself and described the first chip unit are electrically connected, and described the second chip unit has at least one semiconductor layer and at least one metal level, and the second chip unit has most the apertures of running through described semiconductor layer and metal level; Wherein, the second chip unit is run through respectively in each aperture, and the first chip unit and an output input joint element electric connection.
2. the encapsulating structure of integrated circuit as claimed in claim 1 is characterized in that, described the second chip unit also has a jointing metal layer, and according to semiconductor technology described jointing metal layer is produced most output input joint elements.
3. the encapsulating structure of integrated circuit as claimed in claim 1 is characterized in that, the encapsulating structure of described integrated circuit also comprises a knitting layer unit, and according to semiconductor technology most output input joint elements is produced in described knitting layer unit.
4. the encapsulating structure of integrated circuit as claimed in claim 3 is characterized in that, described the first chip unit, the second chip unit and knitting layer unit package become an integrated circuit module.
5. the encapsulating structure of integrated circuit as claimed in claim 1 is characterized in that, the area of described the second chip unit is greater than the area of the first chip unit.
6. the encapsulating structure of integrated circuit as claimed in claim 1 is characterized in that, the area of described the second chip unit equals the area of the first chip unit.
7. the encapsulating structure of integrated circuit as claimed in claim 1 is characterized in that, described the first chip unit and the second chip unit are packaged into an integrated circuit module.
8. the encapsulating structure of integrated circuit as claimed in claim 1 is characterized in that, the material of described semiconductor layer is silicon.
9. the encapsulating structure of integrated circuit as claimed in claim 1 is characterized in that, the material of described semiconductor layer is GaAs.
CN2012100784895A 2012-03-22 2012-03-22 Packing structure for integrated circuit Pending CN103325773A (en)

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Application Number Priority Date Filing Date Title
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5490040A (en) * 1993-12-22 1996-02-06 International Business Machines Corporation Surface mount chip package having an array of solder ball contacts arranged in a circle and conductive pin contacts arranged outside the circular array
WO2000001208A1 (en) * 1998-06-30 2000-01-06 Formfactor, Inc. Assembly of an electronic component with spring packaging
US6379982B1 (en) * 2000-08-17 2002-04-30 Micron Technology, Inc. Wafer on wafer packaging and method of fabrication for full-wafer burn-in and testing
US20060065976A1 (en) * 2004-09-24 2006-03-30 Min-Chih Hsuan Method for manufacturing wafer level chip scale package structure
US20060228825A1 (en) * 2005-04-08 2006-10-12 Micron Technology, Inc. Method and system for fabricating semiconductor components with through wire interconnects

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5490040A (en) * 1993-12-22 1996-02-06 International Business Machines Corporation Surface mount chip package having an array of solder ball contacts arranged in a circle and conductive pin contacts arranged outside the circular array
WO2000001208A1 (en) * 1998-06-30 2000-01-06 Formfactor, Inc. Assembly of an electronic component with spring packaging
US6379982B1 (en) * 2000-08-17 2002-04-30 Micron Technology, Inc. Wafer on wafer packaging and method of fabrication for full-wafer burn-in and testing
US20060065976A1 (en) * 2004-09-24 2006-03-30 Min-Chih Hsuan Method for manufacturing wafer level chip scale package structure
US20060228825A1 (en) * 2005-04-08 2006-10-12 Micron Technology, Inc. Method and system for fabricating semiconductor components with through wire interconnects

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Application publication date: 20130925