CN103339725A - 晶圆内的柔性互连 - Google Patents

晶圆内的柔性互连 Download PDF

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Publication number
CN103339725A
CN103339725A CN2011800669890A CN201180066989A CN103339725A CN 103339725 A CN103339725 A CN 103339725A CN 2011800669890 A CN2011800669890 A CN 2011800669890A CN 201180066989 A CN201180066989 A CN 201180066989A CN 103339725 A CN103339725 A CN 103339725A
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substrate
microelectronic unit
conducting element
bonding part
type surface
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CN103339725B (zh
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瓦格·奥甘赛安
贝勒卡西姆·哈巴
伊利亚斯·默罕默德
皮尤什·萨瓦利亚
克雷格·米切尔
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Adeia Semiconductor Solutions LLC
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Tessera LLC
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15788—Glasses, e.g. amorphous oxides, nitrides or fluorides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress

Abstract

微电子单元(12)包括基板(20)和导电元件(40)。基板(20)可具有小于10ppm/℃的热膨胀系数，主表面(21)具有未贯穿基板而延伸的凹陷(30)，弹性模量小于10GPa的材料(50)沉积在凹陷内。导电元件(40)可包括覆盖凹陷(30)并从被基板(20)支撑的锚部分(41)延伸的接合部分(42)。接合部分(42)可至少部分地在主表面(21)暴露，用于与微电子单元(12)外部的元器件(14)连接。

Description

晶圆内的柔性互连
相关申请的交叉引用
本申请为申请号为12/962806、申请日为2010年12月8日的美国专利申请的继续申请，其公开的内容以引用的方式并入本文。
背景技术
本发明涉及堆叠的微电子组件与制作这种组件的方法，及在这种组件中应用的元器件。
半导体芯片通常设置为单独的、预封装的单元。标准芯片具有扁平的、矩形的主体，其正面具有与芯片有源电路连接的触点。每个单独芯片通常都安装在封装内，而封装再安装在如印刷电路板等的电路板上，并使芯片触点与电路板的导电体连接。在许多常规设计中，芯片封装占据电路板的面积远大于上芯片自身的面积。本文参照具有正面的扁平芯片而应用，“芯片面积”应当理解为指的是正面的面积。
在“倒装芯片”设计中，芯片的正面面对封装基板、即芯片载体的表面，芯片上的触点通过焊料球或其他连接元件与芯片载体的触点直接结合。而芯片载体可通过覆盖芯片正面的端子再与电路板结合。“倒装芯片”设计提供了相对紧凑的布置，每个芯片占据电路板的面积等于或稍大于芯片正面的面积，如在共同转让的专利号分别为5148265、5148266、5679977的美国专利的某些实施例中所公开的，这些专利公开的内容以引用的方式并入本文。
除了使微电子组件所占据电路板的平面面积最小化以外，制造出垂直于电路板平面的总体高度或尺寸小的芯片封装，也是可取的。这种薄的微电子封装允许，其内安装有此封装的电路板放置为与邻近结构相当接近，从而缩减包含此电路板的产品的总体尺寸。
还提出了把复数个芯片封装至“堆叠”布置中，即，复数个芯片以一个在另一个之上的方式放置的布置。在堆叠布置中，数个芯片可安装在小于各芯片面积总和的电路板区域内。例如上述的专利号为5148265、5679977的美国专利、及专利号为5347159的美国专利的某些实施例中已公开了一些堆叠芯片布置，其公开的内容以引用的方式并入本文。同样以引用方式并入本文的专利号为4941033的美国专利中，公开了一种布置，其中芯片以一个在另一个之上的方式堆叠，并通过与芯片相关联的称为“布线膜（wiring films）”上的导电体而彼此互连。
由于触点处不理想的应力分布、及如半导体芯片与芯片将结合的结构之间热膨胀系数（CTE）的不匹配，常规芯片触点可能会面临可靠性方面的挑战。例如，当半导体芯片表面上的导电触点通过相对薄且为刚性的介电材料而绝缘时，触点处可能存在相当大的应力。另外，当半导体芯片与聚合物基板的导电元件结合时，芯片与基板较高热膨胀系数（CTE）的结构之间的电连接，将由于热膨胀系数（CTE）的不匹配而处于应力下。
在芯片的任一几何布置中，尺寸是重要的考虑因素。随着便携式电子装置的快速发展，芯片的更紧凑几何布置的需求变得更为强烈。仅以示例的方式说明，通常称为“智能手机”的装置，集成了移动电话及强大的数据处理器、存储器、如全球定位系统接收器、数码相机等的辅助器件等的功能，以及局域网连接，并伴有高分辨率的显示及相关的图像处理芯片。这种装置可提供如完整的互联网连接、包括高清视频等的娱乐、导航、电子银行及更多的功能，都设置在袖珍式的装置内。复杂的便携装置要求把大量芯片包装至狭小的空间内。此外，一些芯片具有许多输入和输出接口，一般称为“I/O口”。这些I/O口必须与其他芯片的I/O口互连。这种互连应尽量短且应具有低的阻抗，以使信号传输延迟最小化。形成这些互连的元器件应不大幅度增加组件的尺寸。类似需求也出现在其他应用中，例如，数据服务器，如在互联网搜索引擎中使用的数据服务器。例如，在复杂芯片之间设置大量短且阻抗低的互连的结构，可增加搜索引擎的频带宽度（bandwidth），并降低其能耗。
尽管在半导体通路的形成和互连方面已取得进展，但为最小化半导体芯片的尺寸，同时加强电互连的可靠性，仍需做出进一步的改进。本发明的这些特性可通过下文所述的微电子封装的结构而获得。
发明内容
根据本发明的方面，微电子单元可包括基板和导电元件。基板可具有小于10ppm/℃的热膨胀系数，主表面具有未贯穿基板而延伸的凹陷，弹性模量小于10GPa的材料设置在凹陷内。导电元件可包括覆盖凹陷、并从被基板支撑的锚部分延伸的接合部分。接合部分可至少部分地在主表面暴露，用于与微电子单元外部的元器件连接。
在一个实施例中，基板可具有小于7 ppm/℃的热膨胀系数。在特定实施例中，接合部分可为可移动的，从而降低如在微电子单元工作、制造或检测过程中可能存在于接合部分的应力。在示例性的实施例中，基板可基本上从由半导体、玻璃和陶瓷组成的群组中选择的一种材料组成。在一个实施例中，基板可包括复数个有源半导体器件，且导电元件可与复数个有源半导体器件中至少一个电连接。在特定实施例中，设置在凹陷内的材料可包括从由聚酰亚胺、硅树脂和环氧树脂组成的群组中选择的至少一种材料组成。
在示例性的实施例中，凹陷可未贯穿基板而延伸。在一个实施例中，接合部分可沿大致平行于基板主表面的方向延伸。在特定实施例中，锚部分和接合部分可沿相同方向延伸。在示例性的实施例中，导电元件可与导电通路电耦合，导电通路朝与主表面相对的基板第二表面延伸。在一个实施例中，导电通路可在第二表面暴露。在特定实施例中，导电通路可在基板的孔内延伸，孔从第二表面延伸至主表面。
在一个实施例中，孔可包括从主表面朝着第二表面延伸的第一开口和从第一开口延伸至第二表面的第二开口。第一开口的内表面和第二开口的内表面可相对于主表面分别沿第一方向和第二方向延伸，以限定明显的角度。在示例性的实施例中，堆叠组件可至少包括第一微电子单元和第二微电子单元，第二微电子单元与第一微电子单元堆叠，第一微电子单元的基板与第二微电子单元的基板电连接。在特定实施例中，堆叠组件可进一步包括与第一微电子单元的接合部分及第二微电子单元的导电元件电耦合的导电块。
根据本发明另一方面，微电子组件可包括基板和导电元件。基板可具有小于10ppm/℃的热膨胀系数，主表面具有未贯穿基板而延伸的凹陷，弹性模量小于10GPa的材料设置在凹陷内。导电元件可具有相对基板固定的锚部分、至少部分地覆盖凹陷的接合部分、及从接合部分向下延伸至锚部分的连接部分。接合部分可沿远离锚部分的方向延伸，且可在主表面暴露，用于与微电子单元外部的元器件连接。连接部分可具有与凹陷内表面的轮廓不一致的轮廓。
在示例性的实施例中，基板可具有小于7ppm/℃的热膨胀系数。在一个实施例中，接合部分可为可移动的，从而降低如在微电子单元工作、制造或检测过程中可能存在于接合部分的应力。在特定实施例中，基板可基本上从由半导体、玻璃和陶瓷组成的群组中选择的一种材料组成。在一个实施例中，基板可包括复数个有源半导体器件，导电元件可与复数个有源半导体器件中至少一个电连接。在示例性的实施例中，连接部分可延伸至凹陷内。
在特定实施例中，导电元件可与导电通路电耦合，导电通路朝与主表面相对的基板第二表面延伸。在一个实施例中，导电通路可在第二表面暴露。在示例性的实施例中，导电通路可在基板的孔内延伸，孔从第二表面延伸至主表面。在特定实施例中，孔可包括从主表面朝着第二表面延伸的第一开口和从第一开口延伸至第二表面的第二开口。第一开口的内表面和第二开口的内表面可相对于主表面分别沿第一方向和第二方向延伸，以限定明显的角度。在一个实施例中，锚部分可具有与孔内表面的轮廓一致的轮廓。在示例性的实施例中，接合部分可限定内部孔隙。
在一个实施例中，孔隙可穿过接合部分延伸至连接部分内。在特定实施例中，孔隙的至少一部分可用介电材料填充。在示例性的实施例中，堆叠组件可至少包括第一微电子单元和第二微电子单元，第二微电子单元与第一微电子单元堆叠，且第一微电子单元的基板与第二微电子单元的基板电连接。在特定实施例中，堆叠组件可进一步包括与第一微电子单元的接合部分及第二微电子单元的导电元件电耦合的导电块。
根据本发明又一实施例，制造微电子单元的方法可包括：形成支撑在基板主表面上的导电元件的步骤，基板具有小于10ppm/℃的热膨胀系数；从主表面除去至少支撑导电元件接合部分的材料的步骤，以形成未贯穿基板而延伸的凹陷；在凹陷内沉积弹性模量小于10GPa的材料的步骤。接合部分可不被基板支撑，而导电元件邻接接合部分的锚部分可被基板支撑。接合部分可至少部分地在基板主表面暴露，用于与微电子单元外部的元器件连接。
在一个实施例中，基板可具有小于7ppm/℃的热膨胀系数。在示例性的实施例中，基板可基本上从由半导体、玻璃和陶瓷组成的群组中选择的一种材料组成。在特定实施例中，基板可包括复数个有源半导体器件，而在形成导电元件的步骤中，可使导电元件与复数个有源半导体器件中至少一个电连接。在示例性的实施例中，可进行形成导电元件的步骤，使得接合部分设置为大致平行于主表面。在一个实施例中，该方法可进一步包括：从基板上去除材料以形成孔的步骤，孔从主表面延伸至与主表面相对的基板第二表面，及形成在孔内延伸的导电通路的步骤，使得导电通路与导电元件电耦合，并朝第二表面延伸。
在特定实施例中，从基板上去除材料以形成孔的步骤可包括，形成从主表面朝第二表面延伸的第一开口、及从第一开口延伸至第二表面的第二开口。第一开口的内表面和第二开口的内表面可相对于主表面分别沿第一方向和第二方向延伸，以限定明显的角度。在一个实施例中，制造至少包括第一微电子单元和第二微电子单元的堆叠组件的方法可进一步包括，使第一微电子单元的基板与第二微电子单元的基板电连接的步骤。
根据本发明又一实施例，制造微电子单元的方法可包括：从基板上去除材料以形成孔的步骤，基板具有小于10ppm/℃的热膨胀系数，孔从基板的主表面延伸至与主表面相对的基板第二表面；形成导电元件的步骤，导电元件具有在主表面上延伸并由主表面支撑的接合部分、与基板相对固定的锚部分、及从接合部分向下延伸至锚部分的连接部分；从主表面除去至少支撑导电元件接合部分的材料以形成凹陷的步骤，使得接合部分至少部分地覆盖凹陷；及在凹陷内沉积弹性模量小于10GPa的材料的步骤。连接部分的表面具有与孔内表面的轮廓一致的轮廓。连接部分表面的轮廓可与凹陷内表面的轮廓不一致。接合部分可至少部分地在基板主表面暴露，用于与微电子单元外部的元器件连接。
在特定实施例中，基板可具有小于7 ppm/℃的热膨胀系数。在示例性的实施例中，制造微电子单元的方法可进一步包括，在形成导电元件的步骤之前，形成在孔内延伸、并朝第二表面延伸的导电通路的步骤，使得在形成导电元件的步骤中使导电元件与导电通路电耦合。在一个实施例中，可进行形成导电元件的步骤，使得接合部分的中心不在连接部分。在特定实施例中，基板可基本上从由半导体、玻璃和陶瓷组成的群组中选择的一种材料组成。在示例性的实施例中，基板可包括复数个有源半导体器件，在形成导电元件的步骤中，可使导电元件与复数个有源半导体器件中至少一个电连接。在一个实施例中，可进行形成导电元件的步骤，使得接合部分限定内部孔隙。在特定实施例中，可进行形成导电元件的步骤，使得孔隙穿过接合部分延伸至连接部分内。
在一个实施例中，微电子单元的制造方法可进一步包括，在孔隙的至少一部分内沉积介电材料的步骤。在特定实施例中，从基板上去除材料以形成孔的步骤可包括，形成从主表面朝着第二表面延伸的第一开口及从第一开口延伸至第二表面的第二开口。第一开口的内表面和第二开口的内表面可相对于主表面分别沿第一方向和第二方向延伸，以限定明显的角度。在示例性的实施例中，制造至少包括第一微电子单元和第二微电子单元的堆叠组件的方法可进一步包括，使第一微电子单元的基板与第二微电子单元的基板电连接的步骤。
本发明进一步的方面提供了系统，包含根据本发明之前方面的微电子结构、根据本发明之前方面的集成芯片、或二者，与其他电子器件的结合。例如，系统可设置在单个外壳内，外壳可为便携式外壳。根据本发明这个方面优选实施例的系统，与同类常规系统相比可更紧凑。
本发明的进一步的方面提供了可包括复数个根据本发明上述方面微电子组件的模块。每个模块可具有共用的电气接口，用于向或从每个所述微电子组件传输信号。
附图说明
图1A是说明根据本发明实施例具有触点结构的堆叠组件的侧剖视图。
图1B是图3A中堆叠组件沿线A-A剖切时相应的自下而上的截面图的一个实施例。
图1B是图3A中堆叠组件沿线A-A剖切时相应的自下而上的截面图的另一实施例。
图1B是图3A中堆叠组件沿线A-A剖切时相应的自下而上的截面图的又一实施例。
图2A至图2D是说明根据图1A所绘出的本发明实施例制造阶段的截面图。
图3A是根据本发明实施例具有触点结构的堆叠组件的侧剖视图。
图3B是图1A中堆叠组件沿线B-B剖切时相应的自下向上的截面图的一个实施例。
图3C是图1A中堆叠组件沿线B-B剖切时相应的自下向上的截面图的另一实施例。
图3D是图1A中堆叠组件沿线B-B剖切时相应的自下向上的截面图的又一实施例。
图4A至图4E是说明根据图3A所绘出的本发明实施例的制造阶段的截面图。
图5是根据本发明具有与芯片电连接的垫的基板的俯视立体图。
图6是说明根据本发明另一实施例具有触点结构的基板的侧剖视图。
图7是根据本发明一个实施例的模块的示意图。
图8是根据本发明一个实施例的系统的示意图。
具体实施方式
参照图1A，根据本发明实施例的堆叠微电子组件10包括第一微电子单元12和第二微电子单元14。在一些实施例中，第一微电子单元12和第二微电子单元14可为半导体芯片、晶圆、介电基板、或类似物。例如，第一微电子单元12和第二微电子单元14中一个或二者可包括记忆存储元件。在本文中应用的“记忆存储元件”，指的是布置成阵列的大量的伴有电路的存储单元，可用于存储和提取数据，如用于通过电气接口传输数据。
第一微电子单元12包括具有凹陷30的基板20，凹陷从主表面21部分地穿过基板朝与主表面相对的第二表面22延伸，导电元件40具有由基板支撑的锚部分41、从锚部分延伸的接合部分42、及端头部分46，接合部分42至少部分地覆盖凹陷30且至少部分地在主表面暴露，用于与第一微电子单元外部的元器件互连。如图所示，端头部分46位于接合部分42的端部。至少在凹陷30内，介电区域50覆盖内表面31。
在图1A中，与主表面21平行的方向本文称为“水平”或“横向”的方向；而垂直于正面的方向本文称为向上或向下的方向，且本文中还称为“竖直”方向。本文所指的方向参考结构的参照系。因此，对于通常或重力参照系，这些方向可位于任意方向。声明一个特征与另一特征相比，位于“表面上方”较高的高度，意味着这两个特征都以同一正交方向偏离该表面，但沿该正交方向该一个特征比该另一个特征距该表面的距离更远。相反地，声明一个特征与另一个特征相比，位于“表面上方”较低高度，意味着这两个特征都以同一正交方向偏离该表面，但沿该正交方向该一个特征比该另一个特征距该表面的距离更近。
基板20优选地具有小于10×10-6/℃（或ppm/℃）的热膨胀系数（“CTE”）。在特定实施例中，基板20可具有小于7×10-6/℃或ppm/℃）的热膨胀系数（“CTE”）。基板20优选地基本上由如半导体、玻璃或陶瓷等材料组成。在基板20由如硅等半导体制成的实施例中，复数个有源半导体器件（如晶体管、二极管等）可设置在位于主表面21或第二表面22上和/或下方的有源半导体区域内。主表面21与第二表面22之间的基板20厚度典型地小于200微米，且可显著地更小，例如130微米、70微米或甚至更小。
基板20可进一步包括，设置在主表面21与至少一个导电元件40之间的介电层。介电层可覆盖第二表面22。这种介电层可使导电元件与基板20电绝缘。这些介电层中的一个或二者可称为第一微电子单元12的“钝化层”。介电层可包括无机介电材料、或有机介电材料、或二者。介电层可包括电沉积的保形涂层或其他介电材料，例如，光成像(photoimageable)聚合物材料，例如，焊料掩模材料。
微电子元件12可包括在基板20主表面21暴露的一个或多个导电元件40。每个导电元件40的接合部分42都可在主表面21暴露，用于与第一微电子元件12外部的元器件，如第二微电子元件14互连。尽管在图中没有特别地示出，基板20内的有源半导体器件可与接合部分42电连接。因此，通过并入基板20的在一个或多个介电层内或介电层上延伸的布线，有源半导体器件可导电接通。导电元件40（及本文描述的任意其他导电元件）可由任意导电金属，例如包括，铜或金制成。
例如，如图1C所示，接合部分42′可具有导电结合垫如薄平件的仰视形状。每个接合部分42可具有任意仰视形状，例如包括，如图1B所示的矩形迹线形状，如图1C所示的圆形垫的形状，椭圆形、方形、三角形或更复杂的形状。在其他实施例中，接合部分42可为任意其他类型的导电触点，例如包括，导电柱。
接合部分42可与凹陷30对齐，且可完全或部分地位于凹陷所限定的基板20区域内。从图1A可以看出，接合部分42完全位于凹陷30所限定的区域内。如图所示，接合部分42的顶面43所限定的平面与基板20的主表面21所限定的平面大致平行。如图所示，接合部分42的底面44位于基板20的主表面21所限定的平面内。在其他实施例中，接合部分42的底面44可位于主表面21所限定的平面的上方或下方。导电元件40的端头部分46不被基板20支撑，从而相对于锚部分41，端头部分可为悬臂。接合部分42的这种覆盖主表面、且位于介电区域50邻近的不被支撑的端头部分46，可相对于被支撑的锚部分41自由移动，使得接合部分42可作为悬臂。
在本文应用的，声明导电元件“暴露在”基板或覆盖基板表面的介电元件的表面，指的是导电元件可与一理论点接触，该理论点以垂直于该介电元件表面的方向从介电元件外部向该介电元件表面移动。因此，暴露在介电元件表面上的端子或其他导电元件可从该表面突出；可与该表面平齐；或可相对于该表面凹陷，并通过介电元件上的孔或凹坑暴露。
因为基本上任意可用于形成导电元件的技术都可用于形成本文描述的导电元件，可采用共同拥有的申请号为12/842669、申请日为2010年7月23日的美国专利申请中非常详细地描述的特定技术，其公开的内容以引用的方式并入本文。例如，这些技术可包括，应用激光或应用如研磨或喷砂等的机械加工工艺，选择性地处理表面，使得沿将要形成导电元件的路线的该部分表面，处理为与表面的其他部分不同。例如，可应用激光或机械加工工艺，从表面只沿特定路线烧蚀或去除如牺牲层等的材料，因此形成沿该路线延伸的凹槽。然后可在凹槽内沉积如催化剂等的材料，并可在凹槽内沉积一种或多种金属层。
图中所示的导电元件40的端头部分46，没有超出凹陷30的外边界32（图1B）而横向（即沿平行于基板20主表面21的方向）延伸。在本文公开的任意实施例中，导电元件和/或接合部分的端部可超出凹陷的外边界而延伸。在一个实施例中，接合部分的端部可与导电迹线（未示出）耦合，导电迹线超出相应凹陷的外边界而延伸，但相对于相应基板，接合部分可仍是可移动的，以下文所描述的方式。
凹陷30从主表面21部分地穿过基板20朝第二表面22延伸。凹陷30的内表面31可从主表面21以任意角度穿过基板20而延伸。优选地，内表面31从主表面21相对于由主表面21所限定的水平面以0度至90度之间的角度延伸。内表面31可具有恒定的斜度或变化的斜度。例如，当内表面31进一步朝第二表面22伸入时，内表面31相对于由主表面21所限定的水平面的角度或斜度的绝对值可减小（即正、负幅度减小）。
凹陷30可具有任意的仰视形状，例如包括，如图1B所示的椭圆形、或图1C所示的圆形。在图1B所示的实施例中，沿主表面21的第一横向，凹陷30具有宽度W，沿主表面的垂直于第一横向的第二横向，凹陷具有长度L，长度大于宽度。在一些示例中，凹陷40可具有任意三维形状，例如包括，圆柱体、立方体、棱柱、或截头圆锥的形状，及其他。
在特定实施例中，凹陷30可为矩形通道，复数个接合部分42至少部分地覆盖凹陷，如图1D所示。任意数量的接合部分42可覆盖单个凹陷30，接合部分可布置为以任意的几何布局覆盖单个凹陷。例如，三个接合部分42可布置为沿共同轴线覆盖单个凹陷30，如图1D所示。
在所示的实施例中，介电区域50填充凹陷30，使得介电区域的轮廓与凹陷的轮廓（即凹陷内表面31的形状）一致。介电区域50可对于基板20提供良好的介电隔离。介电区域50可为柔性的，具有足够低的弹性模量和足够的厚度，使得模量和厚度的乘积能提供柔性。优选地，导电元件40的接合部分42至少部分地覆盖介电区域50。当外部负载施加至接合部分时，柔性介电区域50可允许导电元件40的接合部分42相对于基板20及被基板支撑的导电元件的锚部分41弯曲或稍微移动。以这种方式，第一微电子单元12的接合部分42与第二微电子单元14的端子之间的结合，可更好地承受由于第一微电子单元与第二微电子单元之间热膨胀系数（“CTE”）的不匹配而引起的热应变。
本文与导电元件的接合部分相关联而应用的，“可移动”应当指的是，通过施加的外部负载，接合部分能相对于基板的主表面移置，达到这种移置明显地释放或降低机械应力的程度，例如在微电子单元工作、制造或检测过程中由于热膨胀不同而引起的应力，在导电元件缺少这种移置时，这种应力将存在于电连接内。
介电区域50的厚度及其弹性模量的乘积所提供的柔性程度，可足以补偿由于第一微电子单元12与第二微电子单元14之间热膨胀的不匹配而施加至接合部分42的应变，第一微电子单元12通过接合部分而安装在第二微电子单元14上。可在介电区域50的外表面51与该第二微电子单元14之间设置底充胶（未示出），以增强对由于热膨胀系数不匹配而产生的热应变的阻力。
在所示的实施例中，介电区域50的外表面51（图1A）位于由基板20主表面21所限定的平面内。替代地，介电区域50的外表面51可高于由基板20主表面21所限定的平面而延伸，或介电区域的外表面可低于由基板主表面所限定的平面而凹陷。
介电层25可覆盖基板20的主表面21及导电元件40的不是接合部分42的部分，以对于基板和导电元件的不是接合部分的部分提供良好的介电隔离。介电层25可包括无机介电材料、或有机介电材料、或二者。在特定实施例中，介电层25可包括与介电区域50相同的柔性介电材料。在示例性的实施例中，介电层25可与介电区域50连续地形成。
第二微电子单元14可包括基板15及至少部分地在基板主表面17暴露的导电触点16a和16b，用于与第一微电子单元12的接合部分42互连。通过设置在第一微电子单元12内的接合部分42及第二微电子单元14内的后导电触点14，复数个微电子单元可以一个在另一个之上的方式堆叠在一起，以形成堆叠微电子组件10。在这种布置中，接合部分42与导电触点16a、16b对齐。
如图1A所示，导电触点16a为导电柱。导电柱16a可为任意类型的导电柱，且可具有任意形状，包括截头圆锥的形状。每个导电柱16a的基底与顶端可大致为圆形的，或具有不同形状，如椭圆形。导电柱可采用的其他示例，如共同拥有的申请号为12/832376、申请日为2010年7月8日的美国专利申请中所示及所描述。示出的导电触点16b为导电垫。导电垫16b可为任意形状，包括圆形、方形、椭圆形、矩形或更复杂的形状。
第一微电子单元12与第二微电子单元14之间的连接可通过导电块18。基板20主表面21上的介电层25和介电区域50以及覆盖基板15主表面17的介电层（如钝化层），可在第一微电子单元12与第二微电子单元14之间提供电隔离，除了所设置的互连以外。
导电块18可包括熔点相对低的易熔金属，如焊料、锡或包括复数种金属的低共熔混合物。替代地，导电块18可包括可湿性金属，如具有高于焊料或其他易熔金属熔点的铜或其他贵金属或非贵金属。这种可湿性金属可与如第二微电子单元14等互连元件的相应特征、如易熔金属特征接合，以使第一微电子单元12与这种互连元件外部互连。在特定实施例中，导电块18可包括在介质中散布的导电材料，例如导电膏，如填充金属的膏、填充焊料的膏，或包括各向同性的导电粘接剂或各向异性的导电粘接剂。
现在参照图2A至图2D，描述微电子组件10（图1A至图1D）的制造方法。如图2A所示，第一微电子单元12包括基板20和覆盖主表面21的一个或多个导电元件40。导电元件40可通过如钝化层（未示出）等的介电层而与基板20绝缘。
在图2B所示的制造阶段，在基板20的主表面21上形成介电层25，在主表面上需要保留其余部分的位置作为蚀刻掩模层。例如，可为如光致抗蚀剂层等的光致成像层的介电层25，沉积并图案化，使其只覆盖部分的主表面21，之后可进行定时蚀刻过程以形成凹陷30。每个导电元件40的接合部分42可仍至少部分地在主表面21暴露（即没有被介电层25覆盖），用于与第一微电子单元12外部的元器件连接。
可采用各种方法形成介电层25。在一个示例中，可流动的介电材料在基板20的主表面21涂敷，然后在“旋涂”操作过程中，可流动材料更均匀地沿主表面分布，随后是可包括加热的干燥周期。在其他示例中，介电材料的热塑性膜可铺在主表面21上，然后加热组件，或在真空环境中加热，即放置在低于外界压力的环境中加热。在另一示例中，可应用气相沉积形成介电层25。
在又一示例中，包括基板20的组件可浸入介电材料沉积槽中以形成保形的介电涂层或介电层25。在本文中应用的“保形涂层”（ "conformal coating"）是指，特定材料的涂层与被涂敷的表面的轮廓一致，例如当介电层25与主表面21的轮廓一致时。可应用电化学沉积法以形成保形的介电层25，例如包括，电泳沉积或电解沉积。
在一个示例中，可应用电泳沉积技术以形成保形的介电涂层，使得保形的介电涂层只沉积在组件暴露的导体与半导体的表面上。在沉积过程中，半导体器件晶圆可保持在所需的电位，电极浸入槽中以使槽保持在不同的所需电位。然后在适当的条件下，组件保持在槽中充足的时间，以在基板的暴露的导体或半导体的表面上形成电沉积的保形介电层25，包括但不限于沿着主表面21。只要在待涂敷表面与槽之间保持足够强的电场，电泳沉积就会发生。因为电泳沉积的涂层为自限制的，在涂层达到沉积过程中由如电压、浓度等参数确定的特定厚度后，沉积过程就会停止。
电泳沉积在组件的导体和/或半导体外表面上形成了连续的厚度均匀的保形涂层。另外，电泳涂层可沉积为涂层不在覆盖主表面21的剩余钝化层上形成，由于它的介电（非导电）性能。换言之，电泳沉积的特性为其不在覆盖导体的介电材料层上形成，假设该介电材料层具有保证其介电性能的足够厚度。典型地，电泳沉积将不在厚度大于约10微米至几十微米的介电层上发生。保形介电层25可由阴极环氧树脂沉积的反应源（precursor）形成。替代地，可应用聚氨酯或丙烯酸沉积的反应源。各种电泳涂层的反应源的成分及供应的原料来源在下面的表1中列出。
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在另一示例中，可电解形成介电层。除了沉积层不是仅限于在接近导体或半导体的表面上形成以外，这种过程与电泳沉积类似。以这种方式，可形成电解沉积的介电层，并达到根据需要所选择的厚度，处理时间是所获得厚度的一个影响因素。
此后，在图2C所示的制造阶段，可形成从基板20的主表面21向下朝第二表面22延伸的凹陷30。凹陷30可形成为，例如，在主表面21需要保留剩余部分的位置形成掩模层（如介电层25）后，通过选择性的蚀刻基板20以去除基板材料而形成。凹陷可形成为，使得除去至少支撑接合部分42的基板20材料。
从主表面21向下朝第二表面22延伸的凹陷30的内表面31，可为倾斜的，即可沿相对于主表面以不是正交（直角）的角度延伸，如图2C所示。如各向同性蚀刻工艺的湿蚀刻工艺、应用锥形刀片锯、及其他方法，都可用于形成具有倾斜内表面31的凹陷30。激光烧蚀、机械球磨、化学蚀刻、等离子蚀刻、朝基板20引入精细研磨粒子流、及其他，也可用于形成具有倾斜内表面31的凹陷30（或本文描述的任意其他孔或开口）。
替代地，凹陷30的内表面可沿竖直或基本竖直的方向从主表面21向下以与主表面21基本为直角的角度延伸，而不是倾斜的。各向异性的蚀刻工艺，激光烧蚀，例如研磨、超声波加工、朝基板20引入精细研磨粒子流等的机械去除工艺，及其他，都可用于形成具有基本竖直内表面的凹陷30。
此后，在图2D中所示的制造阶段，在凹陷30内形成介电区域50。介电区域50可包括无机材料、聚合物材料、或二者。可选择地，介电区域50可形成为，使得该区域的暴露外表面51与基板20的主表面21或介电层25的暴露表面，共面或基本共面。例如，自平面化的介电材料可沉积在凹陷30内，如通过分配（dispensing）或制版（stenciling）过程而沉积。在另一示例中，在形成介电区域50后，可对基板20的主表面21或介电层25的暴露表面应用研磨（grinding）、磨光（lapping）或抛光（polishing）过程，以使介电区域50的表面与主表面21或介电层25的暴露表面共面。
此后，再次参照图1A，第一微电子单元12可在第二微电子单元14之上堆叠，从而形成堆叠微电子组件10。如上所述，第一微电子单元12与第二微电子单元14之间的连接可通过导电块18。导电块18可提供第一微电子单元12的接合部分42与第二微电子单元14的导电触点16a、16b之间的电连接。在这种布置中，接合部分42可与导电触点16a、16b对齐。
现在参照图3A，根据本发明另一实施例的堆叠微电子组件110包括第一微电子单元112和第二微电子单元114。微电子单元112、114可具有与上述微电子单元12、14类似的功能。
第一微电子单元112包括具有凹陷130a、130b和导电元件140a、140b的基板120，凹陷130a、130b从主表面121部分地穿过基板朝与主表面相对的第二表面122延伸，每个导电元件140a、140b具有由基板支撑的相应锚部分141a、141b，至少部分地覆盖相应凹陷130a或130b且至少部分地在主表面暴露的相应接合部分142a或142b，在锚部分与接合部分之间延伸的一个或多个相应的连接部分145a或145b，及端头部分146，接合部分用于与第一微电子单元外部的元器件互连。如图所示，端头部分146设置在每个接合部分142a、142b的端部。至少在凹陷130a或130b内，介电区域150覆盖内表面131。
基板120进一步包括从开口130延伸至第二表面122的孔160、及在孔内从相应的锚部分141a或141b延伸至第二表面的导电通路170。导电通路170包括在第二表面122暴露的触点部分180，用于与堆叠微电子组件110外部的元器件互连。
基板120具有与参照图1A至图2D在上文所述的基板20类似的性能。例如，基板120优选地具有小于10 ppm/℃的热膨胀系数，及基板120优选地基本上由如半导体、玻璃或陶瓷等材料组成。在基板120由如硅等半导体制成的实施例中，基板内可设置复数个有源半导体器件。基板120可进一步包括覆盖主表面121和/或第二表面122的介电层（如“钝化层”）。
微电子元件112可包括在基板120主表面121暴露的一个或多个导电元件140a、140b。各导电元件140a、140b的接合部分142a、142b可在主表面121暴露，用于与第一微电子元件112外部的元器件、如第二微电子元件114互连。基板120内的有源半导体器件可与接合部分142a、142b电连接。
每个接合部分142a、142b可具有任意仰视形状。例如，如图3B所示，接合部分142a、142b可具有如薄平件等的导电结合垫的形状、或导电结合垫的一部分。例如，图3B和图3C所示的接合部分142b具有圆形的实心的仰视形状。图3B所示的接合部分142a具有圆形的仰视形状，具有贯穿延伸的孔隙147。图3C所示的接合部分的各段142a′一起具有圆形的仰视形状，具有贯穿延伸的孔隙147和在相邻接合部分的段之间延伸的间隙148。
接合部分142a、142b可具有其他仰视形状，例如包括，矩形迹线形状或矩形迹线形状的一部分。例如，图3D所示的接合部分142b″具有矩形的迹线形状。图3D所示的接合部分142a″为矩形迹线形状的两部分，具有位于其间的孔隙147。可替代地，接合部分142a、142b可具有更复杂的形状，在其他实施例中，接合部分142a、142b可为任意其他类型的导电触点，例如包括，导电柱。
接合部分142a、142b可与相应的凹陷130a、130b对齐，且可完全或部分地设置在由凹陷所限定的基板20区域内。从图3A可以看出，接合部分142a、142b完全地位于由相应凹陷130a、130b所限定的区域内。如图所示，由各接合部分142a、142b的顶面143a、143b所限定的平面大致平行于由基板120主表面121所限定的平面。如图所示，各接合部分142a、142b的底面144a、144b位于由基板120主表面121所限定的平面上。在其他实施例中，底面144a、144b可位于由主表面121所限定的平面上方或下方。
连接部分145a、145b从相应接合部分142a、142b向下延伸至相应锚部分141a、141b。连接部分145a、145b的至少一部分具有的轮廓与相应凹陷130a、130b的内表面131的轮廓不一致。在特定实施例中，可具有从锚部分141b延伸至接合部分142b的单个的迹线形状的连接部分145b。在替代实施例中，可具有从锚部分延伸的任意数量的连接部分。例如，在一个实施例中，连接部分145a可具有中空的截头圆锥形状，具有内部孔隙147，如图3B所示的实施例。在另一实施例中，可具有在单个锚部分141a与各接合部分之间延伸的四个单独的连接部分，如图3C所示的接合部分142a′。在又一实施例中，可为在单个锚部分141a与各接合部分之间延伸的两个单独的连接部分，如图3D所示的接合部分142a″。优选地，接合部分142a、142b的中心不在相应的连接部分145a、145b，使得相对于相应锚部分141a或141b，各导电元件140a或140b的端头部分146可为悬臂。
凹陷130a、130b与参照图1A至图2D所示及在上文所述的凹陷30类似。凹陷130a、130b从主表面121部分地穿过基板120朝第二表面122延伸。凹陷130a、130b的内表面131可从主表面121穿过基板120以任意角度延伸。优选地，内表面131从主表面121延伸，且相对于由主表面121所限定的水平面以0度至90度的角度延伸。
凹陷130a、130b可具有任意的仰视形状，例如包括，椭圆形、如图1B至图1D所示的凹陷130b，或为圆形、如图1B和图1C所示的凹陷130a。在一些示例中，凹陷130a、130b可具有任意的三维形状，例如包括、圆柱体、立方体、棱柱、截头圆锥及其他。在特定实施例中，凹陷130a、130b可为矩形通道，具有至少部分地覆盖凹陷的复数个相应接合部分142a、142b，布置为与图1D所示的接合部分42类似。
介电区域150具有与参照图1A至图2D所示及在上文所述的介电区域50类似的可能的布置和性能。例如，在图3A至图3D所示的实施例中，介电区域150填充凹陷130a、130b，使得介电区域的轮廓与凹陷的轮廓（即凹陷内表面131的形状）一致。介电区域150可为柔性的，具有足够低的弹性模量和足够厚度，使得模量与厚度的乘积可提供柔性。优选地，接合部分142a、142b至少部分地覆盖介电区域150，使得接合部分可相对于基板120移动。
与参照图1A至图2D在上文所述的介电层25类似，介电层125可覆盖基板120的主表面121及导电元件140a、140b的不是接合部分142a、142b的部分，以对于基板和导电元件的不是接合部分的部分，提供良好的介电隔离。
如图3A至图3D所示，孔160是分段式的，包括从开口130朝第二表面122延伸的第一开口161、及从第一开口延伸至第二表面的第二开口162。分段式的孔160可具有在以下专利申请中更详细示出及描述的任意结构，如共同拥有的申请号为12/842717、申请日为2010年7月23日的美国专利申请，及共同拥有的公开号为2008/0246136的美国专利申请公开说明书，其公开的内容以引用的方式并入本文。在其他实施例中，如参照图6所示及描述的孔60b，孔可具有更简单的不分段的结构。
第一开口161从凹陷130部分地穿过基板120朝第二表面122延伸。第一开口161包括内表面163，它从凹陷130穿过基板120相对于由主表面121所限定的水平面以0度至90度之间的角度延伸。内表面163可具有恒定的斜度或变化的斜度。例如，当内表面163进一步朝第二表面122深入时，内表面163相对于由主表面121所限定的水平面的角度或斜度的绝对值可减小（即正、负幅度减小）。例如，如图4D所示，第一开口161在凹陷130处具有宽度W1，而在第一开口与第二开口162相交处具有比W1小的宽度W2，从而沿从主表面121朝第二表面122的方向，第一开口逐渐变细。在其他示例中，第一开口可具有恒定的宽度，或第一开口可沿从第二表面朝正面的方向逐渐变细。第一开口161可具有任意三维形状，例如包括，立方体、圆柱体、截头圆锥、或棱柱、及其他。
第二开口162从第一开口161部分地穿过基板120朝第二表面122延伸。第二开口162包括内表面164，它从第一开口161穿过基板120相对于由主表面121所限定的水平面以0度至90度之间的角度延伸。与上述的内表面163类似，内表面164可具有恒定的斜度或变化的斜度。例如，如图4D所示，在第二开口与第一开口161相交处，第二开口162具有宽度W3，而在第二表面122处具有比W3大的宽度W4，从而沿从第二表面122朝主表面121的方向，第一开口逐渐变细。在其他示例中，第二开口可具有恒定的宽度，或第二开口可沿从正面朝第二表面的方向逐渐变细。第二开口162可具有任意三维形状，例如包括，立方体、圆柱体、截头圆锥、或棱柱、及其他。
在特定实施例中，内表面163、164可相对于主表面121分别以第一方向和第二方向延伸，以限定明显的角度。任意数量的第一开口161可从单个第二开口162延伸，且任意数量的第二开口可从单个第一开口延伸。相对于彼此及相对于基板120，第一开口161和第二开口162可以任意几何布局布置。各种第一开口和第二开口的布局及形成这些布局的方法的特定示例，在上述共同拥有的申请号为12/842717及公开号为2008/0246136的美国专利申请公开说明书中都有描述。
各导电元件140a、140b的锚部分141a、141b，优选地具有与相应第一开口161的轮廓一致的轮廓，使得锚部分具有相对于基板120固定的位置。当处于如相对于附接的微电子元件因热膨胀不同而导致的机械应力下时，锚部分141a或141b可作为支点，附接的接合部分142a或142b可绕其枢转。
导电通路170穿过孔160在相应的锚部分141a或141b与第二表面122之间延伸。如图3A所示，导电通路170可充满第二开口162内的所有容积，第二开口在可使基板120与导电通路电绝缘的可选用的介电层（未示出）的内部。导电通路170可与第二开口162的轮廓一致。导电通路170可具有圆柱或截头圆锥的形状。导电通路170可由金属或导电金属化合物制成，例如包括，铜或金。
在其他实施例中（未示出），导电通路170的轮廓（即导电通路外表面的形状）与第二开口162的轮廓（即第二开口内表面164的形状）不一致。在这种非保形导电通路的实施例中，导电通路170可具有任意形状，例如包括，圆柱形、截头圆锥形，或圆柱和截头圆锥在距离第二表面122不同位置处组合。
导电通路170可为实心的或中空的。在一些实施例中，导电通路可包括用介电材料填充的内部空间。例如，导电通路170可通过沉积覆盖第二开口162的内表面164的金属而形成，从而生成覆盖第二开口内表面的导电层。各种导电通路结构及这些结构的形成方法的特定示例，在上述共同拥有的申请号为12/842717的美国专利申请、及公开号为2008/0246136的美国专利申请公开说明书中都有描述。
每个导电通路170都包括在第二表面122暴露的触点部分180，用于与堆叠组件110外部的元器件互连。在一些实施例中，每个导电通路170都可与在第二表面122暴露的分隔开的导电触点电耦合。
第二微电子单元114与参照图1A所示及在上文所述的第二微电子单元14类似。第二微电子单元114可包括基板115和至少部分地在基板主表面117暴露的导电触点116，用于与第一微电子单元112的接合部分142a、142b互连。
如图3A所示，导电触点116为导电垫。导电垫116可具有任意形状，包括圆形、方形、椭圆形、矩形或更复杂的形状。在特定实施例中，导电触点116可为任意类型的导电触点，例如包括，导电柱，如图1A所示导电柱16a。可采用的导电柱的其他示例，如共同拥有的申请号为12/832376、申请日为2010年7月8日的美国专利申请中所示及所描述。
第一微电子单元112与第二微电子单元114之间的连接可通过导电块118，以参照图1A至图2D所描述类似的方式。基板120主表面121上的介电层125、介电区域150及覆盖基板115主表面117的介电层（如钝化层）可在第一微电子单元112与第二微电子单元114之间提供电隔离，除了所设置的互连以外。
现在参照图4A至图4D，描述微电子组件110（图3A至图3D）的制造方法。在图4A所示的制造阶段，第一微电子单元112包括基板120。通过从基板去除材料，可形成从基板120主表面121延伸至第二表面122的孔160。在特定实施例中，可形成从主表面121向内延伸的第一开口161，并可形成从第二表面122向内延伸的第二开口。在其他实施例中，第一开口161和第二开口162中任一个或二者，可或者从主表面121形成、或者从第二表面122形成。
孔160可采用参照形成凹陷30在上文所述类似的过程而形成。例如，在主表面121需要保留剩余部分的位置形成掩模层后，孔160可通过选择性地蚀刻基板120、以从基板去除材料而形成。与凹陷30类似，相对于主表面121，第一开口161的内表面163和第二开口162的内表面164可以任意恒定或变化的角度延伸。
尽管没有示出，可选择地形成在基板120的主表面121上和/或覆盖第一开口161的内表面163及第二开口162的内表面164的介电层，使导电元件140a、140b和导电通路170与基板电隔离。这种介电层可采用参照图2B所示介电层25在上文所述的各种方法中任意方法而形成。这种介电层可附加于或取代已覆盖基板120主表面121的钝化层。
在图4B所示的制造阶段，可在第一开口161内形成导电元件140a、140b的锚部分141a、141b和相应的连接部分145a、145b，可形成覆盖主表面121的接合部分142a、142b，及可在第二开口162内形成导电通路170，触点部分180在第二表面122暴露。锚部分141a、141b，连接部分145a、145b，接合部分142a、142b，和导电通路170中，每个都可在单个金属沉积过程或各自的过程中形成。在导电通路170与在第二表面122暴露的分隔开的导电触点电耦合的实施例中，这种导电触点可与导电元件140a、140b及导电通路在单个金属沉积过程中形成，或者这种导电触点可在单独的过程中形成。
形成导电元件140a、140b和导电通路170的示例方法包括沉积金属层，通过在基板20的暴露表面上一次或多次喷射原生金属层（primary metal layer）、电镀或机械沉积的方法而沉积。机械沉积可包括在高速下引入加热的金属微粒流至待涂敷表面的步骤。例如，这个步骤可通过在主表面21、内表面163、164上包层沉积（blanket deposition）而进行。在一个实施例中，原生金属层包括或主要由铝组成。在另一特定实施例中，原生金属层包括或主要由铜组成。在又一实施例中，原生金属层包括或主要由钛组成。一种或多种其他示例金属也可在形成导电元件140a、140b和导电通路170的过程中应用。在特定示例中，可在上述表面中的一个或多个表面上形成包括复数个金属层的堆叠。例如，层叠的金属层可包括钛层伴有覆盖在钛层上的铜层（钛-铜，Ti-Cu）、镍层伴有覆盖在镍层上的铜层（镍-铜，Ni-Cu）、以类似的方式设置的镍-钛-铜（Ni-Ti-Cu）的堆叠、或镍-钒（Ni-V）的堆叠。
在特定实施例中，在从基板上去除任何材料之前，可在基板120的主表面121上沉积接合部分142a、142b，例如，如图2A所示的制造阶段。在这个实施例中，例如通过贯穿接合部分142a和/或142b而蚀刻，然后蚀刻至基板120内，可形成孔160。在穿过接合部分142a和/或142b的孔160形成后，可如上所述形成连接部分145a、145b，锚部分141a、141b和导电通路170。
在图4C所示的制造阶段，在基板120的主表面121上形成介电层125，作为在主表面需要保留剩余部分的位置的蚀刻掩模层。介电层125可采用参照图2B所示的介电层25在上文所述的各种方法中任意方法而形成。接合部分142a、142b可仍至少部分地在主表面121暴露（即，没有被介电层125覆盖），用于与第一微电子单元112外部的元器件连接。
此后，在图4D所示的制造阶段，以参照形成凹陷30而在上文所述类似的方式、采用类似的过程，可形成凹陷130。例如，在主表面121所需保留剩余部分的位置形成掩模层（如介电层25）后，可选择性地蚀刻基板120、以去除基板材料而形成凹陷130。凹陷130可形成为，使得除去至少支撑接合部分142a、142b的基板材料。与凹陷30类似，凹陷130的内表面131可相对于主表面121以任意恒定或变化的角度延伸。
如图4D所示，凹陷130可形成为，使得它们远离主表面121延伸的距离不如第一开口161远，并使得锚部分141a、141b的轮廓与第一开口内表面163剩余部分的轮廓一致。在特定实施例中，凹陷130可形成为，使得它们远离主表面121延伸的距离至少与第一开口121一样远，并使得锚部分141a、141b的轮廓与基板120的任意内表面的轮廓都不一致。在这样的实施例中，通过锚部分与导电通路170之间的附接，锚部分141a、141b可固定至基板120，导电通路170可具有与第二开口162内表面164的轮廓一致的轮廓。
此后，在图4E所示的制造阶段，以参照形成凹陷30内介电区域50而在上文所述类似的方式、采用类似的过程，可在凹陷130内形成介电区域150。例如，介电区域150可形成为，使得该区域的暴露外表面151与基板120的主表面121（如图4E所示）或介电层125的暴露表面共面或基本共面。
此后，再次参照图3A，第一微电子单元112可在第二微电子单元114之上堆叠，从而形成堆叠微电子组件110。如上所述，第一微电子单元112与第二微电子单元114之间的连接可通过导电块118。导电块118可提供第一微电子单元112的接合部分142a、142b与第二微电子单元114的导电触点16之间的电连接。在这种布置中，接合部分142a、142b可与相应导电触点16对齐。
如图5所示，示出的导电元件240的基底部分241和接合部分242，适于在参照图1A至图4E在上文所述的任意实施例中采用。接合部分242从导电元件240的基底部分241延伸。基底部分241可为参照图3A所示第一微电子单元112在上文所述的接合部分142a、142b的一部分，或为参照图1A所示第一微电子单元12在上文所述的锚部分41的一部分。基底部分241可与位于基板220的主表面221下方、或介电区域250的外表面251下方的其他导电元件连接。在图5所示的实施例中，基底部分241包括可为柔性的或能够以沿主表面221所限定平面的方向移动的段243，使得该段能够以沿主表面221的方向被施加的外部负载移置。
现在参照图6，除了导电元件40′与在基板20′的主表面21与第二表面22之间延伸的导电通路70a、70b电连接以外，根据另一实施例的第一微电子组件12′与图1A所示的第一微电子组件12类似。
基板20′包括从主表面21和第二表面22延伸的孔60a、60b，及在相应孔内从导电元件40′的相应锚部分41′延伸至第二表面的导电通路70a、70b。每个导电通路70a、70b包括在第二表面22暴露的触点部分80，用于与第一微电子单元12′外部的元器件互连。孔60a是分段式孔，与图3A所示的孔160类似，除了开口30不与孔60a、60b中任一个重叠以外，因此孔60a、60b从第二表面22延伸至主表面21，而不是从第二表面延伸至相应开口。孔60b是不分段的，即，孔60b可形成为，例如，在单个蚀刻或其他过程中从基板20′去除材料而形成。
与图1A所示的第一微电子组件12类似，每个导电元件40包括可在主表面21暴露的接合部分42，用于与第一微电子元件12′外部的元器件互连。同样与第一微电子组件12类似，介电区域50可为柔性的，从而每个接合部分42可相对于基板20′可移动。
图7绘出的模块300包括在一个单元内布置在一起的至少两个微电子组件310，具有电气接口320，用于向每个微电子组件310及从每个微电子组件310传输信号。电气接口可包括一个或多个触点，用于传输信号或如电源或地面等的参照电位，对其内的每个微电子元件来说共用的。微电子组件310可为上述的任意组件。在特定示例中，模块300可为双列直插内存模块（“DIMM”）或单列直插内存模块（“SIMM”），具有一个或多个部分，其大小制作成用于插入至如可设置在主板上的系统相应的插槽或其他接头内。在这种DIMM或SIMM中，电气接口可具有适于与这种插槽接头内的复数个弹性触点匹配的触点330。这种弹性触点可设置在每个插槽的一侧或多侧，以与相应的模块触点匹配。各种其他模块和互连布置都是可能的，其中模块可具有非堆叠的或堆叠的微电子组件，或可具有并行的或串行的电气接口，或并行的与串行的电气接口的组合，用于向模块或从模块传输电信号。模块300与另一系统接口之间的任意类型电互连布置是本发明所考虑的。
上述的微电子组件可在不同电子系统的结构中利用，如图8所示的系统。例如，根据本发明另一实施例的系统400，包括上述的微电子组件406与其他电子元器件408、410的配合使用。在所示的示例中，元器件408为半导体芯片，而元器件410为显示屏，但任意其他元器件都可应用。当然，尽管为清楚图示起见，在图8中只描述了两个附加元器件，系统可包括任意数量的这种元器件。微电子组件406可为上述的任意组件。在另一变例中，任意数量的这种微电子组件都可应用。
微电子组件406和元器件408、410都安装至以虚线示意性地描绘的共同外壳401内，且彼此电互连以形成所需的电路。在所示的示例性系统中，系统包括如柔性印刷电路板等的电路板402，且电路板包括使元器件之间彼此互连的大量导电体404，其中在图8中只示出了一个。但是，这只是示例，任意适当的用于形成电连接的结构都可应用。
外壳401作为便携式外壳而绘出，具有用于如移动电话或个人数字助理等的类型，显示屏410暴露在外壳的表面。其中结构406包括如成像芯片等的光敏元件，还可配置镜头411或其他光学器件，以提供光至结构的路线。同样，图8内所示的简化系统只是示例，其他系统，包括一般视为固定结构的系统，如台式计算机、路由器及类似的结构，都可应用上述的结构而制成。
本文公开的通路和通路导电体可通过以下专利申请中非常详细描述的过程而形成，如在共同待决、共同转让的专利申请号分别为12/842587、12/842612、12/842651、12/842669、12/842692和12/842717，申请日都为2010年7月23日的美国专利申请中，及在申请公开号为2008/0246136的已公开的美国专利申请公开说明书中，所有这些专利申请公开的内容以引用的方式并入本文。
尽管本发明参照特定实施例进行描述，可以理解的是，这些实施例只是说明本发明的原理和应用。因此，应理解为，在不偏离由附加的权利要求书所限定的本发明实质和范围的情况下，说明的实施例可做出许多修改及可设计出其他布置。
可是理解的是，各从属权利要求及其阐述的特征可以与存在于最初权利要求书中的不同的方式组合。也可理解的是，与单个实施例结合进行描述的特征可与其他已描述的实施例共用。
工业实用性
本发明具有广泛的工业实用性，包括但不限于，微电子单元和微电子单元的制造方法。

Claims (37)

1. 微电子单元，包括：
基板，具有小于10ppm/℃的热膨胀系数，其主表面具有未贯穿所述基板而延伸的凹陷，弹性模量小于10GPa的材料设置在所述凹陷内；及
导电元件，包括覆盖所述凹陷、并从由所述基板支撑的锚部分延伸的接合部分，所述接合部分至少部分地在所述主表面暴露，用于与所述微电子单元外部的元器件连接。
2. 根据权利要求1所述的微电子单元，其中所述基板具有小于7 ppm/℃的热膨胀系数。
3. 根据权利要求1所述的微电子单元，其中所述接合部分为可移动的，从而降低如在所述微电子单元工作、制造或检测过程中可能存在于所述接合部分的应力。
4. 根据权利要求1所述的微电子单元，其中所述基板基本上从由半导体、玻璃和陶瓷组成的群组中选择的一种材料组成。
5. 根据权利要求1所述的微电子单元，其中所述基板包括复数个有源半导体器件，且所述导电元件与所述复数个有源半导体器件中至少一个电连接。
6. 根据权利要求1所述的微电子单元，其中设置在所述凹陷内的所述材料包括从由聚酰亚胺、硅树脂和环氧树脂组成的群组中选择的至少一种材料组成。
7. 根据权利要求1所述的微电子单元，其中所述凹陷未贯穿所述基板而延伸。
8. 根据权利要求1所述的微电子单元，其中所述接合部分沿大致平行于所述基板的主表面的方向延伸。
9. 根据权利要求1所述的微电子单元，其中所述锚部分和所述接合部分沿相同方向延伸。
10. 根据权利要求9所述的微电子单元，其中所述导电元件与导电通路电耦合，所述导电通路朝所述基板的与所述主表面相对的第二表面延伸。
11. 根据权利要求10所述的微电子单元，其中所述导电通路在所述第二表面暴露。
12. 根据权利要求10所述的微电子单元，其中所述导电通路在所述基板的孔内延伸，所述孔从所述第二表面延伸至所述主表面。
13. 根据权利要求12所述的微电子单元，其中所述孔包括第一开口和第二开口，所述第一开口从所述主表面朝着所述第二表面延伸，所述第二开口从所述第一开口延伸至所述第二表面，其中所述第一开口的内表面和所述第二开口的内表面相对于所述主表面分别沿第一方向和第二方向延伸，以限定明显的角度。
14. 堆叠组件，至少包括第一微电子单元和第二微电子单元，所述第一微电子单元如权利要求1所述，所述第二微电子单元与所述第一微电子单元堆叠，所述第一微电子单元的基板与所述第二微电子单元的基板电连接。
15. 根据权利要求14所述的堆叠组件，进一步包括与所述第一微电子单元的接合部分及所述第二微电子单元的导电元件电耦合的导电块。
16. 系统，包括根据权利要1所述的结构，及与所述结构电连接的一个或多个其他电子元器件。
17. 根据权利要求16所述的系统，进一步包括外壳，所述结构和所述其他电子元器件安装至所述外壳。
18. 模块，包括复数个根据权利要求1所述的微电子组件，所述模块具有共用的电气接口，用于向或从每个所述微电子组件传输信号。
19. 制造微电子单元的方法，包括：
形成支撑在基板的主表面上的导电元件，所述基板具有小于10ppm/℃的热膨胀系数；
从所述主表面除去至少支撑所述导电元件的接合部分的材料，以形成未贯穿所述基板而延伸的凹陷，使得所述接合部分不被所述基板支撑，而所述导电元件的邻接所述接合部分的锚部分被所述基板支撑；及
在所述凹陷内沉积弹性模量小于10GPa的材料，
其中所述接合部分至少部分地在所述基板的主表面暴露，用于与所述微电子单元外部的元器件连接。
20. 根据权利要求19所述的方法，其中所述基板具有小于7ppm/℃的热膨胀系数。
21. 根据权利要求19所述的方法，其中所述基板基本上从由半导体、玻璃和陶瓷组成的群组中选择的一种材料组成。
22. 根据权利要求19所述的方法，其中所述基板包括复数个有源半导体器件，而在形成所述导电元件的步骤中，使所述导电元件与所述复数个有源半导体器件中的至少一个电连接。
23. 根据权利要求19所述的方法，其中进行所述形成导电元件的步骤时，使得所述接合部分设置为大致平行于所述主表面。
24. 根据权利要求19所述的方法，进一步包括：
从所述基板上去除材料以形成孔，所述孔从所述主表面延伸至所述基板的与所述主表面相对的第二表面；及
形成在所述孔内延伸的导电通路，使得所述导电通路与所述导电元件电耦合，且朝着所述第二表面延伸。
25. 根据权利要求24所述的方法，其中从所述基板上去除材料以形成孔的步骤包括，形成从所述主表面朝所述第二表面延伸的第一开口、及从所述第一开口延伸至所述第二表面的第二开口，其中所述第一开口的内表面和所述第二开口的内表面相对于所述主表面分别沿第一方向和第二方向延伸，以限定明显的角度。
26. 制造至少包括第一微电子单元和第二微电子单元的堆叠组件的方法，所述第一微电子单元根据权利要求19所述的方法制造，进一步包括，使所述第一微电子单元的基板与所述第二微电子单元的基板电连接的步骤。
27. 制造微电子单元的方法，包括：
从基板上去除材料以形成孔，所述基板具有小于10ppm/℃的热膨胀系数，所述孔从所述基板的主表面延伸至所述基板的与所述主表面相对的第二表面；
形成导电元件，所述导电元件具有在所述主表面上延伸并由所述主表面支撑的接合部分、与所述基板相对固定的锚部分、及从所述接合部分向下延伸至所述锚部分的连接部分，所述连接部分的表面的轮廓与所述孔的内表面的轮廓一致；
从所述主表面除去至少支撑所述导电元件的接合部分的材料以形成凹陷，使得所述接合部分至少部分地覆盖所述凹陷，所述连接部分的表面的轮廓与所述凹陷的内表面的轮廓不一致；及
在所述凹陷内沉积弹性模量小于10GPa的材料，
其中所述接合部分至少部分地在所述基板的主表面暴露，用于与所述微电子单元外部的元器件连接。
28. 根据权利要求27所述的方法，其中所述基板具有小于7 ppm/℃的热膨胀系数。
29. 根据权利要求27所述的方法，进一步包括，在形成所述导电元件的步骤之前，形成在所述孔内延伸、并朝所述第二表面延伸的导电通路，使得在形成所述导电元件的步骤中，使所述导电元件与所述导电通路电耦合。
30. 根据权利要求27所述的方法，其中进行形成所述导电元件的步骤时，使得所述接合部分的中心不在所述连接部分。
31. 根据权利要求27所述的方法，其中所述基板基本上从由半导体、玻璃和陶瓷组成的群组中选择的一种材料组成。
32. 根据权利要求27所述的方法，其中所述基板包括复数个有源半导体器件，在形成所述导电元件的步骤中，使所述导电元件与所述复数个有源半导体器件中至少一个电连接。
33. 根据权利要求27所述的方法，其中进行形成所述导电元件的步骤时，使得所述接合部分限定内部孔隙。
34. 根据权利要求33所述的方法，其中进行形成所述导电元件的步骤时，使得所述孔隙穿过所述接合部分延伸至所述连接部分内。
35. 根据权利要求34所述的方法，进一步包括，在所述孔隙的至少一部分内沉积介电材料。
36. 根据权利要求27所述的方法，其中从基板上去除材料以形成孔的步骤包括，形成从所述主表面朝着所述第二表面延伸的第一开口、及从所述第一开口延伸至所述第二表面的第二开口，其中所述第一开口的内表面和所述第二开口的内表面相对于所述主表面分别沿第一方向和第二方向延伸，以限定明显的角度。
37. 制造至少包括第一微电子单元和第二微电子单元的堆叠组件的方法，所述第一微电子单元根据权利要求27所述的方法制造，进一步包括，使所述第一微电子单元的基板与所述第二微电子单元的基板电连接的步骤。
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