CN103354205B - The method improving polycrystalline silicon gate grid etching process stability - Google Patents
The method improving polycrystalline silicon gate grid etching process stability Download PDFInfo
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- CN103354205B CN103354205B CN201310256210.2A CN201310256210A CN103354205B CN 103354205 B CN103354205 B CN 103354205B CN 201310256210 A CN201310256210 A CN 201310256210A CN 103354205 B CN103354205 B CN 103354205B
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Abstract
The method improving polycrystalline silicon gate grid etching process stability of the present invention, including: a Semiconductor substrate is provided, forms grid oxide layer on a semiconductor substrate；Grid oxide layer is formed layer of oxide layer；Oxide layer coats a layer photoetching glue, etched, the oxide layer of polysilicon gate region is removed, removes photoresist；Growing polycrystalline silicon layer on a semiconductor substrate；Through photoetching and etching, polysilicon layer forms described polysilicon gate.The method of the present invention, during etches polycrystalline silicon gate, by increasing layer of oxide layer, it is to avoid the phenomenon that active area that the etching selection ratio of polysilicon gate and grid oxide layer causes not is impaired, thus improve the electrical property of polycrystalline silicon gate grid etching process stability and product.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, be specifically related to a kind of raising etching polysilicon gate work
The method of skill stability.
Background technology
Along with the development of semiconductor technology, the size of semiconductor devices is more and more less, particularly at 65nm
And in following technique, in order to meet electrical demand, grid oxide layer thins down, to polysilicon gate
The requirement of the etching technics of pole is more and more higher.
As shown in figures 1 to 6, Fig. 1 is the schematic flow sheet of conventional etching polysilicon gate method, Fig. 2-6
The cross section structure schematic diagram formed by each preparation process of conventional etching polysilicon gate method, including:
Step S11: refer to Fig. 2 a, it is provided that Semiconductor substrate 101, in Semiconductor substrate 101
Form grid oxide layer 102；
Step S12: refer to Fig. 3, growing polycrystalline silicon layer 103 on grid oxide layer 102；
Step S13: refer to Fig. 4, sequentially forms hard mask layer 104 on polysilicon layer 103 and prevents
Reflecting layer 105；
Step S14: refer to Fig. 5, uses photoetching process, is sequentially etched anti-reflection layer 105 and firmly covers
Film layer 104；
Step S15: refer to Fig. 6, with hard mask layer 104 as masterplate, continues etching, at polysilicon
Layer 103 is formed polysilicon gate.
So, in the technique of etches polycrystalline silicon gate, due to polysilicon layer 103 and grid oxide layer 102 it
Between etching selection ratio big not, thus active area can be caused after etches polycrystalline silicon layer 103 impaired, as
Defect 106 shown in Fig. 6, cuts through grid oxide layer 102, etches in Semiconductor substrate 101, thus makes
About the increase of polycrystalline silicon etching process window, reduce and improve the range of choice that polysilicon gate is electrical.
Generally, in order to improve the etching selection ratio between polysilicon gate and grid oxide layer, photoetching is used to combine
The ashing of glue processes technique and hard mask dressing technique etc., and these methods can make the polysilicon gate after etching
The pattern of pole changes, and such as becomes to tilt, so, although etching selection ratio can be improved, but,
Product electrically can be produced impact.
Summary of the invention
In order to overcome the problems referred to above, the purpose of the present invention is intended to avoid due to polysilicon gate and grid oxide layer
Etching selection ratio causes not greatly the phenomenon that active area is impaired, thus improves etching polysilicon work further
Skill stability.
A kind of method improving polycrystalline silicon gate grid etching process stability of the present invention, including:
Step S01 a: Semiconductor substrate is provided, forms grid oxide layer on the semiconductor substrate；
Step S02: form layer of oxide layer on described grid oxide layer；
Step S03: coat a layer photoetching glue in described oxide layer, etched, by described polysilicon gate
The described oxide layer in territory, polar region is removed, and removes described photoresist；
Step S04: growing polycrystalline silicon layer on the semiconductor substrate；
Step S05: through photoetching and etching, forms described polysilicon gate in described polysilicon layer.
Preferably, the forming method of described oxide layer, including:
Step S21: measure described polysilicon layer etch rate and described oxide layer etch rate respectively；
Step S22: set described polysilicon layer thicknesses, calculates the thickness of described oxide layer, described meter
Calculating the formula used is: d=a/b*c, and wherein, a is for setting polysilicon layer thicknesses, and b is that polysilicon layer is carved
Erosion speed, c is oxide layer etch rate, and d is the thickness of oxide layer；
Step S23: form the described oxide layer of the thickness of described calculating on described grid oxide layer.
Preferably, described photoresist is negative photoresist.
Preferably, described polysilicon gate region is positioned at the active region of described Semiconductor substrate.
Preferably, the material of described oxide layer is silica.
Preferably, chemical vapour deposition technique is used to form described oxide layer.
Preferably, in described step S05, including:
Step S51: sequentially form hard mask layer and anti-reflection layer on described polysilicon layer；
Step S52: use photoetching process, be sequentially etched described anti-reflection layer and hard mask layer；
Step S53: with described hard mask layer as masterplate, continues etching, is formed in described polysilicon layer
Described polysilicon gate.
Preferably, the material of described hard mask layer is silicon nitride.
Preferably, containing N-type active area and p-type active area in described Semiconductor substrate.
Preferably, fleet plough groove isolation structure is included in described Semiconductor substrate and below described grid oxide layer.
The method improving polycrystalline silicon gate grid etching process stability of the present invention, by conventional etching work
On the basis of skill, before growing polycrystalline silicon layer, on grid oxide layer, redeposited layer of oxide layer, utilizes this oxygen
Change layer and improve the thickness of grid oxide layer, then use photoetching process, remove the oxidation of polysilicon gate region
Layer segment, retains the oxide layer of other parts, so, during etches polycrystalline silicon gate, due to
Add layer of oxide layer, it is to avoid what the etching selection ratio of polysilicon gate and grid oxide layer caused not has
The phenomenon that source region is impaired；
Meanwhile, increase layer of oxide layer and can not have influence on the product electrical requirements to grid oxide layer, not only gram
Take the problem that etching selection ratio is the biggest, and the polysilicon gate pattern after etching do not changed,
Such that it is able to carry out the regulation of more polysilicon gate pattern, improve etching technics stability and product
Electrical property.
Accompanying drawing explanation
Fig. 1 is the schematic flow sheet of conventional etching polysilicon gate method
The cross section structure that Fig. 2-6 is formed by each preparation process of conventional etching polysilicon gate method shows
It is intended to
Fig. 7 is the side improving polycrystalline silicon gate grid etching process stability of a preferred embodiment of the present invention
The schematic flow sheet of method
Fig. 8-14 is the raising polycrystalline silicon gate grid etching process stability of the above-mentioned preferred embodiment of the present invention
The cross section structure schematic diagram corresponding to each preparation process of method
Figure 15 is the schematic flow sheet of the forming method of the oxide layer of a preferred embodiment of the present invention
Detailed description of the invention
Embodiment feature of present invention will describe with the embodiment of advantage in the explanation of back segment in detail.It should be understood that
Being that the present invention can have various changes in different examples, it neither departs from the scope of the present invention,
And explanation therein and being shown in substantially as purposes of discussion, and be not used to limit the present invention.
Below in conjunction with accompanying drawing 7-15, by the specific embodiment raising etching polysilicon gate work to the present invention
The method of skill stability is described in further detail.It should be noted that, accompanying drawing all uses the shape simplified very much
Formula, use non-ratio accurately, and only in order to convenient, reach to aid in illustrating the embodiment of the present invention lucidly
Purpose.
Referring to Fig. 7-15, Fig. 7 is the raising etching polysilicon gate of a preferred embodiment of the present invention
The schematic flow sheet of the method for technology stability, Fig. 8-14 is the raising of the above-mentioned preferred embodiment of the present invention
The cross section structure schematic diagram corresponding to each preparation process of the method for polycrystalline silicon gate grid etching process stability,
Figure 15 is the schematic flow sheet of the forming method of the oxide layer of a preferred embodiment of the present invention, the present invention
Improve polycrystalline silicon gate grid etching process stability method, including:
Step S01: refer to Fig. 8 a, it is provided that Semiconductor substrate 301, in Semiconductor substrate 301
Form grid oxide layer 302；Concrete, the Semiconductor substrate of the present invention can be any substrate, such as silicon lining
The end, MOS substrate etc., in the present embodiment of the present invention, active containing N-type in Semiconductor substrate 301
District and p-type active area；In another preferred embodiment, in Semiconductor substrate and can under grid oxide layer
To include fleet plough groove isolation structure；In the present embodiment, the formation of grid oxide layer 302 can use but not limit
In chemical vapour deposition technique.
Step S02: refer to Fig. 9, forms layer of oxide layer 303 on grid oxide layer 302；Concrete,
In the present embodiment, the forming method of oxide layer 303, refer to Figure 15, including:
Step S21: measure polysilicon layer etch rate and oxide layer etch rate respectively；Concrete, many
The measurement of crystal silicon layer etch rate and oxide layer etch rate can be, but not limited to for analogue measurement, such as use
The simulation calculation of computer program design, or carry out the measurement of reality, can be by the thickness etched
Obtain divided by the time consumed；
Step S22: set polysilicon layer thicknesses, calculates the thickness of oxide layer, calculates the formula used
For: d=a/b*c, wherein, a is for setting polysilicon layer thicknesses, and b is polysilicon layer etch rate, and c is oxygen
Changing layer etch rate, d is the thickness of oxide layer；Here, according to actual process requirement, set polysilicon
The thickness a of grid, then utilizes above-mentioned formula to calculate oxidated layer thickness d；
Step S23: form the oxide layer of the thickness of calculating on grid oxide layer；Concrete, in the present embodiment,
The oxide layer that chemical vapor deposition thickness can be used to be d, the material of oxide layer can be oxidation
Silicon.
Step S03: refer to Figure 10, coats a layer photoetching glue in oxide layer 303, etched,
Oxide layer 303 etches polysilicon gate region, removes photoresist；Concrete, in the present embodiment,
The photoresist used is negative photoresist, that is to say exposed development, polysilicon gate in the photoresist
The pattern in region is removed, and remaining photoresist part retains, then, utilize this photoresist for template, right
Oxide layer performs etching, and can be, but not limited to using plasma dry etching, by polysilicon gate region
Oxide layer remove, retain remaining oxide layer, then photoresist removed；It should be noted that by
The active region of Semiconductor substrate 301 it is positioned in polysilicon gate, so, many in oxide layer 303
Polysilicon gate region also is located at the active region of Semiconductor substrate 301.
Step S04: refer to Figure 11, growing polycrystalline silicon layer 304 in Semiconductor substrate 301；Specifically
, in the present embodiment, the growing method of polysilicon layer 304 can be, but not limited to as chemical vapour deposition technique,
Polysilicon layer 304 some be positioned in the polysilicon region of above-mentioned oxide layer 303, other parts are positioned at
The surface of oxide layer 303；
Step S05: through photoetching and etching, forms polysilicon gate in polysilicon layer 304；Concrete,
In the present embodiment, the formation of polysilicon gate includes:
Step S51: refer to Figure 12, sequentially forms hard mask layer 305 on polysilicon layer 304 and prevents
Reflecting layer 306；Here it is possible to but be not limited to use chemical vapour deposition technique to form hard mask layer 305 He
Anti-reflection layer 306, the material of hard mask layer 305 can be silicon nitride, and the material of anti-reflection layer 306 can
Think inorganic material, it is also possible to for organic material.
Step S52: refer to Figure 13, uses photoetching process, is sequentially etched anti-reflection layer 306 and firmly covers
Film layer 305；Concrete, in the present embodiment, on anti-reflecting layer 306, first coat a layer photoetching glue,
Then, exposed and developed, this layer photoetching glue etches the pattern of polysilicon gate region, then with
This photoresist is template, first etching anti-reflection layer 306, then etches hard mask layer 305, finally at hard mask
Layer 305 etches the pattern of polysilicon gate region；
Step S53: refer to Figure 14, with hard mask layer 305 as masterplate, continues etching, at polysilicon
Layer 304 is formed polysilicon gate；Concrete, can be, but not limited to using plasma dry etching,
Polysilicon layer 304 is performed etching, finally in polysilicon layer 304, etches polysilicon gate.
It should be noted that during the actual process of etches polycrystalline silicon layer 304, hard mask layer 305
Bigger with the etching selection of polysilicon layer 304, while etches polycrystalline silicon layer 303, hard mask layer
305 are also gradually etched away, and after etching polysilicon gate, hard mask layer 305 is carved the most therewith
Etching off removes；
It addition, during etching, it is possible to the part on the surface of oxide layer 303 can be etched away,
Or can use but be not limited to photoetching method and oxide layer 303 is removed, due in this method, although profit
The thickness of the grid oxide layer 302 of active area is added to a certain extent by oxide layer 303, but, polycrystalline
The oxide layer 303 in silicon gate region is removed, and that is to say, the grid oxide layer 302 of polysilicon gate region
Thickness do not increase, the most do not affect the electrical of final products, so, to oxide layer in step S05
The removal of 303 is not required, and this is not used in restriction the scope of the present invention.
To sum up, the method improving polycrystalline silicon gate grid etching process stability of the present invention, by routine
On the basis of etching technics, before growing polycrystalline silicon layer, redeposited layer of oxide layer, profit on grid oxide layer
Improve the thickness of grid oxide layer by this oxide layer, then use photoetching process, remove polysilicon gate region
Oxide layer portion, retain other parts oxide layer, so, during etches polycrystalline silicon gate,
Owing to adding layer of oxide layer, it is to avoid the etching selection ratio of polysilicon gate and grid oxide layer causes not
The impaired phenomenon of active area, simultaneously as the oxide layer of polysilicon gate region is removed, increase by one
Layer oxide layer can not have influence on the product electrical requirements to grid oxide layer, not only overcomes etching selection ratio not
Enough big problems, and the polysilicon gate pattern after etching does not changes, such that it is able to carry out more
The regulation of many polysilicon gate patterns, improves the electrical property of etching technics stability and product.
The above-described embodiments of the invention that are only, described embodiment also is not used to limit the special of the present invention
Profit protection domain, the equivalent structure change that the specification of the most every utilization present invention and accompanying drawing content are made,
In like manner should be included in protection scope of the present invention.
Claims (9)
1. the method improving polycrystalline silicon gate grid etching process stability, it is characterised in that including:
Step S01 a: Semiconductor substrate is provided, forms grid oxide layer on the semiconductor substrate；
Step S02: form layer of oxide layer on described grid oxide layer；
Step S03: coat a layer photoetching glue in described oxide layer, etched, by described polysilicon gate
The described oxide layer in territory, polar region is removed, and removes described photoresist；
Step S04: growing polycrystalline silicon layer on the semiconductor substrate；
Step S05: through photoetching and etching, forms described polysilicon gate in described polysilicon layer；
Wherein, the forming method of described oxide layer, including:
Step S21: measure described polysilicon layer etch rate and described oxide layer etch rate respectively；
Step S22: set described polysilicon layer thicknesses, calculates the thickness of described oxide layer, described meter
Calculating the formula used is: d=a/b*c, and wherein, a is for setting polysilicon layer thicknesses, and b is that polysilicon layer is carved
Erosion speed, c is oxide layer etch rate, and d is the thickness of oxide layer；
Step S23: form certain thickness described oxide layer on described grid oxide layer.
Method the most according to claim 1, it is characterised in that described photoresist is negative photoresist.
Method the most according to claim 1, it is characterised in that described polysilicon gate region is positioned at
The active region of described Semiconductor substrate.
Method the most according to claim 1, it is characterised in that the material of described oxide layer is oxidation
Silicon.
Method the most according to claim 1, it is characterised in that use chemical vapour deposition technique to be formed
Described oxide layer.
Method the most according to claim 1, it is characterised in that in described step S05, including:
Step S51: sequentially form hard mask layer and anti-reflection layer on described polysilicon layer；
Step S52: use photoetching process, be sequentially etched described anti-reflection layer and hard mask layer；
Step S53: with described hard mask layer as masterplate, continues etching, is formed in described polysilicon layer
Described polysilicon gate.
Method the most according to claim 6, it is characterised in that the material of described hard mask layer is nitrogen
SiClx.
Method the most according to claim 1, it is characterised in that containing N in described Semiconductor substrate
Type active area and p-type active area.
Method the most according to claim 1, it is characterised in that in described Semiconductor substrate and in institute
State and below grid oxide layer, include fleet plough groove isolation structure.
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5960289A (en) * | 1998-06-22 | 1999-09-28 | Motorola, Inc. | Method for making a dual-thickness gate oxide layer using a nitride/oxide composite region |
| US6083815A (en) * | 1998-04-27 | 2000-07-04 | Taiwan Semiconductor Manufacturing Company | Method of gate etching with thin gate oxide |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6083815A (en) * | 1998-04-27 | 2000-07-04 | Taiwan Semiconductor Manufacturing Company | Method of gate etching with thin gate oxide |
| US5960289A (en) * | 1998-06-22 | 1999-09-28 | Motorola, Inc. | Method for making a dual-thickness gate oxide layer using a nitride/oxide composite region |
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