CN103354951A - 互连结构 - Google Patents

互连结构 Download PDF

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Publication number
CN103354951A
CN103354951A CN2011800672234A CN201180067223A CN103354951A CN 103354951 A CN103354951 A CN 103354951A CN 2011800672234 A CN2011800672234 A CN 2011800672234A CN 201180067223 A CN201180067223 A CN 201180067223A CN 103354951 A CN103354951 A CN 103354951A
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China
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substrate
working face
conductive
dielectric materials
conductive prominence
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CN2011800672234A
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CN103354951B (zh
Inventor
德巴布拉塔·吉普塔
桥本夕纪夫
伊利亚斯·默罕默德
劳拉·米尔卡瑞米
拉杰什·卡特卡
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Adeia Semiconductor Solutions LLC
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Tessera LLC
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Abstract

微电子元件(10)包括第一表面(22)和第一薄导电元件(52)，第一薄导电元件(52)在第一表面(22)暴露且具有由第一区域和第二区域组成的工作面(54)。具有与工作面(54)的第一区域连接并覆盖该区域的基底(58)的第一导电突起(56)延伸至远离基底的端部(62)。第一介电材料层(40)覆盖第一薄元件(52)的第二区域，并至少与第一导电突起(56)的基底(58)接触。组件(10)进一步包括第二基板(18)，第二基板具有第二工作面(24)和从第二工作面(24)向外延伸的第二导电突起(76)。第一易熔金属块(70)使第一突起(56)与第二突起(76)连接，并沿第一突起(56)的边缘朝第一介电材料层(40)延伸。

Description

互连结构
相关申请的交叉引用
本申请要求申请号为12/965192、申请日为2010年12月10日的申请日之利益，其公开的内容以引用的方式并入本文。
背景技术
本申请涉及封装微电子组件内采用的互连结构。特别地，其涉及在如倒装芯片结合中微电子芯片及裸片与基板的连接、或如形成堆叠封装时基板之间的连接中采用的互连结构。本文描述的结构可用于减少互连结合的失效，这种失效归因于具有在先技术结构的元器件之间发生电迁移而导致空穴的形成。
电迁移是互连失效的主要诱因，尤其是在互连内电流密度及器件工作温度都高的高性能器件内。总的来说，电迁移由于互连组件内采用的各材料的扩散速率不同而导致。例如，互连组件可包括，在两个基板中每个上都形成的由铜制成的接触垫，及在接触垫之间结合的焊料块。焊料与两个接触垫机械固定，因此，其上形成有接触垫的基板也与两个垫电连接，使得电流承载的信号能通过焊料块在两个垫之间传递。在这个示例中，焊料与铜垫之间的扩散速率可能是不同的。扩散速率为，长时间工作尤其是在承受电流或器件工作导致的热量时，金属结构内分子移动的速率。
互连结构内形成的空穴可降低采用这种互连结构的微电子组件的可靠性。另外，在空穴周围区域内，空穴的存在增加了材料内的电流密度。而这进一步使扩散速率的差异增加，导致空穴加速形成，最终导致互连元件的电失效及机械失效。
目前用于降低电迁移的方式包括，在焊料内应用阻挡金属或掺杂剂。但是，这些方式存在自身可靠性的问题，而且导致成本的增加可能大于它们的效果。因此，需要另外的方法来降低电迁移。
发明内容
本发明实施例涉及微电子组件。微电子组件包括第一表面，及在第一表面暴露、且具有由第一区域和第二区域组成的工作面的第一薄导电元件。具有基底与工作面的第一区域连接并覆盖该区域的第一导电突起，延伸至远离基底的端部。第一介电材料层覆盖第一薄元件的第二区域，并至少与第一导电突起的基底接触。组件进一步包括，具有第二工作面和远离第二工作面而延伸的第二导电突起的第二基板。第一易熔金属块使第一突起与第二突起连接，使得第一工作面的第一表面面向第二表面。第一块沿第一突起的边缘朝第一介电材料层延伸。在另一实施例中，第一易熔金属块可与第一介电材料层接触。
微电子组件可构造为，使得第一表面形成在基板上，而第二表面形成在微电子元件上。附加地或替代地，第一表面可在进一步具有微电子元件附接于其上的基板上形成，而第二表面可在第二基板上形成。在另一实施例中，微电子组件包括复数个互连结构，每个都包括，第一导电元件、第一导电突起、第二导电突起和第一金属块。每个互连结构在第一工作面面的第一区域与第二工作面之间连接，且具有与上述类似的结构，其中第一介电材料层覆盖薄元件的第二区域。
第一介电材料层内的第一开口可限定内表面，使得内表面沿第一突起的一部分延伸，并基本与其接触。相应地，第一介电材料层可具有沿垂直于第一薄元件的第一工作面的方向延伸的厚度。该厚度可为第一导电突起高度的约20%至50%。
第一导电突起的基底可具有外周，使得第一工作面的第二区域在第一突起基底的外周之外暴露。这种布置可进一步在第一薄元件的第一工作面与第一导电元件侧壁之间形成拐角。拐角可沿第一导电元件基底的外周设置，且第一介电材料层可基本覆盖该拐角。
在另一实施例中，第二薄导电元件可在第二表面暴露，且可具有由第一区域和第二区域组成的第二工作面。第二突起可进一步具有与第二薄元件的第一区域连接、并覆盖该区域且限定外周的基底，及远离基底的端头部分。第二介电材料层可覆盖第二薄元件的第二区域。另外，第一块可在第二导电突起的一部分上朝第二介电材料层延伸。
本发明的另一实施例涉及微电子组件，包括第一表面及在第一表面暴露且具有由第一区域和第二区域组成的工作面的第一薄导电元件。第一导电突起与第一工作面的第一区域连接并覆盖该区域，并延伸至远离该区域的端部。导电突起具有沿其一部分形成的屏障，屏障具有远离第一薄导电元件的第一边缘。组件进一步包括第二工作面，第二导电突起远离第二工作面而延伸。第一易熔金属块使第一导电突起与第二导电突起连接，使得第一工作面的第一表面面向第二基板的第二表面。第一块沿第一导电突起的一部分延伸至朝向屏障第一边缘的位置，屏障位于第一薄元件与第一金属块之间。屏障可为形成在第一导电突起内的表面处理层。表面处理层可通过氧化而形成、或可为施加至第一导电突起表面上的涂层。
在又一实施例中，微电子组件包括具有第一表面和第一薄导电元件的第一基板，第一薄导电元件在第一表面暴露且具有第一工作面。具有基底与第一工作面连接的第一导电突起，延伸至远离第一工作面的端部，并在基底与端部之间限定侧壁。介电材料层沿第一基板的第一表面延伸，且具有第二表面及远离第二表面的第三表面。介电材料层进一步具有形成在其内并限定外周的第一开口。金属镀层具有沿第一导电突起的端部及侧壁的至少一部分延伸的第一部分。金属镀层的第二部分沿介电材料层的一部分向外延伸，并远离第一导电突起。第一焊料块至少在镀层的第一部分上形成，并朝第三表面延伸。
又一实施例涉及的微电子组件包括基板，基板具有第一表面、在第一表面暴露并限定工作面的复数个第一导电垫、及复数个第一金属柱。每个金属柱限定具有外周的基底，并与相应的一个第一导电垫连接。每个金属柱沿侧壁从基底延伸至远离第一导电垫的端部。组件进一步包括具有内表面、外表面及复数个开口的介电材料层。内表面沿基板的第一表面延伸，外表面远离基板。各第一金属柱贯穿开口而突出，使得介电材料层至少与第一金属柱的外周接触。复数个易熔金属块与至少一些第一金属柱的端部接触，并沿第一金属柱的侧壁朝介电材料层的外表面延伸。微电子元件承载在基板上，并至少与一些第一导电垫电连接。
又一实施例涉及的微电子组件包括第一基板，第一基板具有第一表面及具有第一工作面且在第一表面暴露的第一薄导电元件。第一导电突起具有与第一工作面连接的基底，并延伸至远离第一工作面的端部。侧壁在基底与端部之间限定。组件进一步包括，具有第二表面及远离第二表面的第三表面的介电材料层。第二表面沿第一基板的第一表面延伸，介电材料层内形成有具有周壁的第一开口。第一焊料块在第一导电突起上形成，并沿端部和侧壁的一部分延伸至位于基底与端部之间的位置。第一导电突起贯穿第一开口而延伸，使得开口的周壁与侧壁的一部分接触。焊料块朝介电材料层的第三表面延伸。
附图说明
图1示出了包括根据本发明实施例互连结构的封装微电子元件的堆叠组件。
图2示出了包括根据本发明另一实施例互连结构的封装微电子元件的堆叠组件。
图3示出了说明根据图1实施例互连结构在第一条件下的特性的图表。
图4示出了说明根据图1实施例互连结构在第二条件下的特性的图表。
图5示出了说明在先技术互连结构在第一条件下的特性的图表。
图6示出了说明图5中在先技术互连结构在第二条件下的特性的图表。
图7示出了根据替代实施例互连结构的元器件。
图8示出了根据另一替代实施例互连结构的元器件。
图9示出了根据替代实施例互连结构的元器件。
图10示出了根据另一变例互连结构的元器件。
图11示出了包括沉积金属层的互连结构的元器件。
具体实施方式
现在参照附图，其中相同的标号用于相同的特征，图1和图2示出了微电子子组件12、14的堆叠封装10。通过包括将进一步详述的元器件的一个或多个互连结构50，微电子子组件相互电接合及机械接合在一起。
图1中堆叠封装10包括下组件12和上组件14。需要指出的是，本文中应用的，术语上和下，及指示方向或位置的任意其他术语，如水平或竖直、左或右、及其他，是参照附图和使用时的示例性模式的。本说明书中的这些术语是为了清楚的目的而采用，并不是限制，对于本领域普通技术人员来说，其他位置和方向是可以理解的。下基板16和上基板18中每个具有各自的下表面20、24和上表面22、26。上表面22、26通常平行于它们各自的下表面20、24，且所有表面20、22、24、26通常都是平坦的。上基板14和下基板12中每个的厚度在各自的上表面22、26与下表面20、24之间限定。上基板14和下基板12的厚度可大致相等，或可不同。厚度通常小于基板12、14的长度和宽度，条件是足以使基板12、14大致为薄的、晶圆状的结构，并落入本领域普通技术人员通常理解的范围内。
每个组件12、14还包括各自的微电子元件30、32。所示的微电子元件30以倒装芯片结合的方式附接至下基板16，其中微电子元件30反转，使得其导电触点（未示出）面向上表面22。然后,微电子元件利用从其触点延伸的导电突起34固定至基板16，并利用焊料块36或另一导电结合材料与形成在基板16上的第二导电突起38结合。用于使微电子元件30与基板16连接的其他可能布置包括面朝上安装，其中微电子元件30的触点背对上表面26，采用粘接剂使微电子元件30与上表面26结合在一起，导线引线用于使微电子元件30的触点与形成于基板16上的如迹线或垫等的导电特征电连接。所示的微电子元件32以类似方式固定在基板18上，且可选择如上所述之一的附接方式。
图1所示的互连结构50包括的导电垫52，具有在基板16上表面22暴露的工作面54。本文中应用的术语“暴露”，不是指垫52以任何特定方式附接在基板16上、或二者之间的任何相对位置。而是指，导电结构可与一理论点接触，该理论点沿垂直于介电结构表面的方向，从介电结构外部向该介电结构的表面移动。因此，暴露在介电结构表面上的端子或其他导电结构，可从该表面突出；可与该表面平齐；或可相对该表面凹陷，并通过介电元件上的孔或凹坑暴露。通过直接在表面22上沉积或类似过程形成垫，垫52可而附接至基板16，或垫52可嵌入基板16内，使得工作面54与表面22平齐、或位于表面22上方或下方的一高度，只要工作面54保持在表面22上暴露即可。在替代实施例中，互连结构50可包括导电迹线或导电迹线的一部分，用于补充或替代导电垫52。
导电柱56形成在导电垫52工作面54的一部分上。从图1可以看出，柱56的基底58覆盖工作面54的一部分，并使工作面的另一部分从基底58的外周延伸，并在表面22暴露。柱56还限定从柱56的基底58延伸至端部62的边缘表面60。如本领域普通技术人员可以理解的一样，尽管图1示出的为导电柱，但可采用形成导电突起的替代结构，包括引脚、突柱或类似物。
互连结构50进一步包括，具有在基板18下表面24暴露的工作面66的导电垫64。与接触垫52一样，垫64可嵌入基板18内，使得工作面66与下表面24平齐，或位于下表面24的上方或下方，只要工作面66保持在表面24暴露即可。利用贯穿基板18而形成的导电通路68，垫64可与形成在基板18上表面26上的如迹线或导线等导电特征连接。在替代实施例中，互连结构50可包括，在下表面24暴露的取代垫64的迹线或迹线的一部分。
焊料块70用于使柱56与垫64机械结合和电结合。在封装10的形成与组装过程中，焊料块70可首先在柱56上或垫64上形成，然后当组件12、14对齐排列在一起后回流，以使焊料块70与柱56或垫64中的另一个固定。一旦置入封装10内后，焊料块70就形成了上边缘72和下边缘74。上边缘72和下边缘74中每个都可形成为单个的线或点或面。如图1所示，上边缘72为沿围绕垫64的表面24的一部分延伸的表面。上边缘72还可形成为与垫64接触的表面，或为环绕垫的圆，或者与表面24接触、或者远离，根据垫64的几何形状而定。
本文公开的结构和技术可有助于减少垫和与垫连接的焊料块之间的界面处的电迁移。电迁移可引起在相互接触的区域，两个或更多金属元件呈现出不同扩散速率的问题。在这种情况下，在结合界面内可能产生空穴。也就是说，一种金属会脱离另一种金属，形成其间的间隙或开口。
与焊料块连接两个相面对的垫的结构相比，互连结构50内的柱56或另一导电突起的应用，沿电流通过的路线，减小了柱56的端部62与垫64之间的距离。相应地，其中柱56和垫64都由铜制成时，在铜-焊料-铜的互连结构内，图1的结构可显示出有效地减少了导致空穴产生的电迁移。当在电互连结构内应用的同类金属（like metal）被第二金属分隔开时，金属间化合物（ inter-metallic compound），及同类金属，在第二金属内形成。这种金属间化合物将从一个同类金属结构朝另一同类金属结构延伸。金属间化合物的形成是减少由于电迁移而使空穴形成的因素，因为金属间化合物具有比焊料低的电迁移率。通过减小结构内同类金属与同类金属之间的距离，可形成从一个同类金属结构延伸至另一同类金属结构的金属间化合物。在图1的示例中，其中垫64和柱56由铜制成，而焊料块70包括锡，金属间化合物的比例可变化，例如从Cu3Sn变为Cu3Sn5。另外，本文所示的互连结构可降低同类金属在整个互连结构内的浓度梯度，这示为减少电迁移的主要因素。结构内的浓度梯度是指浓度变化的速度，例如结构内同类金属浓度随空间变化的速度。柱56延伸至焊料块70内，使结构内铜的表面积增加，其进一步使焊料块70内的金属间化合物增加。金属间化合物的这种增量的扩展能降低结构内铜的变化速度，进一步降低电迁移。
图3至图6所示的图表说明了上述的现象。图3和图4示出在一水平位置处，与图1类似的互连结构在其整个竖直距离内铜浓度的变化。所示的图表对应于互连结构50，其中垫52、64和柱56由铜制成，而焊料块70由包含锡的焊料化合物制成。图3示出当结构在温度（T0）且没有电流通过时出现的铜浓度，表明这种温度条件下，焊料块70内没有铜。图4示出相同结构在存在电流的平衡温度下，整个结构内的铜浓度。图4中的图表示出焊料块70内存在铜浓度，其存在是由于金属间化合物的形成。示出的金属间化合物从柱56的端部62延伸至垫52的工作面54。铜浓度既沿端部62又沿工作面54延伸，也表明沿其基本没有空穴形成。另外，图4中的图表示出，柱56的存在可降低整个互连结构50内铜浓度变化的速度。例如，在紧邻近垫64的焊料块70内的区域，代表铜浓度的曲线的方向急剧变化。相反地，在邻近柱56的焊料块70内的区域，代表铜浓度的曲线的方向变化缓和得多。需要指出的是，图表仅为示例性的，用于解释本文描述的工作情况，并不是按比例或准确表示图中所示特定结构的工作情况。
图5和图6所示的图表示出，焊料块170位于两个接触垫152、162之间的在先技术互连结构的铜浓度，其中垫152、164之间的距离190与图3和图4中垫52、64之间的距离90基本相同。图5示出在T0温度时结构内的铜浓度，表明在这种条件下焊料块170内没有铜存在。图6示出在平衡温度下结构内的铜浓度，示出由于金属间化合物的形成，焊料块170内具有一些铜浓度，但该浓度没有贯穿焊料块170而延伸。这导致断开处形成空穴186。
相应地，在柱56具有的端部62延伸至焊料块70内、并朝焊料块另一侧的如垫64等同类金属的结构延伸时，柱的存在可减小由于电迁移形成空穴的可能性。在结构内穿过总距离90而延伸的距离，大于金属间化合物预期延伸的距离时，这尤其是正确的。在柱56和垫64由铜制成且焊料块70包括锡的实施例中，端部62与工作面66之间的距离92可为距离90的约10%至50%。需要指出的是，在图3中，距离90在基板18的下表面24与介电层40的外表面之间限定，距离90在围绕垫52、64的任意类型的结构的主表面之间限定。
在一个实施例中，下边缘74形成围绕柱56的边缘表面60的一部分的圆形线或环形表面，柱延伸至焊料块70内。另外，下边缘74与垫52分隔开，使得焊料块70与垫52的任意部分都不直接接触，包括围绕柱56的基底58而仍暴露的部分。可对柱56、尤其是对邻近基底58的边缘表面60进行处理，可防止焊料块70浸润边缘表面60并与工作面54或垫52接触。这种处理可包括氧化或类似的过程。类似地，可围绕边缘表面60施加抵抗焊料流动的材料层。
在另一实施例中，通过在工作面54上延伸并与边缘表面68邻近基底58的至少一部分接触的介电层40，焊料块70的下边缘74保持为远离垫52的工作面54。在这个实施例中，允许焊料块70流动至与介电层40接触，包括表面42，使得下边缘74可以与垫52间隔开的位置关系沿表面延伸。
通过使焊料块70远离垫52，由于电迁移形成空穴的可能性也可降低。这种类型的互连结构，通过降低焊料块70内的电流集聚而减少电迁移。如图7和图8所示，经过互连结构50的电流对角地沿线移动，从结构一端上的点移动至结构另一端与初始点基本横向相对的另一点。这表明电流从图7中的垫252沿线296所表示的路线移动，经过焊料块270返回至柱256内。然后电流离开柱256，在到达垫264之前，再次进入焊料块270内。这种路线导致在邻近柱256基底258的焊料块270的部分内电流集聚。电流集聚是继电迁移之后可导致空穴形成的另一主要因素，空穴形成导致互连失效。
如图8所示，通过在焊料块70的下边缘74与暴露垫52之间插入介电层40，在垫52外没有电流经过。而是，电流将沿只进入焊料块70内一次的线96移动，示出为在端部与焊料块70的界面处进入。这可以大约为1.25至1.75之间的系数降低电流聚集的梯度，其可再次降低空穴形成的可能性。只要焊料块70通过介电层40保持为远离垫52，类似路径可在焊料块沿介电层40的一部分向外延伸的结构内发现。
图1所示的介电层40为沿基板16上表面22的主要部分延伸的。这个部分包括没有被其他接触元件穿过的所有上表面22。替代地，介电层40可在环绕互连结构50内应用的所有柱56的部分内形成，并向外延伸至足以使焊料块70保持远离相关接触垫52的距离。在这种实施例中，介电层部分可与接触垫的大小和形状基本相同，或稍大，从而可靠地覆盖垫的任何另外暴露的部分。
在实施例中，在覆盖垫52的区域，介电层40可具有厚度42，使得焊料块70的下端74保持与垫间隔开一距离。这个距离可包括材料总厚度中所有容差的补偿，以确保没有导致垫52的工作面54非预期暴露的孔或间隙存在。厚度42可为约10微米至30微米之间。在这种实施例中，介电层40将具有一个孔44或复数个孔44，任意互连柱56穿过孔延伸。孔44形成有内表面46，与从基底58向上延伸的边缘表面60的一部分接触。
如图11所示，镀层488可在柱456上施加，包括端部462和暴露在介电层440上方的边缘表面460的一部分。镀层488可有助于保证柱456与焊料块470之间的可靠互连。
图2示出包括具有互连结构50的复数个微电子子组件12、14的堆叠组件10。除了图2中封装10内的互连结构50包括从垫64的工作面66延伸的导电柱76以外，图2所示的封装10与图1所示的基本类似。柱包括附接在工作面66上的基底78，及延伸至远离工作面66的端部82的边缘表面80。第二介电层41可沿基板18的下表面24而形成，并覆盖工作面66和暴露在基底78外周之外的垫64的任何部分。与介电层40类似，介电层41保持焊料块70的上边缘72远离接触垫64，以减少邻近上表面72处的焊料块70内的电流聚集。这进一步降低互连结构50内形成空穴的可能性，如参照介电层40在上文所述。
图9和图10说明，通过保持焊料块不与相关导电垫接触，致使包含在互连结构内的焊料块内的电流聚集降低。图9示出的互连结构350包括垫352及在垫上形成的柱356。焊料块370使柱356及垫552与上部垫364及在垫上形成的柱376附接。由线396表示的电流，从触点垫352流出而进入焊料块370内，然后返回至柱356内，然后又返回焊料块370内。然后电流（线396）在返回焊料块370之前，进入柱376内，最后进入垫364内。这种电流路线396致使在焊料块370上边缘372和下边缘374的区域内，电流聚集增加。如图10所示，介电层40、41的存在防止电流（线96）穿过邻近其上边缘72和下边缘74的焊料块70区域，以约为1.25至1.75之间的系数，降低每个区域内的电流聚集梯度。这可致使由于在焊料块70每个端部的界面内形成空穴而互连失效的可能性降低。
另外，组件14内的柱76的存在，可进一步减小互连结构70内同类金属与同类金属之间的距离，如参照图1在上文所述。在图2的结构内，这个距离由端对端的距离94来表示。当距离94为距离90的大约10%至30%之间时，距离94可致使从端部62延伸至端部82的金属间化合物的形成。替代地，柱76可为任意导电突起，如突柱、引脚或类似物。通过在两个组件12、14内都包括导电突起，获得产生可靠的金属间化合物的连接、同时在相邻互连结构50之间获得比如图1所示采用柱至垫的布置中可能的间距更小的间距是可能的，同时可具有更大的总距离90。另外，与简单地使焊料块70形成在垫64上相比，通过在垫64上形成介电层41，更低的电流聚集是可能的。通过在互连结构50内包括柱76，浓度梯度对电迁移的影响也可进一步降低。在这种结构内，互连结构50中柱56的区域内铜浓度变化速度的降低，也可在柱76的区域内获得，从而在焊料块70的两个端部都没有铜浓度的急剧变化。
图1和图2所示的包括介电层40、41及其相关结构的互连结构50，可在其他连接类型中采用，不限于图1和图2所示的堆叠子组件布置。例如，它们可在倒装芯片结合（如图1和图2中所示的微电子元件30与基板16之间的结合）中采用，及在与微电子子组件（如微电子子组件12）与另一基板以面向上或者以倒装芯片的结合方式的连接中采用。另外，在基板18的上表面26上，组件（如组件14）可进一步包括具有形成于其上的柱和介电层的附加触点垫，以与柱56和介电层40相同的方式，与另一微电子组件采用如图1和图2所示的互连结构连接。这种布置可继续，以在堆叠封装内附接另外的组件。
尽管本发明参照特定实施例进行描述，可以理解的是，这些实施例只是说明本发明的原理和应用。因此，应理解为，在不偏离由附加的权利要求书所限定的本发明实质和范围的情况下，说明的实施例可做出许多修改及可设计出其他布置。

Claims (30)

1. 微电子组件，包括：
第一表面；
第一薄导电元件，在所述第一表面暴露，并具有包含第一区域和第二区域的工作面；
第一导电突起，具有与所述工作面的第一区域连接并覆盖该区域的基底，且延伸至远离所述基底的端部；
第一介电材料层，覆盖所述第一薄元件的第二区域，并至少与所述第一导电突起的基底接触；及
第二基板，具有第二工作面和远离所述第二工作面而延伸的第二导电突起；及
第一易熔金属块，使所述第一突起与所述第二突起连接，使得所述第一工作面的第一表面面向所述第二表面，其中所述第一块沿所述第一突起的边缘朝所述第一介电材料层延伸。
2. 根据权利要求1所述的微电子组件，其中所述第一表面形成在基板上，且其中所述第二表面形成在微电子元件上。
3. 根据权利要求1所述的微电子组件，其中所述第一表面形成在进一步具有附接于其上的微电子元件的基板上，且其中所述第二表面形成在第二基板上。
4. 根据权利要求1所述的微电子组件，其中所述第一易熔金属块与所述第一介电材料层接触。
5. 根据权利要求1所述的微电子组件，其中所述第一介电材料覆盖所述第一表面的至少一部分。
6. 根据权利要求1所述的微电子组件，其中所述第二导电突起包括远离所述第二表面的端部，且其中所述第一导电突起的端部与所述第二导电突起的端部间隔开第一距离，并在其间限定间隙，且其中所述金属块在所述间隙内延伸。
7. 根据权利要求6所述的微电子组件，其中所述第一距离在10微米至30微米之间。
8. 根据权利要求1所述的微电子组件，进一步包括在所述第一表面暴露的复数个薄导电元件、复数个第一导电突起和复数个第二导电突起，每个薄导电元件都具有包括第一区域和第二区域的工作面，每个第一导电突起都与所述复数个薄元件中相应的一个的第一工作面的第一区域连接，并延伸至远离其的端部，每个第二导电突起远离第二工作面而延伸；
其中所述第一介电材料层覆盖所述薄元件的第二区域，复数个第一易熔金属块使所述第一突起中相应的一个与所述第二突起中相应的一个连接，其中相应的第一块在相应的第一突起的一部分上朝所述第一介电层延伸。
9. 根据权利要求1所述的微电子组件，其中所述第一介电材料层内的第一开口限定内表面，且其中所述内表面沿所述第一突起的一部分延伸，并与其基本接触。
10. 根据权利要求9所述的微电子组件，其中所述第一介电材料层具有沿垂直于所述第一薄元件的第一工作面的方向延伸的厚度，且其中所述厚度在约10微米至30微米之间。
11. 根据权利要求9所述的微电子组件，其中所述第一介电材料层具有沿垂直于所述第一薄元件的第一工作面的方向延伸的厚度，且其中所述厚度为所述第一导电突起的高度的约20%至50%。
12. 根据权利要求1所述的微电子组件，其中所述第一导电突起的基底具有外周，其中所述第一工作面的第二区域在所述第一突起的基底的外周之外暴露。
13. 根据权利要求12所述的微电子组件，其中所述第一突起限定侧壁，所述侧壁沿其横截面轮廓基本为笔直的。
14. 根据权利要求13所述的微电子组件，其中在所述第一薄元件的第一工作面与所述第一导电元件的侧壁之间形成拐角，所述拐角沿所述第一导电元件的基底的外周设置，且其中所述第一介电材料层基本覆盖所述拐角。
15. 根据权利要求12所述的微电子组件，其中所述第一导电突起的基底包括从所述端部延伸的基本笔直部分及从所述基底的外周延伸的过渡部分，所述过渡部分沿其横截面轮廓基本为拱形， 且其中所述第一介电材料层基本覆盖所述过渡部分。
16. 根据权利要求12所述的微电子组件，其中所述第一导电突起的基底与所述第一薄元件通过导电金属层而连接，所述导电金属层具有与所述第一导电突起的基底的外周基本对齐的外表面，且其中所述第一介电材料层基本覆盖所述导电金属层的外表面。
17. 根据权利要求1所述的微电子组件，进一步包括：
第二薄导电元件，在所述第二表面暴露，且具有由第一区域和第二区域组成的第二工作面，且其中所述第二突起具有限定外周、且与所述第二薄元件的第一区域连接并覆盖该区域的基底，及远离所述基底的端部；
第二介电材料层，覆盖所述第二薄元件的第二区域。
18. 根据权利要求要求17所述的微电子组件，其中所述第一块在所述第二导电突起的一部分上朝所述第二介电材料层延伸。
19. 根据权利要求1所述的微电子组件，其中所述第一导电突起限定侧壁，且其中沉积金属层形成在所述第一导电突起的端部及其所述侧壁的至少一部分上。
20. 根据权利要求19所述的微电子组件，其中所述第一介电材料层包括与所述第一表面基本平行的外表面，所述镀层进一步形成为，其一部分沿所述外表面并远离所述第一导电突起向外延伸。
21. 根据权利要求1所述的微电子组件，其中所述薄元件为基本圆形的垫。
22. 根据权利要求21所述的微电子组件，其中所述第一子组件进一步包括形成在所述第一基板上并从所述垫延伸的导电迹线。
23. 微电子组件，包括：
第一表面；
第一薄导电元件，在所述第一表面暴露，且具有由第一区域和第二区域组成的工作面；
第一导电突起，与所述第一工作面的第一区域连接并覆盖该区域，且延伸至远离该区域的端部，并具有沿其一部分而形成的屏障，所述屏障具有远离所述第一薄导电元件的第一边缘；
第二工作面，具有从其向外延伸的第二导电突起；及
第一易熔金属块，使所述第一导电突起与所述第二导电突起连接，使得所述第一工作面的第一表面面向所述第二基板的第二表面，其中所述第一块沿所述第一导电突起的一部分延伸至朝所述屏障的第一边缘的位置，所述屏障位于所述第一薄元件与所述第一金属块之间。
24. 根据权利要求23所述的微电子组件，其中所述屏障为形成在所述第一导电突起上的表面处理层。
25. 根据权利要求24所述的微电子组件，其中所述表面处理层通过氧化而形成。
26. 根据权利要求24所述的微电子组件，其中所述表面处理层为施加在所述第一导电突起的表面上的涂层。
27. 根据权利要求23所述的微电子组件，其中所述屏障为介电材料层。
28. 根据权利要求27所述的微电子组件，其中所述介电材料层覆盖所述第一薄元件的第二区域。
29. 微电子组件，包括：
第一子组件，包括：
第一基板，具有第一表面；
复数个第一导电垫，每个都具有在所述第一表面暴露的第一工作面；
复数个第一突起，每个都限定具有外周并与所述第一垫中相应的一个连接的基底，所述第一突起远离相应的第一垫而延伸，其中所述第一工作面的暴露部分在所述第一突起的基底的外周之外限定；及
第一介电材料层，覆盖所述第一垫的工作面的暴露部分，并限定复数个开口，所述第一突起中相应的一个穿过所述开口，所述第一介电材料层至少与所述第一突起的外周接触，并限定第一外表面；
第二子组件，包括第二基板，所述第二基板具有第二表面、在所述第二表面暴露的复数个第二导电垫以及复数个第二突起，每个第二突起都具有与所述第二垫中相应的一个连接的基底，并从所述基底延伸；及
复数个易熔金属块，分别使所述复数个第一连接元件与所述复数个第二连接元件中相应的一个接合，使得所述第二基板的第二工作面面向所述第一基板的第一工作面，其中所述易熔金属块覆盖延伸至所述第一介电材料层的第一外表面的所述第一突起的至少一部分。
30. 微电子组件，包括：
第一基板，具有第一表面；
第一薄导电元件，在所述第一表面暴露，且具有第一工作面；
第一导电突起，具有与所述第一工作面连接的基底，并延伸至远离所述第一工作面的端部，侧壁在所述基底与所述端部之间限定；
介电材料层，具有第二表面和远离所述第二表面的第三表面，所述第二表面沿所述第一基板的第一表面延伸，所述介电材料层具有第一开口，其限定了形成于其内的周壁；
金属镀层，具有沿所述第一导电突起的端部及至少一部分的侧壁延伸的第一部分，及沿所述介电材料层一部分并远离所述第一导电突起向外延伸的第二部分；及
第一焊料块，至少在所述镀层的第一部分上形成，并朝所述第三表面延伸。
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