CN103368546A - Analog switch which starts after power failure and relevant method - Google Patents
Analog switch which starts after power failure and relevant method Download PDFInfo
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- CN103368546A CN103368546A CN2012100999740A CN201210099974A CN103368546A CN 103368546 A CN103368546 A CN 103368546A CN 2012100999740 A CN2012100999740 A CN 2012100999740A CN 201210099974 A CN201210099974 A CN 201210099974A CN 103368546 A CN103368546 A CN 103368546A
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Abstract
The invention relates to an analog switch which starts after a power failure and a relevant method. Apart from other contents, this article discusses a device and method that transmits a signal in the state of the power failure. An example of a switch device can comprises a first depletion type transistor, a control circuit and a tracking circuit. The first depletion type transistor is configured in a way that an analog signal is transmitted between a first node and a second node in a first state, and the first node is isolated from the second node in a second state. The control circuit is connected with the control node of the first depletion type transistor and is configured in the way that the control node is isolated form a first power supply input end in the first state, and the control node is connected with the first power supply input end in the second state. The tracking circuit is configured in the way that the control node of the first depletion type transistor is connected with the first node during the first state, and the control node of the first depletion type transistor is isolated from the first node in the second state.
Description
Technical field
This theme relates to switch, and more specifically, relates to the analog switch for transmission of signal during off-position.
Background technology
A lot of analog switches need to provide power supply to analog switch, to allow and to realize that positive grid is to source voltage (V
GS), thereby transmit the signal that swings around earth potential.During off-position, a lot of N-shaped metal-oxide semiconductor (MOS) (NMOS) analog switches do not have positive V
GS, and can not transmit the above Ground signal of electromotive force.Similarly, under power down mode, a lot of p-type metal-oxide semiconductor (MOS) (PMOS) analog switches do not have negative V
GS, and can not transmit the signal that is lower than earth potential.In addition, traditional complementary metal oxide semiconductors (CMOS) (CMOS) analog switch can allow transmission of signal, but has significant distorted signals and relatively poor quality.
Summary of the invention
Except other guide, this paper has discussed the apparatus and method that are used for transmission of signal under off-position.Exemplary switchgear can comprise: the first depletion mode transistor, described the first depletion mode transistor be configured under the first state between first node and Section Point the transfer die analog signal, and under the second state with the isolation of first node and Section Point; Control circuit, described control circuit be connected to the control node of described the first depletion mode transistor and be configured under described the first state with the isolation of described control node and the first power input and under described the second state, described control node is connected to described the first power input; And tracking circuit, described tracking circuit be configured to during described the first state the described control node of described the first depletion mode transistor is connected to described first node and under described the second state with described control node and the isolation of described first node of described the first depletion mode transistor.
Exemplary method can comprise: using the first depletion mode transistor transfer die analog signal between first node and Section Point under the first state; Under the second state, use described the first depletion mode transistor with described first node and the isolation of described Section Point; Use control circuit control node and isolation of the first power input with described the first depletion mode transistor under described the first state; Use described control circuit under described the second state, the described control node of described the first depletion mode transistor to be connected to described the first power input; Use tracking circuit under described the first state, the described control node of described the first depletion mode transistor to be connected to described first node; And use described tracking circuit under described the second state, described control node and the described first node of described the first depletion mode transistor to be isolated.
This joint aims to provide the general introduction to subject of this patent application.It is not to aim to provide explanation exclusiveness of the present invention or exhaustive.Comprise and describing in detail so that the further information about present patent application to be provided.
Description of drawings
In the accompanying drawings (these accompanying drawings not necessarily are drawn to scale), similar numeral can be described the like in the different views.Similar numeral with different letter suffix can represent the different instances of like.Accompanying drawing illustrates by way of example and unrestriced mode shows herein each embodiment that discusses substantially.
Fig. 1 shows exemplary switchgear substantially.
Fig. 2 shows substantially for the illustrative switch equipment that transmits the analog signal such as audio signal between two nodes.
Fig. 3 A and Fig. 3 B show the illustrative switch equipment for transfer die analog signal during the off-position of the device that comprises switchgear substantially.
Embodiment
Except other guide, the inventor has realized that some system and methods, these system and methods are configured to allow in the situation that does not apply power with higher quality and less distortion transmission of signal, and do not allow transmission of signal (for example, disabled switch) when applying power.In one example, switch can comprise the depletion type analog switch that is configured to transmit audio signal in the situation that does not apply power.In one example, can use 0 constant V gate source voltage (V
GS) signal enables switch, this provides best total harmonic distortion (THD) performance.When powering up, can disabled switch.In one example, this implementation can not consume any a large amount of power and comes transmission of signal.
Fig. 1 shows exemplary switchgear 100 substantially, and it comprises depletion mode transistor 101, control circuit 102 and tracking circuit 103.In some examples, control circuit 102 can comprise that being configured to reception controls voltage (V
CTL) input 104.In one example, as control voltage (V
CTL) be in or closely during electromotive force (GND), control circuit 102 can be setovered to the control node of depletion mode transistor 101, so that depletion mode transistor 101 is disabled, perhaps be under the first state, and can be between the first node (A) of switchgear 100 and Section Point (B) transmission of signal (for example, simulated audio signal).
In some examples, tracking circuit 103 can be connected to the control node of depletion mode transistor 101 one in first node or the Section Point (A, B), to keep the V that is substantially 0V of depletion mode transistor 101
GSTherefore, under the first state, depletion mode transistor 101 can have less distortion or not have in the situation of distortion transmission of signal between first node and Section Point (A, B).In some examples, switchgear 100 can receive normal power supplies voltage (V
CC), and control voltage (V
CTL) can be the output voltage of charge pump, so that when switchgear 100 is in the first state, control voltage (V
CTL) equal substantially 0V (for example, earth potential), and when switchgear 100 was in the second state, charge pump can be activated and can provide had the substantially control voltage (V of negative voltage
CTL) (for example, in some examples, be about-2V).
In some examples, as control voltage (V
CTL) when being in the first negative voltage level with respect to GND, control circuit 102 can be setovered to the control node of depletion mode transistor 101, so that depletion mode transistor 101 is disabled, thus first node (A) and Section Point (B) is electrically isolated from one.In some examples, tracking circuit 103 can be isolated the control node of depletion mode transistor 101 and in first node and the Section Point (A, B) one or two, to keep the grid of crossing over depletion mode transistor 101 and the negative voltage on the source electrode under the second state.Therefore, under the second state, depletion mode transistor 101 can be electrically isolated from one with first node and Section Point (A, B).
In some examples, switchgear 100 can comprise voltage identification 105, and voltage identification 105 is configured to provide the second reference voltage to control circuit 102.In one example, voltage identification 105 can receive a plurality of voltages, and the minimum voltage in these a plurality of voltages is provided.In one example, these a plurality of voltages can comprise control voltage (V
CTL), the voltage located of first node (A), voltage, GND or its combination that Section Point (B) is located.
Fig. 2 shows substantially for controlling voltage (V
CTL) be in or during near reference potential (for example, earth potential (GND)), between two nodes (A, B), transmit the illustrative switch equipment 200 of the analog signal such as audio signal.In some examples, switchgear 200 can comprise the first depletion mode transistor 201, control circuit 202, tracking circuit 203 and switch discriminator 205.Under the first state of switchgear 200, when the first depletion mode transistor 201 is activated (for example, at the grid of the first depletion mode transistor 201 voltage (V to source electrode
GS) be in or during near 0V), the first depletion mode transistor 201 can be between first node (A) and Section Point (B) the transfer die analog signal.
In some examples, control circuit 202 can receive control voltage (V
CTL), and use control voltage (V
CTL) voltage levvl control the control node of the first depletion mode transistor 201.In some instances, control circuit 202 can comprise pair of transistor 211, the 212 and the 3rd transistor 213 that is connected to inverter.In some examples, the 3rd transistor 213 can be configured to will control voltage (V under the first state
CTL) isolate with the control node of the first depletion mode transistor 201, enable the first depletion mode transistor 201 to allow the first depletion mode transistor 201, and under the second state, will control voltage (V
CTL) be connected to the control node, to forbid the first depletion mode transistor 201.In one example, the transistor 211,212 that is connected to inverter can comprise p-type metal-oxide semiconductor (MOS) (PMOS) enhancement transistor 211 that is connected to GND and N-shaped metal-oxide semiconductor (MOS) (NMOS) enhancement transistor 212 that is connected to voltage identification 205 via power rail (NRail).
Under the first state of switchgear 200, control voltage (V
CTL) can be in or near GND, and NMOS enhancement transistor 212 can turn-on voltage discriminator 205 and voltage identification 205 is connected to the control node of the 3rd transistor 213.Voltage identification 205 can provide the minimum voltage in two or more voltages, for example, and control voltage (V
CTL) or first node and Section Point (A, B) in voltage of occurring of one or two place in minimum voltage.The low-voltage that occurs from the control Nodes of the 3rd transistor 213 of voltage identification 205 can allow the first depletion mode transistor 201 to enable and the transfer die analog signal.
Under the second state of switchgear 200, control voltage (V
CTL) can be in the negative voltage level that is configured to forbid the first depletion mode transistor 201.V
CTLCan conducting PMOS enhancement transistor 211, and PMOS enhancement transistor 211 can be connected to GND with the 3rd transistorized control node.Because control voltage (V
CTL) be negative voltage with respect to GND, therefore the 3rd transistor 213 can be in grid (or control node) conducting when being connected to GND of the 3rd transistor 213.In case open, the 3rd transistor 213 of control circuit 202 can be connected to the control node of the first depletion mode transistor 201 negative control voltage (V
CTL), thereby allow the first depletion mode transistor 201 that first node and Section Point (A, B) is electrically isolated from one.In some examples, the 3rd transistor 213 can comprise enhancement transistor, for example, and the NMOS enhancement transistor.
In some examples, tracking circuit 203 can comprise the second depletion mode transistor 214.Under the first state of switchgear 200, the second depletion mode transistor 214 can be connected to by the control node with the first depletion mode transistor 201 first node (A) to be guaranteed to keep stable, the V of 0V substantially at the grid of the first depletion mode transistor 201 and source electrode
GSUnder the first state, the control node of the second depletion mode transistor 214 can be in or near 0V, so that the second depletion mode transistor 214 comprises conducting channel.Under the second state of switchgear 200, the control node of the second depletion mode transistor 214 can be connected to the second control voltage (V
CTL2), to forbid the second depletion mode transistor 214.In some examples, the control voltage (V that receives at input 104 places of switchgear 200
CTL) can be in the first negative voltage, and the second control voltage (V
CTL) can be in the second negative voltage, to control voltage (V second
CTL2) than the first control voltage (V
CTL) forbid the first depletion mode transistor 201 when negative ground is more.Under the second state of switchgear 200, can control node and first node (A) electricity of the first depletion mode transistor 201 be isolated with the second disabled depletion mode transistor 214.Should be understood that, in the situation of the scope that does not break away from this theme, tracking circuit 203 can selectively link together the control node of Section Point (B) with the first depletion mode transistor 201 under the first state, and can be with the control node isolation of Section Point (B) with the first depletion mode transistor 201 under the second state.
Usually, voltage identification can comprise the transistor that pair of cross connects, to differentiate two higher voltage level or lower voltage level in the voltage input.In the illustrative switch equipment 200 of Fig. 2, voltage identification 205 can comprise respectively two pairs of cross-coupled transistors 215,216 and 217,218, and the 3rd pair of transistor 219,220, to differentiate the minimum voltage in three voltages that received by voltage identification 205.In some examples, three voltages that received by voltage identification 205 can comprise control voltage (V
CTL), the voltage located of the voltage located of first node (A) and Section Point (B).
Fig. 3 A shows the illustrative switch equipment 300 for transfer die analog signal during the off-position of the device that comprises switchgear 300 substantially.Switchgear 300 can comprise depletion mode transistor 301, control circuit 302, tracking circuit 303 and the first voltage identification 305.Under the first state of switchgear 300, depletion mode transistor 301 can be for example at the grid of the first depletion mode transistor 301 voltage (V to source electrode
GS) be in or during near 0V transfer die analog signal between first node (A) and Section Point (B).Under the second state of switchgear 300, depletion mode transistor 301 can be for example at the V of the first depletion mode transistor 301
GSWhen being in negative voltage (this negative voltage has been eliminated the conducting channel of the first depletion mode transistor 301 substantially), with first node (A) and mutually isolation of Section Point (B).
In some examples, control circuit 302 can receive control voltage (V
CTL), and in response to control voltage (V
CTL) voltage levvl control the control node of the first depletion mode transistor 301.In some instances, control circuit 302 can comprise pair of transistor 311, the 312 and the 3rd transistor 313 that connects into inverter.In some examples, the 3rd transistor 313 can be configured to will control voltage (V under the first state
CTL) isolate with the control node of the first depletion mode transistor 301, enable the first depletion mode transistor 301 to allow the first depletion mode transistor 301, and under the second state, will control voltage (V
CTL) be connected to the control node to forbid the first depletion mode transistor 301.In one example, the transistor 311,312 that is connected to inverter can comprise the PMOS enhancement transistor 311 that is connected to ground (GND) and the NMOS enhancement transistor 312 that is connected to voltage identification 305 via power rail (NRail).
Under the first state of switchgear 300, control voltage (V
CTL) can be in or electromotive force closely, and the NMOS enhancement transistor 312 of control circuit 302 can turn-on voltage discriminator 305 and voltage identification 305 is connected to the control node of the 3rd transistor 313 of control circuit 302.Voltage identification 305 can provide the minimum voltage in two or more voltages.In one example, voltage identification 305 can provide the minimum voltage in voltage of controlling one or two place's existence in voltage or first node and the Section Point (A, B).The low-voltage that occurs from the control Nodes of the 3rd transistor 313 of voltage identification 305 can allow depletion mode transistor 301 to enable and the transfer die analog signal.
Under the second state of switchgear 300, control voltage (V
CTL) can be in the negative voltage level that is configured to forbid the first depletion mode transistor 301.Control voltage (V
CTL) can open PMOS enhancement transistor 311, and PMOS enhancement transistor 3 11 can be connected to GND with the control node of the 3rd transistor 313.Because control voltage (V
CTL) be the negative voltage with respect to GND, therefore the 3rd transistor 313 can be opened when being connected to ground at the grid (or control node) of the 3rd transistor 313.In case open, the 3rd transistor 313 of control circuit 302 can be connected to the control node of depletion mode transistor 301 negative control voltage (V
CTL), thereby allow enhancement transistor 301 that first node and Section Point (A, B) is electrically isolated from one.In some examples, the 3rd transistor 313 can comprise enhancement transistor, for example, and the NMOS enhancement transistor.
In some examples, tracking circuit 303 can comprise a pair of enhancement transistor 321 that is connected in parallel, 322 and floating voltage discriminator 323.In some examples, tracking circuit 303 can be connected to first node (A).In one example, the transistor that is connected in parallel 321 of tracking circuit 303,322 can comprise low threshold voltage CMOS transistor.The transistor that is connected in parallel 321 of tracking circuit 303,322 with respect to other tracking circuit (for example can improve, use the tracking circuit of the second depletion type equipment) the performance of switchgear 300, this is because depletion type equipment can lose linearity and along with signal voltage increases and transships.
Usually, tracking circuit 303 can be configured to when under first state of depletion mode transistor 301 at switchgear 300 between first node and Section Point (A, B) during transmission of signal, guarantee the substantially constant conducting resistance of depletion mode transistor 301.Constant conducting resistance can allow have less distortion or do not having in the situation of distortion transmission of signal between first node and Section Point (A, B) substantially.Therefore, for example, audio signal can be sent to another equipment from an equipment, and the fidelity that can not destroy significantly sound.
In some examples, the signal that tracking circuit 303 can allow the control node tracking of depletion mode transistor 301 to transmit between first node and Section Point (A, B) is so that keep V near 0V at depletion mode transistor 301
GSIn one example, during the first state of switchgear 300, for example, and between the turnoff time of the device that comprises switchgear 300, control voltage (V
CTL) and normal power supplies voltage (V
CC) can be 0V with respect to GND.In addition, the control node of the nmos pass transistor 322 of tracking circuit 303 can be connected to control voltage (V
CTL), so that the voltage levvl of the signal of locating when first node (A) is above Ground during electromotive force, the nmos pass transistor 322 of tracking circuit 303 can be connected to first node (A) the control node of depletion mode transistor 301.Although not shown, in identical example, the control node of the PMOS transistor 321 of tracking circuit 303 can be connected to normal power supplies voltage (V
CC), so that the voltage levvl of the signal of locating when first node (A) is when being lower than earth potential, PMOS transistor 321 can be connected to first node (A) the control node of depletion mode transistor 301, to keep the grid of crossing over depletion mode transistor 301 and the V that source electrode is substantially 0V
GS
In some instances, not that control node with the PMOS transistor 321 of tracking circuit is connected to normal power supplies voltage (V
CC), but the control node of the PMOS transistor 321 of tracking circuit 303 can be connected to floating voltage discriminator 323.Floating voltage discriminator 323 can be connected to the control node of PMOS transistor 321 normal power supplies voltage (V
CC) or the minimum voltage of first node (A) voltage locating to occur.At normal power supplies voltage (V
CC) can have larger positive voltage and control voltage (V
CTL) in the time of can having larger negative voltage, this arrangement can reduce the pressure of pair pmos transistor 321 under the second state of switchgear.In some examples, normal power supplies voltage (V
CC) can be to control voltage (V is provided
CTL) charge pump power supply.
Fig. 3 B shows the illustrative switch equipment 300 that comprises the first tracking circuit 303 and the second tracking circuit 306 substantially.In one example, the first tracking circuit 303 can be connected to first node (A), and the second tracking circuit 306 can be connected to Section Point (B).This configuration can with wherein can be associated with the switchgear that analog signal drives first node or Section Point (A, B) independently.
In some examples, the main body of depletion mode transistor 301 or back of the body grid 307 can be connected to the control node with optimization total harmonic distortion under the first state of switchgear 300 and eliminate substantially the conducting channel of depletion mode transistor 301 under the second state, this is that back of the body grid 307 also can be connected to larger negative voltage under the second state because similar with the control node.
Complementary annotations
[add herein claim with as the example before submitting to]
In example 1, switchgear can comprise: the first depletion mode transistor, its be configured under the first state between first node and Section Point the transfer die analog signal, and under the second state with the isolation of described first node and described Section Point; Control circuit, it is connected to the control node of described the first depletion mode transistor, described control circuit is configured under described the first state described control node and the first power input be isolated, and under described the second state described control node is connected to described the first power input; And tracking circuit, its be configured to during described the first state the described control node of described the first depletion mode transistor is connected to described first node and under described the second state with described control node and the isolation of described first node of described the first depletion mode transistor.
In example 2, the described control circuit in the example 1 optionally comprises inverter, and described inverter has the input that is connected to described the first power input; And enhancement transistor, it is configured to receive the output of described inverter and controls described control node with the described output of described inverter.
In example 3, any one in the example 1 to 2 or a plurality of switchgears selectively comprise the first voltage identification that is connected to described first node; Wherein, the first power input of described inverter is configured to be connected to ground; Wherein, the second source input of described inverter is configured to be connected to the output of described the first voltage identification; And wherein, described the first voltage identification is configured to receive a plurality of voltage levvls and provides the voltage levvl that equals substantially the minimum voltage level in described a plurality of voltage levvl at the described output of described the first voltage identification.
In example 4, any one in the example 1 to 3 or a plurality of a plurality of voltage levvls selectively comprise the voltage levvl of described power input.
In example 5, any one in the example 1 to 4 or a plurality of a plurality of voltage levvls selectively comprise the voltage levvl of described first node.
In example 6, in the example 1 to 3 any one or a plurality of switchgears selectively comprise the second voltage discriminator, described second voltage discriminator is connected to the described output of described Section Point and described the first discriminator, wherein, described second voltage discriminator is configured to receive more than second voltage levvl and provides the voltage levvl that equals substantially the minimum voltage level in described more than second voltage levvl at the output of described second voltage discriminator; And wherein, described more than second voltage levvl comprises the voltage levvl of described power input and the voltage levvl of described Section Point.
In example 7, in the example 1 to 6 any one or a plurality of tracking circuits selectively comprise the second depletion mode transistor, described the second depletion mode transistor is connected to the described control node of described the first depletion mode transistor, described the second depletion mode transistor is configured under described the first state the described control node of described the first depletion mode transistor is connected to described first node, and under described the second state with described control node and the isolation of described first node of described the first depletion mode transistor.
In example 8, any one in the example 1 to 3 or a plurality of switchgears selectively comprise the second source input, and described second source input is connected to the control node of described the second depletion mode transistor; Wherein, described the first power input and described second source input are configured to receive the first voltage under described the first state; Wherein, described the first power input is configured to receive second voltage under described the second state; Wherein, described second source input is configured to receive tertiary voltage under described the second state; And wherein, described tertiary voltage is lower than described second voltage, and described second voltage is lower than described the first voltage.
In example 9, in the example 1 to 8 any one or a plurality of tracking circuits optionally comprise the first tracking circuit, described the first tracking circuit be configured under described the first state described first node is connected to the described control node of described the first depletion mode transistor and under described the second state with the described control node isolation of described first node and described the first depletion type equipment; Wherein, described the first tracking circuit comprises the PMOS transistor that is connected in parallel with nmos pass transistor; Wherein, the control node of described nmos pass transistor is connected to described the first power supply; And wherein, when the voltage levvl of described first node under described the first state was lower than described earth potential level, the transistorized control node of described PMOS was connected to described first node.
In example 10, in the example 1 to 9 any one or a plurality of tracking circuits selectively comprise the second tracking circuit, described the second tracking circuit is configured under described the first state described Section Point is connected to the described control node of described the first depletion mode transistor, and under described the second state the described control node of described Section Point and described the first depletion mode transistor is isolated; Wherein, described the first tracking circuit comprises the PMOS transistor that is connected in parallel with nmos pass transistor; Wherein, the control node of described nmos pass transistor is connected to described the first power supply; And wherein, when the voltage levvl of described first node under described the first state was lower than the earth potential level, the transistorized control node of described PMOS was connected to described first node.
In example 11, in the example 1 to 10 any one or a plurality of switchgears selectively comprise the tertiary voltage discriminator, described tertiary voltage discriminator be configured to provide output to control described the first tracking circuit described PMOS transistor and the described PMOS transistor of described the second tracking circuit.
In example 12, the back of the body grid of any one in the example 1 to 11 or a plurality of the first depletion mode transistor selectively are connected to the described control node of described the first depletion mode transistor.
In example 13, method can comprise: using the first depletion mode transistor transfer die analog signal between first node and Section Point under the first state; Under the second state, use described the first depletion mode transistor with described first node and the isolation of described Section Point; Use control circuit control node and isolation of the first power input with described the first depletion mode transistor under described the first state; Use described control circuit under described the second state, the described control node of described the first depletion mode transistor to be connected to described the first power input; Use tracking circuit under described the first state, the described control node of described the first depletion mode transistor to be connected to described first node; And use described tracking circuit under described the second state, described control node and the described first node of described the first depletion mode transistor to be isolated.
In example 14, any one in the example 1 to 13 or a plurality of described control nodes with described the first depletion mode transistor are connected to described first node and selectively comprise: use the second depletion mode transistor under described the first state the described control node of described the first depletion mode transistor to be connected to described first node.
In example 15, any one in the example 1 to 14 or a plurality of described first node and the isolation of described Section Point are selectively comprised: negative voltage is connected to described the first power input.
In example 16, any one in the example 1 to 15 or a plurality of described first node and the isolation of described Section Point are selectively comprised: the control node that the second negative voltage is connected to described the second depletion mode transistor.
In example 17, in the example 1 to 16 any one or a plurality of control node and isolation of the first power input with described the first depletion mode transistor selectively comprise: use inverter that the control node of the output transistor of described control node is connected to power rail, wherein, described output transistor is connected to the described control node of described the first power input, described the first depletion mode transistor and the output of described inverter.
In example 18, any one in the example 1 to 17 or a plurality of use inverter are connected to power rail with the control node of the output transistor of described control node and selectively comprise: use voltage identification to be provided at minimum voltage in the voltage that described the first power input, described first node and described Section Point place present at described power rail place.
In example 19, any one in the example 1 to 3 or a plurality of described control nodes with described the first depletion mode transistor are connected to described first node and selectively comprise: the described control node of the nmos pass transistor of tracking circuit is connected to described the first power input; And when the voltage levvl of described first node under described the first state is lower than the earth potential level, the transistorized control node of the PMOS of described tracking circuit is connected to described first node.
In example 20, any one in the example 1 to 19 or a plurality of methods comprise that selectively the back of the body grid with described the first depletion mode transistor are connected to the described control node of described the first depletion mode transistor.
Example 21 can comprise following theme, perhaps can be selectively with example 1 to 20 in any one or a plurality of arbitrary portion or the combination of arbitrary portion combine to comprise described following theme, described theme can comprise for any one of the function of carrying out example 1 to 20 or a plurality of module or comprise when carried out by machine so that any one in the function of machine execution example 1 to 20 or a plurality of machine readable medias.
Above-mentioned detail specifications is with reference to accompanying drawing, and accompanying drawing also is the part of described detail specifications.Accompanying drawing has shown in graphic mode can use specific embodiments of the invention.These embodiment are known as " example " in the present invention.These examples can comprise except shown in or element the element described.Yet the inventor also is susceptible to the example that those elements that illustrate or describe wherein only are provided.In addition, the inventor also is susceptible to for shown in this article or described particular example (or one is individual or many aspects), or for shown in this article or described other example (or one or many aspects), shown in the use or the example of the combination in any of described those elements or arrangement (or one or many aspects).
All publications, patent and patent document involved in the present invention be all as reference content of the present invention, although they are respectively in addition references.If there is purposes difference between the present invention and the reference paper, then regard replenishing of purposes of the present invention as with reference to the purposes of file, if there is implacable difference between the two, then be as the criterion with purposes of the present invention.
In the present invention, normally used the same with patent document, term " " or " a certain " expression comprises one or more, but other situations or when using " at least one " or " one or more " should except.In the present invention, except as otherwise noted, otherwise use the term "or" refer to without exclusiveness or, so that " A or B " comprising: " A but be not B ", " B but be not A " and " A and B ".In claims, term " comprises " and " therein " is equal to that each term " comprises " and the popular English of " wherein ".Equally, in this article, term " comprises " and " comprising " is open, namely, system, equipment, article or step comprise parts those listed after in claim this term parts, still are considered as dropping within the scope of this claim.And in the claim below, term " first ", " second " and " the 3rd " etc. as label, are not that object is had quantitative requirement only.
Method example as herein described is at least part of can be that machine or computer are carried out.Some examples can comprise computer-readable medium or machine readable media, and it is encoded with and is operable as the instruction that electronic installation is configured to carry out the method described in above-mentioned example.The realization of these methods can comprise code, microcode for example, assembler language code, higher-level language code etc.This code can comprise for the computer-readable instruction of carrying out the whole bag of tricks.Described code can consist of the part of computer program.In addition, in one example, described code can be for example the term of execution or visibly be stored in At All Other Times on one or more volatile, nonvolatiles or the non-volatile tangible computer-readable medium.The example of these tangible computer-readable mediums includes but not limited to, hard disk, mobile disk, moving CD (for example, compact disk and digital video disk), tape, storage card or rod, random access memory (RAM), read-only memory (ROM) etc.
The effect of above-mentioned explanation is to explain orally and unrestricted.For example, above-mentioned example (or one or more aspects of example) can be combined with.Can on the basis of understanding above-mentioned specification, utilize certain routine techniques of prior art to carry out other embodiment.The regulation of abideing by 37 C.F.R. § 1.72 (b) provides summary, allows the reader to determine fast the disclosed character of present technique.Should be understood that when submitting this summary to that this summary is not used in scope or the meaning of explaining or limiting claim.Equally, in the superincumbent embodiment, various features can be classified into rationalizes the disclosure.This open feature that does not should be understood to failed call is essential to any claim.On the contrary, the theme of the present invention feature that can be is less than all features of specific disclosed embodiment.Therefore, following claim is incorporated in the embodiment accordingly, and each claim is all as an independent embodiment, and can be susceptible to these embodiment and be bonded to each other in can or arranging in various combinations.Should be referring to appended claim, and all scopes of the equivalent enjoyed of these claims, determine scope of the present invention.
Claims (20)
1. switchgear comprises:
The first depletion mode transistor, its be configured under the first state between first node and Section Point the transfer die analog signal, and under the second state with the isolation of described first node and described Section Point;
Control circuit, it is connected to the control node of described the first depletion mode transistor, described control circuit is configured under described the first state described control node and the first power input be isolated, and under described the second state described control node is connected to described the first power input; And
Tracking circuit, its be configured to during described the first state the described control node of described the first depletion mode transistor is connected to described first node and under described the second state with described control node and the isolation of described first node of described the first depletion mode transistor.
2. switchgear according to claim 1, wherein, described control circuit comprises:
Inverter, it has the input that is connected to described the first power input; And
Enhancement transistor, it is configured to receive the output of described inverter and controls described control node with the described output of described inverter.
3. switchgear according to claim 2 comprises the first voltage identification that is connected to described first node;
Wherein, the first power input of described inverter is configured to be connected to ground;
Wherein, the second source input of described inverter is configured to be connected to the output of described the first voltage identification; And
Wherein, described the first voltage identification is configured to receive a plurality of voltage levvls and provides the voltage levvl that equals substantially the minimum voltage level in described a plurality of voltage levvl at the described output of described the first voltage identification.
4. switchgear according to claim 3, wherein, described a plurality of voltage levvls comprise the voltage levvl of described power input.
5. switchgear according to claim 3, wherein, described a plurality of voltage levvls comprise the voltage levvl of described first node.
6. switchgear according to claim 3 comprises the second voltage discriminator, and described second voltage discriminator is connected to the described output of described Section Point and described the first discriminator;
Wherein, described second voltage discriminator is configured to receive more than second voltage levvl and provides the voltage levvl that equals substantially the minimum voltage level in described more than second voltage levvl at the output of described second voltage discriminator; And
Wherein, described more than second voltage levvl comprises the voltage levvl of described power input and the voltage levvl of described Section Point.
7. each described switchgear in 6 according to claim 1, wherein, described tracking circuit comprises the second depletion mode transistor, described the second depletion mode transistor is connected to the described control node of described the first depletion mode transistor, described the second depletion mode transistor is configured under described the first state the described control node of described the first depletion mode transistor is connected to described first node, and under described the second state with described control node and the isolation of described first node of described the first depletion mode transistor.
8. switchgear according to claim 7 comprises the second source input, and described second source input is connected to the control node of described the second depletion mode transistor;
Wherein, described the first power input and described second source input are configured to receive the first voltage under described the first state;
Wherein, described the first power input is configured to receive second voltage under described the second state;
Wherein, described second source input is configured to receive tertiary voltage under described the second state; And
Wherein, described tertiary voltage is lower than described second voltage, and described second voltage is lower than described the first voltage.
9. each described switchgear in 6 according to claim 1, wherein, described tracking circuit comprises the first tracking circuit, described the first tracking circuit be configured under described the first state described first node is connected to the described control node of described the first depletion mode transistor and under described the second state with the described control node isolation of described first node and described the first depletion type equipment;
Wherein, described the first tracking circuit comprises the PMOS transistor that is connected in parallel with nmos pass transistor;
Wherein, the control node of described nmos pass transistor is connected to described the first power supply; And
Wherein, when the voltage levvl of described first node under described the first state was lower than described earth potential level, the transistorized control node of described PMOS was connected to described first node.
10. switchgear according to claim 9, wherein, described tracking circuit comprises the second tracking circuit, described the second tracking circuit is configured under described the first state described Section Point is connected to the described control node of described the first depletion mode transistor, and under described the second state the described control node of described Section Point and described the first depletion device is isolated;
Wherein, described the first tracking circuit comprises the PMOS transistor that is connected in parallel with nmos pass transistor;
Wherein, the control node of described nmos pass transistor is connected to described the first power supply; And
Wherein, when the voltage levvl of described first node under described the first state was lower than the earth potential level, the transistorized control node of described PMOS was connected to described first node.
11. switchgear according to claim 10 comprises the tertiary voltage discriminator, described tertiary voltage discriminator be configured to provide output to control described the first tracking circuit described PMOS transistor and the described PMOS transistor of described the second tracking circuit.
12. each described switchgear in 6 according to claim 1, wherein, the back of the body grid of described the first depletion mode transistor are connected to the described control node of described the first depletion mode transistor.
13. a method comprises:
Using the first depletion mode transistor transfer die analog signal between first node and Section Point under the first state;
Under the second state, use described the first depletion mode transistor with described first node and the isolation of described Section Point;
Use control circuit control node and isolation of the first power input with described the first depletion mode transistor under described the first state;
Use described control circuit under described the second state, the described control node of described the first depletion mode transistor to be connected to described the first power input;
Use tracking circuit under described the first state, the described control node of described the first depletion mode transistor to be connected to described first node; And
Use described control node and the isolation of described first node with described the first depletion mode transistor under described the second state of described tracking circuit.
14. method according to claim 13, wherein, the described control node of described the first depletion mode transistor being connected to described first node comprises: use the second depletion mode transistor under described the first state the described control node of described the first depletion mode transistor to be connected to described first node.
15. method according to claim 14 wherein, comprises described first node and the isolation of described Section Point: negative voltage is connected to described the first power input.
16. method according to claim 15 wherein, comprises described first node and the isolation of described Section Point: the control node that the second negative voltage is connected to described the second depletion mode transistor.
17. method according to claim 13, wherein, control node and the isolation of the first power input of described the first depletion mode transistor are comprised: use inverter that the control node of the output transistor of described control node is connected to power rail, wherein, described output transistor is connected to the described control node of described the first power input, described the first depletion mode transistor and the output of described inverter.
18. method according to claim 17, wherein, using inverter that the control node of the output transistor of described control node is connected to power rail comprises: come to be provided at described power rail place minimum voltage in the voltage that described the first power input, described first node and described Section Point place present with voltage identification.
19. method according to claim 13 wherein, is connected to described first node with the described control node of described the first depletion mode transistor and comprises:
The described control node of the nmos pass transistor of tracking circuit is connected to described the first power input; And
When the voltage levvl of described first node under described the first state is lower than the earth potential level, the transistorized control node of the PMOS of described tracking circuit is connected to described first node.
20. method according to claim 13 comprises that the back of the body grid with described the first depletion mode transistor are connected to the described control node of described the first depletion mode transistor.
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| Application Number | Priority Date | Filing Date | Title |
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| CN2012100999740A CN103368546A (en) | 2012-03-30 | 2012-03-30 | Analog switch which starts after power failure and relevant method |
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| Application Number | Priority Date | Filing Date | Title |
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| CN2012100999740A CN103368546A (en) | 2012-03-30 | 2012-03-30 | Analog switch which starts after power failure and relevant method |
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Application publication date: 20131023 |