CN103373700A - Methods for producing a cavity within a semiconductor substrate - Google Patents

Methods for producing a cavity within a semiconductor substrate Download PDF

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Publication number
CN103373700A
CN103373700A CN2013101333197A CN201310133319A CN103373700A CN 103373700 A CN103373700 A CN 103373700A CN 2013101333197 A CN2013101333197 A CN 2013101333197A CN 201310133319 A CN201310133319 A CN 201310133319A CN 103373700 A CN103373700 A CN 103373700A
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cavity
etching
semiconductor base
section
mems
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CN2013101333197A
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CN103373700B (en
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凯-亚历山大·施雷贝尔
安德烈亚斯·贝伦特
索克拉蒂斯·斯古里迪斯
伯恩哈德·温克勒
马丁·泽加加
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Infineon Technologies AG
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Infineon Technologies AG
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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00436—Shaping materials, i.e. techniques for structuring the substrate or the layers on the substrate
    • B81C1/00555—Achieving a desired geometry, i.e. controlling etch rates, anisotropy or selectivity
    • B81C1/00619—Forming high aspect ratio structures having deep steep walls
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00436—Shaping materials, i.e. techniques for structuring the substrate or the layers on the substrate
    • B81C1/00523—Etching material
    • B81C1/00531—Dry etching
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B3/00—Devices comprising flexible or deformable elements, e.g. comprising elastic tongues or membranes
    • B81B3/0018—Structures acting upon the moving or flexible element for transforming energy into mechanical movement or vice versa, i.e. actuators, sensors, generators
    • B81B3/0021—Transducers for transforming electrical into mechanical energy or vice versa
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B3/00—Devices comprising flexible or deformable elements, e.g. comprising elastic tongues or membranes
    • B81B3/0064—Constitution or structural means for improving or controlling the physical properties of a device
    • B81B3/0094—Constitution or structural means for improving or controlling physical properties not provided for in B81B3/0067 - B81B3/0091
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00436—Shaping materials, i.e. techniques for structuring the substrate or the layers on the substrate
    • B81C1/00555—Achieving a desired geometry, i.e. controlling etch rates, anisotropy or selectivity
    • B81C1/00626—Processes for achieving a desired geometry not provided for in groups B81C1/00563 - B81C1/00619
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B2203/00—Basic microelectromechanical structures
    • B81B2203/03—Static structures
    • B81B2203/0323—Grooves
    • B81B2203/033—Trenches
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2201/00—Manufacture or treatment of microstructural devices or systems
    • B81C2201/01—Manufacture or treatment of microstructural devices or systems in or on a substrate
    • B81C2201/0101—Shaping material; Structuring the bulk substrate or layers on the substrate; Film patterning
    • B81C2201/0128—Processes for removing material
    • B81C2201/013—Etching
    • B81C2201/0135—Controlling etch progression
    • B81C2201/0139—Controlling etch progression with the electric potential of an electrochemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3063—Electrolytic etching

Abstract

A method for producing at least one cavity within a semiconductor substrate includes dry etching the semiconductor substrate from a surface of the semiconductor substrate at at least one intended cavity location in order to obtain at least one provisional cavity. The method includes depositing a protective material with regard to a subsequent wet-etching process at the surface of the semiconductor substrate and at cavity surfaces of the at least one provisional cavity. Furthermore, the method includes removing the protective material at least at a section of a bottom of the at least one provisional cavity in order to expose the semiconductor substrate. This is followed by electrochemically etching the semiconductor substrate at the exposed section of the bottom of the at least one provisional cavity. A method for producing a micromechanical sensor system in which this type of cavity formation is used and a corresponding MEMS are also disclosed.

Description

Be used in the inner method that forms cavity of semiconductor base
Technical field
Embodiments of the invention can be realized a kind of for the method at least one cavity of the inner formation of semiconductor base.Other embodiments of the invention can realize MEMS.
Background technology
(English: " microelectromechanical systems ", MEMS), also for example the height integrated package of some microelectronic devices needs deep cavity, hole or leaves a blank some MEMSs.For example, in MEMS technique, real MEMS structure is usually in the upper structuring of the first surface (for example upper surface or front) of semiconductor base.Type according to the MEMS assembly, may need to be positioned at first surface or positive existing structure so that also can enter these from the second surface of semiconductor base or the back side, wherein this second surface is relatively arranged with first surface for semiconductor base.Example is pressure sensor, the diaphragm of pressure sensor is provided in the first surface of semiconductor base or front by means of MEMS technique, but second surface or the back side also additionally need entrance, can apply the pressure that will measure to diaphragm by this entrance wherein.Other example is acoustic transducer (loudspeaker or microphone) and acceleration transducer.At the MEMS(MEMS for the production of this type (sensor and actuator)) (usually: the wafer that is made of semi-conducting material) making cavity, is the frequent task of appearance in the MEMS technique for the silicon wafer of member (for example pressure sensor and acceleration transducer).
Now, typically in HIGH-PURITY SILICON by means of anisotropy, chemical etching with the TMAH(Tetramethylammoniumhydroxid(TMAH)) realize these cavitys.Utilizing TMAH to carry out etching is wet-chemical etch methods.Typically, the cavity of pure wet chemical etch has relatively large expansion according to area because be selectively with 54.7 ° angle of the flank naturally given in advance (etching given in advance between Si＜100〉and Si＜111 crystallization angle between the face) carry out etching.In other words, can utilize wet-chemical etch methods typically only to reach the aspect rate of less.Aspect rate typically refers to the ratio of constructional depth and its (minimum) lateral spread size.
So-called chemical etching also belongs to wet-chemical etch methods.It is a kind of be used to making etching process automation and the method for control selectively being used for according to the chemical etching (English: " Electrochemical Etching " (ECE)) that dopant material is removed silicon selectively.Usually, need the pn that activates to tie, and two kinds of dopant materials can be as anti-etching material (" etch stop ").With the anisotropic etch method combination, chemical etching can be used for for example controlling with high accuracy the thickness (for example diaphragm thickness of the pressure sensor of pressure drag) of MEMS structure.Required selective doping zone can for example be realized by injection, diffusion or epitaxial deposition silicon or other semi-conducting material for this reason.Can be in the chemical etching process with the precision of about 0.05 μ m, perhaps even with the precision of about 0.03 μ m control etch depth (thereby and also control in case of necessity the thickness of corresponding MEMS structure).
What be worth yearning is, provide a kind of in the inner method that forms at least one cavity of semiconductor base, the method can be combined with the possibility of the etch stop of relatively high precision control and the large as far as possible aspect rate that formed cavity can reach.Replacedly or additionally, can make one or more cavitys in semiconductor base is to be worth yearning for, and this one or more cavity is set out by (these) cavity on the surface and has as far as possible little area requirements.In addition, what replacedly or additionally be worth yearning for is, can with low cost as far as possible and/or fast mode in semiconductor base, form one or more darker cavitys.
Summary of the invention
This (these) purpose realizes for the method, a kind of method and a kind of MEMS according to claim 22 for the production of MEMS according to claim 21 that form at least one cavity at semiconductor base by according to claim 1 a kind of or claim 13 is described.
Embodiments of the invention have been realized a kind of for the method at least one cavity of the inner formation of semiconductor base.This method comprises: dry etching semiconductor base, deposition protective material, remove protective material and semiconductor base is carried out chemical etching.From the surface of semiconductor base, at the empty cavity position place of at least one expection semiconductor base is carried out dry etching, in order to obtain at least one interim cavity.In view of follow-up wet etch process deposits protective material on the surface of semiconductor base and the cavity surface place of at least one interim cavity.When removing protective material, remove protective material at a section section place of at least one interim cavity bottom at least, in order to expose this semiconductor base.Then at the section section place of exposing of the bottom of at least one interim cavity this semiconductor base is carried out chemical etching.
Other embodiments of the invention can realize for the method at least one cavity of the inner formation of semiconductor base.The substrate surface that this method is included in semiconductor base is implemented richly to execute process (Boschprozess), in order to form at least one interim cavity.In addition, this method is included in the PCVD of the cavity surface enforcement silica of substrate surface and at least one interim cavity.In addition, this method comprises at least at a section section place of the bottom of at least one interim cavity silica is carried out anisotropic etching.This method also is included under the condition of using the pn etch stop that is subjected to electrochemical control carries out electrochemistry, anisotropic etching to semiconductor base, wherein, at least carry out electrochemistry, anisotropic etching at a section section place of the bottom of at least one interim cavity, and at least one interim cavity is widened in this way.
Other embodiments of the invention realize the method for the production of the micro mechanical sensor system.This method comprises the semiconductor base that doping is provided.Then be implemented in the zone of semiconductor base inner counter doping (Umdotieren) at least one contra-doping of doping, wherein the zone of at least one contra-doping is arranged in the degree of depth of determining with the substrate surface of semiconductor base apart.This method also comprises for forming micro electromechanical structure and implement structurizing process at semiconductor base with at substrate surface.At least a portion of the micro electromechanical structure that arranges extends in the zone of contra-doping.Then, implement described method for form at least one cavity in semiconductor base inside of preamble.After production is finished, the part adjacency of the cavity of formation and the zone of contra-doping and micro electromechanical structure, this part extends in the zone of contra-doping.
According to other embodiments of the invention, MEMS comprises the semiconductor base with surface and the cavity that forms in this semiconductor base.The sidewall of this cavity comprises First section and second section far away apart from this substrate surface.The first angle that First Duan Yiyu surface is between 70 ° to 110 ° is extended.The second angle that second Duan Yiyu surface is between 40 ° to 65 ° is extended.
Embodiment is based upon on such basis, and the anisotropic etch process of namely at first carrying out is conducive to make (these) cavity that will form to reach high as far as possible aspect rate or as far as possible little area requirements.Then, this anisotropic etching process is taken over by the chemical etching process, thereby provides relatively accurately control for the degree of depth of (these) cavity that will form.
By the dry etching of at first using, can obtain etching side (Aetzflanken) or the sidewall of perpendicular within certain etch depth, this etching side or sidewall combine with subsequent process steps and can reduce the required chip area of sensor.Therefore, can utilize the less gross area to realize the production process of semiconductor component (for example silicon component).
Be used for to be included as in the inner method that forms at least one cavity of semiconductor base the dry etching deposition oxide mask of semiconductor base.Typically, deposition oxide mask and make its structuring before dry etching.At the empty cavity position place of at least one expectation, for example by photoetching process, the local oxide mask of removing.
The dry etching of semiconductor base can comprise at least one in the following process: reactive ion etching (RIE), deep reaction ion(ic) etching (DRIE) and the rich process of executing.This etching process is anisotropy fully usually, so that (these) the interim cavity that forms by these processes obtains precipitous sidewall or side.Can consider equally anisotropic etching process or common structurized process.
Protective material can be oxide, particularly silica and/or isolation oxide.Usually, the selection of protective material depends on whether the performance, particularly protective material of protective material in follow-up chemical etching process is corroded relatively lessly by the chemical etching process, otherwise base material is etched relatively rapidly.In other words, can select like this protective material, namely take full advantage of or be implemented in the high as far as possible selective of chemical etching between semiconductor-based bottom material and the protective material.
The deposition of protective material can comprise plasma deposition, thermal oxide deposition or their combination.
Remove protective material and can comprise plasma etching.The plasma etching of protective material is typically answered anisotropy.
Before removing protective material, be used for to comprise deposition mask and this mask structure that makes deposition in the inner method that forms at least one cavity of semiconductor base.Only can realize in this way removing protective material in the position of determining, for example at least at a section section place of the bottom of previously described, at least one interim cavity.In an embodiment, can also design the protective material that removal is located substantially on the whole bottom of cavity.Because typically should increase the degree of depth of interim cavity; so what the protective layer of the bottom by removing interim cavity (or interim cavity at least one section place, bottom) can be realized is that the bottom of soon exposing by this way (section's section) is provided for follow-up chemical etching process as erosion surface.On the contrary, the protection of the surperficial protected material that other of semiconductor base do not expose, and correspondingly do not suffer the chemical etching process.
The alkali etching medium can be used for chemical etching.
Chemical etching can provide the etch stop technology, for example by at semiconductor base be present between the electrode in the etching media and execute alive mode.
The method that is used to form at least one cavity can also comprise implements photoetching process and injection subsequently, so that the depth in semiconductor base inside forms the pn knot, wherein, this degree of depth that this pn ties is the function of depth desired of the bottom of at least one cavity.
Chemical etching can comprise very first time section and the second time period.In very first time section, can raise is applied to the voltage of semiconductor-based bottom.Within the second time period, for example can make the voltage that has reached keep constant or again decline.The reference potential that is applied to the voltage on the semiconductor base is usually relevant with the electrode that is arranged in etching media or contact with etching media.Voltage raises can be relevant with voltage value.Typically, in the pn knot, relative with the surface side voltage is applied in the substrate, should forms cavity in the surface.In this way, executing alive at least a portion forges by this pn and falls.
The etching media that is used for chemical etching for example can comprise the aqueous solution, hydrazine, potassium hydroxide (KOH) or their combination of TMAH (TMAH), ethylenediamine and catechol (EDP).
According to the embodiment of MEMS, this system can also comprise the pn knot that is positioned at semiconductor base inside.At this, this pn knot can be arranged in or be positioned at the cavity bottom side opposite with cavity.Yet the pn knot can that is to say on the height of this cavity bottom also that basically pn knot and cavity bottom are measured from one of them substrate surface, basically are in the identical degree of depth or are in identical depth bounds.
Relatively near the surface, cavity begins from this surface to extend and/or stretch into the semiconductor base First section of cavity sidewalls for the surface of semiconductor base.On the contrary, second section can be in semiconductor base inside depths more.
In the First section, cavity sidewalls can have the structure with a plurality of recess that overlap each other or breach.This structure represents that typically the First section of cavity or cavity forms by means of the rich process of executing.Compare with the cross section of the first cavity section, basically attaching troops to a unit has larger cross section in the second cavity section of second section of sidewall.
In an embodiment, MEMS comprises: sensor, actuator, pressure sensor, acceleration transducer or dynamo-electric converter (Wandler).
Basal part section between this surperficial or other surface of cavity bottom and semiconductor base can consist of diaphragm, beam, cantilever or the mechanical quality element (Masseelement) of MEMS.For pack into other structure of MEMS inside of the function that realizes determining is admissible equally.
In the embodiment of MEMS, except having a mind to and/or unintentionally impurity (dopings) and the conversion of material in case of necessity (for example oxidation of partial restriction or oxide layer formation), substrate can mainly be made of silicon.
In an embodiment, sidewall can have end difference or the arris that for example consists of the transition between the first side wall section section and the second side wall portion section at least.In the inside of the second side wall portion section itself, sidewall also can have end difference or arris.
The aspect rate of embodiment cavity can be 1.5 or more than.
Description of drawings
Below by accompanying drawing embodiments of the invention are at length described.Shown in the figure:
Fig. 1 is used at the inner indicative flowchart that forms the method for at least one cavity of semiconductor base according to embodiment.
Fig. 2 is used at the inner indicative flowchart that forms the method for at least one cavity of semiconductor base according to other embodiment.
Fig. 3 illustrates the method that is used to form at least one cavity according to embodiment with the schematic cross-sectional view of passing semiconductor base.
Fig. 4 illustrates the method that is used to form at least one cavity according to other embodiment with schematic substrate cross section.
Fig. 5 illustrates the schematic cross-sectional view of utilizing two cavitys that the method according to embodiment forms.
Fig. 6 illustrates the schematic cross-sectional view of utilizing two cavitys that the method according to other embodiment forms.
Fig. 7 illustrates the schematic cross-sectional view of MEMS, and this MEMS has cover wafers (Abdeck-Wafer) and channel wafer (Zugang-Wafer).
Fig. 8 illustrates the schematic cross-sectional view of sensor device geometry.
Fig. 9 is illustrated in the schematic perspective viewgraph of cross-section that is used to form four interim cavitys that form in the method for at least one cavity according to embodiment.
Figure 10 illustrates and utilizes the schematic perspective viewgraph of cross-section that is used to form two cavitys that the method for at least one cavity forms according to embodiment.
Figure 11 illustrates the schematic diagram of the various etching models of the combination realization that can utilize various engraving methods or engraving method.
Figure 12 illustrates the details profile of cavity sidewalls upper edge with electron micrograph.
The specific embodiment
Following by accompanying drawing embodiment is set forth before, it may be noted that and use identical element or the identical element of function of same or analogous reference number mark, and be not repeated in this description these elements.So the description with element of same or analogous reference number can exchange each other.One or more features of embodiment can be with one or more Feature Combinations of another embodiment or by its replacement.
In MEMS technique, most of micro electromechanical structure forms at substrate surface mostly.At this, particularly can make the base material self structure, and can make other material in substrate surface deposition and structuring, so that final micro electromechanical structure typically has layer structure.Yet in this external some MEMS, also may need or what be fit to is to realize the raceway groove from opposite substrate surface to micro electromechanical structure.For example, pressure sensor can need transmission channel, and the pressure that measure flows to the diaphragm that forms the microelectromechaniccomponents components structure by this transmission channel.In acceleration transducer, may need or be fit to be, be used in the mechanical quality element of surveying acceleration and can be offset enough far, for this reason, must be around mass elements the enough large free space of design, in order to do not hinder the skew of mass elements.In these and other example, can in semiconductor base, design cavity, this cavity is by the back side (that is, with respect to the surface that the forms micro electromechanical structure) moulding of substrate.
Embodiment is used for that (perhaps in general: the wafer that is made of semi-conducting material) production cavity, this silicon wafer is used to form the MEMS member (for example pressure sensor and acceleration transducer) of this type (sensor and actuator) at silicon wafer.In order to form these cavitys in the HIGH-PURITY SILICON body material of MEMS member, in this use so-called " anabolic process ", this anabolic process typically comprises following processing step successively on different process equipments:
1. carry out dry etching (DRIE-" ion(ic) etching of Deep reactive ion etching(deep reaction) under the condition of oxide hardmask using "/the rich process of executing)
2. deposition isolation oxide and etching is as the oxide of follow-up wet chemical etch sidewall protective-isolation-structure
3. carry out the anisotropic etching of electrochemistry with TMAH
By when beginning (in step 1) use richly execute etching, can obtain vertical etching side, until certain etch depth, this is rich executes etching and two subsequent process steps (2. and 3.) and makes up and can reduce the required chip area of sensor.Therefore, can utilize the less gross area to realize the production process of silicon component (being generally semiconductor component).
According to the anabolic process of embodiment, in this example of exemplarily describing herein, can realize 4.08mm 2Chip size; At present, the MEMS silicon sensor area that has a structure of comparativity is 6.49mm 2(saving area 37%).Can be by executing etching process and reduce the sensor component area with rich, this is rich executes etching process provides vertically extending etching side.Execute the etched degree of depth (etching process duration) according to rich, can further reduce the cavity area, thereby further reduce the area of silicon MEMS sensor component.Execute in the etching process rich, etch depth is restricted thus, namely just begin afterwards ground connection (nachgeschaltet) realization pn etching from the etch depth of determining, this is because be to have reached the space-charge region (being called for short RLZ) of pn knot in this degree of depth of substrate, and does not realize the etch stop of self-regulation.
Fig. 1 illustrates according to embodiment and is used at the inner indicative flowchart that forms the method for at least one cavity of semiconductor base.In step 102, at first from the surface of semiconductor base, in the position of at least one expectation cavity semiconductor base is carried out dry etching, in order to obtain at least one interim cavity.Dry etching can comprise reactive ion etching (English: " Reactive ion etching " RIE) or the deep reaction ion(ic) etching (English: " Deep reactive ion etching ", DRIE).
Show such as step 104 in the flow chart of Fig. 1, then deposit protective material.In view of follow-up wet etch process (step 108 is seen the below) deposits protective material at semiconductor-based basal surface with at the cavity surface place of at least one interim cavity.Basically can be on whole area and isotropically deposit protective material so that surface substrate or at least one cavity basically with its orientation irrespectively protected material cover.In many cases, the oxide of base material is suitable as protective material.Protective material for example can be isolation oxide.In this case, also step 104 can be called isolated deposition.Particularly, can be with silane (Silan) as protective material, however wherein, also can use other protective material and do not repel fully.
Subsequently, remove protective material at a section section place of the bottom of at least one interim cavity at least, in order to expose semiconductor base at this, shown in step 106 in the indicative flowchart of Fig. 1.By step 104(deposition protective material) and 106(local removal protective material selectively) interaction; except expose this/these section places, semiconductor base is protected follow-up wet chemical etch process or chemical etchings of preventing all throughout almost.Section's section that this exposes or that these expose can be positioned at the bottom of at least one interim cavity, so that follow-up wet chemical etch process or chemical etching process can this/these positions remove or corrode substrate, thereby and under the condition of the opening of surface, make this cavity darker not expanding this cavity.This is described in the step 108 of the indicative flowchart of Fig. 1, according to this step, at the section section place of exposing of the bottom of at least one interim cavity semiconductor base is carried out chemical etching.According to the selection to chemical etching process or wet chemical etch process, may cavity significantly be widened by section's intersegmental part electrochemical or that wet chemical etch forms.It is proportional that cavity this widened with the additional depth that reaches by the chemical etching to cavity in step 108.Take chemical etching as comparing according to forming cavity, can utilize the method formation cavity that is used to form at least one cavity according to embodiment with only, this cavity has the lateral spread less than other method when the degree of depth has comparativity.
Proceed to which kind of degree of depth and make the selection of the further moulding of cavity according to step 108 by chemical etching subsequently for the step 102 with dry etching, can and require coupling with the actual conditions of respective process or the MEMS that will produce.Selection to dry etching and chemical etching proportion, for example can consider the different etching speeds of two etching processes and the process duration that determines thus, its cost (in view of required device and operating cost) and the higher yield rate or the quantity that are used for the chip of each wafer, it can reach by the combined method of recommending.If each wafer is preponderated than high cost than processed wafer is issuable than the advantage of high finished product rate, particularly can consider to carry out as far as possible for a long time dry etching (step 102).This depends on especially, can accurately carry out regulation and control to etch depth in the dry etching process.Dry etching should stop before reaching the final cavity depth of expection usually, otherwise, can produce the risk that corrodes even destroy micro electromechanical structure, this micro electromechanical structure is arranged in the extension of final cavity or is positioned at cavity bottom.For example, with respect to the ultimate depth of cavity, the ratio of dry etching can be 2/3rds.Replacedly, the ratio of dry etching can be between 30% and 90%, and particularly has following numerical value: the ultimate depth with respect to the cavity that will form is 30%, 50%, 75%, 80% or 90% respectively.
Chemical etching step 108 stops automatically in the degree of depth given in advance usually, and this is by providing corresponding etch stop (for example utilizing the form of the pn knot that has applied voltage) to realize.
As possible application, embodiment provides the possibility that significantly reduces MEMS sensor (for example combination pressure sensor and acceleration transducer) member area, in order to arrange sensor component as much as possible at (for example on 6 inches wafers or 8 inches wafers) on the wafer of determining size with corresponding as far as possible little area thus.
In the pressure sensor and acceleration transducer that mention as an example herein, combination, for example focus can be placed on the sensor area that reduces acceleration transducer, this acceleration transducer finally should be with the sensitivity operation identical according to the larger homologue of area with it.For this reason, usually make every effort to make the inertia mass of sensor to remain unchanged as far as possible, because only in this way could realize to the full extent consistent resonant frequency, sensor utilizes this resonant frequency operation.
Realize that this point need adopt in such a way, that is, at first execute etching (maybe can resist under the condition of negative glue (Negativ-Lack) of etching media using the oxide dura mater) chip back surface (wafer material is silicon for example) with the photoetching form structure is degraded by means of rich.Can obtain in this way the etching side of perpendicular in the body silicon.Rely on spacer techniques (plasma or thermal oxide deposition; carry out subsequently anisotropic plasma etching); protect the rich vertical sidewall of executing the cavity that etching forms by means of oxide layer; and the electrochemistry of carrying out subsequently; anisotropic etching is (with TMAH; EDP; hydrazine; the alkali etching medium that KOH or other are commonly used) make the etching working face reach existing space charged region in the p-substrate the degree of depth (chemical etching stops at before the pn knot that polarizes on the cut-off direction-etching media is from the p zone; stop at the n region direction), this etching working face is finally determined diaphragm thickness (pressure sensor) or cantilever thickness (Cantileverdicke) (acceleration transducer).
Feature according to the method for embodiment is and SOI(" Silicon-on-Insulator " (silicon on the dielectric substrate)) to compare silica-based material price cheap for stock.Another kind realizes that by means of silico briquette etching process (Silizium-Bulk-Aetzverfahren) possibility than the minor structure size is to use the SOI stock in MEMS sensor construction element.Yet do not use pn etch stop method at this, thereby and do not use anabolic process.This principle is only executed etching process as foundation to adopt to win mostly.At this, etch stop is realized in the oxide layer of SOI material.Therefore, the MEMS product that is made of the SOI stock has vertical etching side with the rich great majority of executing etching method of use.
So, embodiment based on described herein for the production of MEMS silicon sensor member and silicon wafer substrate on other MEMS assembly or " anabolic process " (variant scheme of " Silizium-Micro Machining " (Si micromachining)) of electronic building brick.Replacedly, also can consider other semi-conducting material.This technology can reduce required chip area (particularly silicon wafer area) and correspondingly reduce member, the particularly area of silicon sensor member (English: " shrink ").
Embodiment comprises described for for example at block HIGH-PURITY SILICON (Bulk-Reinstsilizium)＜100〉form the processing step of cavity structure:
A) under the condition of using positive glue or negative glue mask, implement the rich etching process (DRIE) of executing
B) to for the protection of through the rich vertical silicon sidewall of executing the cavity that etching forms, unadulterated silex glass (interval technique) carries out plasma CVD deposition and anisotropic etching
C) utilize the etch stop technology to carry out electrochemistry, anisotropic etching (realized etch stop in depth section before the space-charge region of the pn knot that the cut-off direction polarizes, this pn knot for example produces by means of photoetching and injection technique) with alkaline medium
Fig. 2 illustrates the indicative flowchart that is used to form the method for at least one cavity according to other possible embodiment.This method is executed process as beginning to win in the enforcement of the substrate surface place of semiconductor base in step 202, in order to consist of at least one interim cavity.
Then, carry out silica (or another kind of oxide) PCVD (English: " Plasma chemical vapor deposition(CVD) in the cavity surface of substrate surface and at least one interim cavity ").Silica also deposits on the plane that is not parallel to the substrate surface extension usually, and for example the sidewall of interim cavity also is this situation.Silica is in particular as the protective material (seeing step 208 and follow-up to the description under this) of subsequent.
Shown in the step 206 of the indicative flowchart of Fig. 2, subsequently silica is carried out anisotropic etching, namely carry out at a section section place of the bottom of at least one interim cavity at least.In this way, remove the silica in this zone and expose the respective segments of bottom, that is to say that base material is no longer covered by silica on this position.For in the position of expectation, namely at least at a section section place of (these) interim cavity bottom, realize selectively the etching to silica in the part, can before be connected to step 206 ground and realize in advance lithography step or other suitable being used to form/the remove process of surf zone mask.
Be used for after silica is carried out anisotropic etching, utilizing electrochemistry, the anisotropic etching of semiconductor base being proceeded in the inner method that forms at least one cavity of semiconductor base, see step 208.Be subjected in use to realize electrochemistry, anisotropic etching under the condition of pn etch stop of electrochemical control, wherein, at least realize this electrochemistry, anisotropic etching at a section section place of the bottom of at least one interim cavity, this section in advance (step 206) is exposed.In this way, interim cavity is enlarged, namely from the bottom of interim cavity with etching outline, this etching outline has characterized employed electrochemistry, anisotropic engraving method.For example, the sidewall of cavity consists of definite angle at the section's Duan Zhongyu substrate surface that is formed by electrochemistry, anisotropic etching, for example in Si＜100〉and Si＜111 54.7 ° crystallization angle between the face.
Fig. 3 illustrates the schematic diagram of the anabolic process of being recommended with five width of cloth schematic cross-sectional view, and this viewgraph of cross-section correspondingly illustrates the intermediate steps of anabolic process.
Subgraph at Fig. 3 a) illustrates substrate 10 with cross section.This substrate is that p mixes, and this for example can be by hitherward realizing for B Implanted atom in the lattice of silicon.Be assumed to silicon crystal in the example that this substrate illustrates herein, this crystal＜100〉face consist of the interarea of substrates 10, i.e. first surface 11 and second surface 12.Can notice, in MEMS technique, micro electromechanical structure often realize in advance and be arranged in substrate 10, referred to herein as the surface of second surface 12.At second surface 12 places or in its vicinity, be provided with contra-doping zone 15 in substrate 10 inside.So in the example of the substrate 10 that the p that illustrates herein mixes, contra-doping zone 15 is that n mixes.This contra-doping can realize by this way, and namely in contra-doping zone 15, the concentration of the second dopant material is higher than the concentration of the first dopant material (herein for example boron), and it is uniform in whole substrate 10 basically.Between the remainder of contra-doping zone 15 and substrate 10, consist of by this way the pn knot.At this, contra-doping zone 15 is the n zone in the example of Fig. 3, and the remainder of substrate 10 is p zones.
Oxide layer 20 also is shown at the subgraph of Fig. 3 in a), this oxide layer is arranged on the first surface 11 of substrate 10.Be used for the follow-up dry etching process that will carry out or the rich process of executing such as the follow-up oxide layer that illustrates 20 as dura mater.
Subgraph b at Fig. 3) in, oxide layer 20 is during this period by means of the photoetching method structuring.In this way, the first surface 11 of substrate 10 comes out in the position of expectation cavity, and in still oxide dura mater 20 coverings of the outside of the position of expecting cavity.
Figure c in the flow process of Fig. 3) in, utilize positive glue or negative glue implement rich execute process after, with cross section substrate 10 is shown.Rich execute process and form interim cavity 40, they for example can dark 300 μ m, begin to measure from the first surface 11 of substrate 10.Rich execute process or other suitable dry etching process illustrates the first subprocess that is used to form the method for at least one cavity according to embodiment.Interim cavity 40 has respectively bottom 41.Cavity 40 also has sidewall 42, and this sidewall is substantially perpendicular to the first surface 11 of substrate 10 at this.
Oxide spacer deposition/anisotropic etching the state afterwards of implementing has been shown the subgraph d at Fig. 3).At first at the first surface 11 of substrate 10 with at the surface deposition protective material 30(of interim cavity 40 be: the oxide spacer material) herein.By means of protective material 30 is carried out the etching of local anisotropy, particularly again expose the section 41a of section of the bottom 41 of interim cavity 40.In addition, in the example that illustrates herein, bottom 41 also has the section 41b of section that does not expose.The thickness of the protective material that deposits can be between 0.5 μ m to 10 μ m, for example 2.5 μ m.The protective material 30 among the section 41a of section that exposes has been removed in anisotropic etching basically fully so that (at least piecemeal) thus expose the bottom 41(of this interim cavity 40 and expose base material).The deposition of protective material and its (anisotropy) etching are illustrated in semiconductor base 10 inner another step or the processing steps that form the method for cavity.
Subgraph e at Fig. 3) with viewgraph of cross-section (anisotropy and electrochemically) is shown in and implements state after the pn etching, this pn etching illustrates another step of the recommend method that is used to form cavity.Remove subsequently the process of oxide layer too at subgraph d) and state e) between finish.The sidewall of existing in type cavity 45 has First section 42, and this section is at subgraph b) and c) between the dry etching process in form.These sections 42 extend through and stem from etched second section 47 of pn.Corresponding therewith, second section 47 of cavity 45 sidewalls needn't be extended perpendicular to substrate surface 11 basically, but consists of with it angle, the angle between 40 ° to 65 ° for example, for example particularly 54.7 °.The First section 42 of the sidewall of cavity 45 typically and first surface 11 be formed in angle between 70 ° and 110 °, particularly between 85 ° and 95 °.
Cavity 45 has bottom 46, this bottom and contra-doping zone 15 adjacency.Therefore this appearance is that etch stop has been described in contra-doping zone 15 for the pn etching.
Possible and the embodiment that is chosen as example herein of the present invention pressure-and the acceleration transducer place be implemented on the common sensor component plane.At this, the cavity of chip back surface by means of described anabolic process be etched to＜100〉silica-based material in.At this moment, total depth may change, and common etch depth depends on the thickness of the cantilever of required diaphragm thickness or acceleration transducer, and be approximately 375 μ m or 400 μ m at this this moment.Etch depth also depends on original wafer thickness.
In addition, also consider with two antiparallel spring mass system cavitys of packing into each other, in order to so-called twin shaft acceleration measurement system is provided.On the basis of use according to the anabolic process of embodiment, these two structural details are integrated in the cavity to save the mode of taking up an area the space, and utilize the also structuring of this process.
According to area, the size of acceleration transducer is less, because anabolic process can realize the mass thickness that conforms to the silicon wafer mass thickness.
Contra-doping zone 15 in the substrate 10 utilizes the second dopant material moulding, by changing the injection degree of depth of this second dopant material, can provide the different etch stop degree of depth for the pn etching.In this way, for example can in same pn etching process, produce the cavity of a plurality of different depths.In addition, can also make by this way the cavity 45(Fig. 3 e that has formed) bottom 46 structurings, structure, the recess by projection for example is set or leave a blank.
Fig. 4 illustrates technological process according to embodiment with schematic cross-sectional view.Identical with Fig. 3, or from substrate 10, this substrate has p and mixes by means of the B Implanted atom.For example, can therefore reach the resistivity that is about 3 Ω cm.Layer 20 is oxide hardmask.Substrate is near the second substrate surface 12 or directly have contra-doping zone 15 near this substrate surface, mixes so this zone is n.
Subgraph b at Fig. 4) implemented the photoetching to oxide hardmask 20 in, so that removed oxide hard mask 20 at the empty cavity position place of two expections.
Subgraph b at Fig. 4) and implemented between the state c) rich to execute process, this process causes forming the interim cavity 40 with substantially vertical sidewall 42 and respective base 41.For example can in so-called AVIZA method, realize the rich process of executing by the etch depth of 200 μ m.
The subgraph d of Fig. 4) structure that substrate 10 is shown and realizes during this period with cross section accordingly, has been arranged protective material 430 at the sidewall of interim cavity 40.This for example can realize by polymer deposition.The polymer of deposition or the thickness of protective material 430 can be between 150nm to 500nm, and end at equally in the AVIZA reactor.Can notice that the rich process of executing of implementing in advance typically after all arranges polymer deposition at the sidewall of the interim cavity 40 that forms gradually.
Next the method proceeds pn etching (chemical etching), makes thus interim cavity 40 expand as especially final cavity 45 aspect the degree of depth.At this, the sidewall 42 of interim cavity 40 proceeds to contra-doping zone 15 by means of the side wall portion section 47 that tilts to extend.Reach contra-doping zone 15 o'clock, the pn etch stop, and final cavity 45 has cavity bottom 46 in this position.
Fig. 5 illustrates the schematic cross-sectional view of two cavitys, and these two cavitys are to form by means of the method according to embodiment.These cavitys have the total depth d that begins from substrate surface, and from then on these two cavitys begin basad middle extension.On substrate surface, cavity has lateral spread w.Until depth d 1, the sidewall of cavity keeps about 95 ° angle with respect to substrate surface.Therefore, cavity increases and slightly enlarges along with the degree of depth.Rich do not execute process and will cause this expansion if arrange best.Polymer deposition rate and silicon rate of etch must accurately be set each other, in order to obtain vertical side.Yet be noted that and only have a small amount of application to need (being close to) accurately vertical side.Use for many other, if it is just enough to form approximately perpendicular side (for example having the angle between 80 ° and 100 °).Lateral spread reaches maximum w1 when the degree of depth is d1.Section's section corresponding to depth d 1 typically comes from enforcement dry etching method or the rich etching process of executing.From depth d 1, the lateral spread of cavity increases along with the degree of depth and reduces, and finally reaches numerical value w2 in cavity bottom.In the depth bounds of d1 to d, cavity sidewalls and substrate surface are formed on the angle between 40 ° and 65 °.Can notice that the bottom of right side cavity has the structure that can be used in micro electromechanical structure.
Compare with Fig. 5, Fig. 6 illustrates the schematic cross-section of passing two cavitys, and these two cavitys are to form by means of anabolic process, yet do not deposit protective material between dry etching and chemical etching.In addition, different from example shown in Figure 5 with the ratio of the formed degree of depth of chemical etching process by the dry etching process.Particularly in example shown in Figure 6, chemical etching is preponderated, and then opposite among Fig. 5, dry etching is preponderated.Because the sidewall of interim cavity is not protected the protection of material during chemical etching, so these sidewalls also can be corroded by chemical etching.Cavity has its maximum lateral spread w1 when depth d 1.On this position, remaining wall thickness less between two cavitys.Therefore, when use forming the process of cavity shown in Figure 6, although the micro electromechanical structure that is arranged in the respective cavities bottom section can allow this of lateral spacing to reduce fully, the lateral spacing between two cavitys can't further reduce.Can notice, win and execute the degree of depth that etching process approximately is implemented into 2x d1.Compare with the configuration among Fig. 5, the w1/w2 large percentage in the configuration shown in Figure 6, this causes, and it is more unfavorable to utilize in the situation comparison diagram 5 according to the side direction area in the configuration of Fig. 6.Execute process and only form cavity by means of the pn etching if remove the rich of the dry etching of beginning or beginning fully, the area that then can realize utilizes situation even can be more unfavorable.
Fig. 7 illustrates the schematic cross-sectional view of passing MEMS, and this MEMS has the layer structure that is made of three wafers.Master wafer 710 is arranged in as sandwich between channel wafer 780 and the cover wafers 790.Structure shown in Fig. 7 consists of pressure sensor and the acceleration transducer of combination.For this reason, master wafer 710 has pressure-sensitive diaphragm 760, this diaphragm and cavity 745 bottoms 746 adjacency.Form cavity 745 by means of the method that is used to form cavity according to several at least embodiment.In a side relative to pressure-sensitive diaphragm 760 and cavity 745, cover wafers 790 has cavity 791, and this cavity is as tonometric balancing gate pit or reference pressure chamber.For this reason, master wafer 710 and cover wafers 790 are connected to each other with gastight manner in cavity 791 scopes at least.In channel wafer 780, be provided with raceway groove 781, this raceway groove leads to cavity 745, and this cavity is connected with the surrounding environment of pressure sensor, regnant pressure can act on the diaphragm 760 in the surrounding environment so that make, and makes where necessary this diaphragm deformation.May comprise embedded resistor 761 in the diaphragm 760, the purpose that disposes this resistance is that the diaphragm deformation that will be determined by pressure is converted into resistance variations, can analyze this resistance variations by the mode of electricity.The thickness of diaphragm 760 can be at for example 5 μ m to 20 μ m, particularly 10 μ m, and wherein these numerical value only are exemplary, and never are limited to this.
On the pressure sensor right side, the acceleration transducer parts of micro-electro-mechanical sensors system have been designed.
Cover wafers 790 is connected with master wafer 710 by means of anode (wafer) pressure welding (Bonden) 795.
Acceleration transducer has mass 750, and this mass is connected with the substrate of master wafer 710 by cantilever (Kragarm) 751.Cantilever 751 its towards a side of cavity 745 by cavity bottom 746 limited boundaries.Because the suspension effect of cantilever, mass 750 can swing, thereby and can make a response to acceleration.Can measure by means of sheet resistance 748 distortion of cantilever 751.Another cavity 745 is arranged on mass 750 right sides.This another cavity 745 is by master wafer 710, until it reaches one in the cavity 791 of design in cover wafers 790.Being arranged in mass 750 left sides is connected cavity 745 and also connects with the cavity 782 that is connected in channel wafer 780 with the right side.
Realize by main contacts 702 and flush type horizontal lead wire 704 through the pressure sensor of combination and the electrical connection of acceleration transducer.For example, the thickness of master wafer 710 can be about 400 μ m, and the thickness of cover wafers and channel wafer 790,780 is about 350 μ m.
Can also identify in Fig. 7, the cavity 745 in the master wafer 710 has sidewall, and this sidewall has First section and second section.The First section is substantially perpendicular to the surface of master wafer 710 and extends.On the contrary, extend with the off plumb angle on the surface of second of sidewall section and master wafer 710.This is particularly favourable to the mass 750 of acceleration transducer, because, to compare with method before, mass can keep having the lateral dimensions of comparativity, yet can also take full advantage of whole wafer thickness simultaneously.Thus, the mass penalty of element 750, lateral dimensions that perhaps can selection of small when quality remains unchanged substantially.
Fig. 8 exemplarily illustrates the physical dimension of sensor device, and the device of Fig. 7 is integrated in this sensor device.Sensor device has housing 809 and joint 804a, 804b.In enclosure interior, structure shown in Figure 7 and control chip and/or analysis chip 800 have been arranged.Chip 800 by means of be electrically connected 806,807 with one of them contact 804b with main contacts 702(Fig. 7 of master wafer 710) be connected.Device shown in Fig. 7 is encapsulated in housing 809 inside, as passing through shown in the packaging body 808.The channel 781 of channel wafer 780 utilizes hole 881 to carry out UNICOM, and this hole design is in housing 809.Contact 804a and contact 804b electric insulation, and for example be grounding connection.Can notice that except two contact 804a that illustrate, 804b can also design other contact herein, so that for sensor device power supply and can draw the signal of measuring.
Fig. 9 illustrates the schematic perspective viewgraph of cross-section of four interim cavitys.At this, these four interim cavitys have the plane of rectangle, wherein, yet also can consider other shape.Sidewall and the angle between the substrate surface of interim cavity are slightly larger than 90 °.
Figure 10 illustrates the viewgraph of cross-section of the schematic perspective of two final cavitys, and this cavity is to execute etching by means of rich after the oxide hardmask structuring that does not have polymer deposition, and (after removing glue) forms by means of the pn etching.As described in conjunction with Fig. 6, lack the result that polymer deposition causes and be, not protected at follow-up pn during etching at the rich sidewall of executing the interim cavity that during etching forms.Thus, originally almost vertical surperficial side wall portion section some can be etched, until reach be effective as etch stop and work＜111〉crystal face.
In the bottom of right side cavity, can see that indication acceleration transducer mass elements 750(sees Fig. 7) structure.
Figure 11 illustrates the schematic diagram of etching model, can realize this etching model by means of the combination of different engraving methods or different engraving method.Suppose to form the cavity with depth d, and the combination of whole engraving method or engraving method can be with substrate surface as identical erosion surface.
At first considering can be by means of the etching model of pn etching realization.Based on the sidewall that relatively flat extends, the cross section of formed cavity increases along with the degree of depth and reduces.In the example shown in Figure 11, utilize cavity that the pn etching forms to only have very little lateral spread during for d in the degree of depth.
In addition, Figure 11 also illustrates two by the rich etching model of executing the various combination process that etching and pn etching consist of.The difference of these two anabolic processes is its rich shared ratio of etching of executing.
In the first anabolic process, at first execute process with depth d by means of rich Bosch1The cavity that etching is interim.It is therefore, rich that to execute the etching proportion be d Bosch1/ d.In the second variant scheme, rich to execute the etching proportion higher, so that the depth d of the interim cavity that forms by this way Bosch2D Bosch1(in this case, the rich etching proportion=d that executes Bosch2/ d).
In both cases, next all to carry out the pn etching.At this moment, can distinguish in two kinds of situation: in the first situation, the sidewall of interim cavity is protected by corresponding protective material at the pn during etching, and therefore substantially is not etched.In the second situation, sidewall is not protected at the pn during etching, and therefore can change equally, and this causes the cavity in this zone to be widened.
Also set as an example following numerical value: d=400 μ m, d Bosch1=200 μ m and d Bosch2=300 μ m.Be stressed that the numerical value that must will hereinafter provide is regarded example as.
Figure 11 illustrates, by means of the first anabolic process, cavity its bottom to extend laterally with only comparing the numerical value that can increase through pn etched cavity be 2w AIn conjunction with the Numerical examples that provides above, w A=140 μ m.(win and execute etching until depth d in the second anabolic process Bosch2) situation under, the bottom of final cavity with only compare even be increased to 2 (w through pn etched cavity A+ w B).
In conjunction with the numerical value that provides above, w BFor example be 72 μ m in this case.
Just in MEMS technique, cavity size has been determined in extending laterally that cavity bottom is required, and particularly the maximum of cavity extends laterally.Figure 11 illustrates, and the high as far as possible rich etching ratio of executing can be brought benefit on the one hand at this.In practice, usually make every effort to utilize at the rich better area of executing the etched different installation cost of etching and pn and process cost and can realizing and find half measure between the situation.In addition, be noted that with rich and execute etching and compare that the pn etching typically provides the etch stop that can control better, thereby and allow more accurately to make the MEMS structure.
In the first anabolic process, cavity bottom extend laterally Billy with the rich little 2 (w that extend laterally that execute interim cavity that etching forms B+ w C).Again in conjunction with the numerical value that provides above, w CBe 68 μ m at this.
Figure 11 also illustrates, when sidewall when the pn during etching is not subject to the protection of suitable protective material, the sidewall of interim cavity is in the variation of pn during etching.At the first anabolic process (until d Bosch1richly execute etching) in, cavity has enlarged 2w at lateral D, this w wherein DBe 72 μ m in conjunction with the numerical value that provides above.At the second anabolic process (until d Bosch2richly execute etching) in, maximum extends laterally with respect to extending laterally of interim cavity and enlarges 2 (w D+ w E), on hypothesis in the situation of the numerical value that provides, this w wherein EBe 32 μ m.
Following table has been summed up the exemplary value of size shown in Figure 11.
d 400μm
d Bosch1 200μm
d Bosch2 300μm
w A 140μm
w B 72μm
w C 68μm
w D 72μm
w E 32μm
The details viewgraph of cross-section that Figure 12 illustrates the cavity sidewalls top edge (perhaps; in the situation that respective change occurs; exemplary details viewgraph of cross-section as string diagram) electron micrograph wherein, can be found out protective material 30 on the surface of substrate 10 and the sidewall.As shown in Figure 12, the protection oxide thickness with protective material 30 is chosen to be about 2500nm.Typically, must select like this thickness, namely at bottom and the inferior horn place of interim cavity 40 enough protection oxide thickness be arranged, in order in follow-up plasma etch processes, avoid the surface etching to inferior horn or sidewall.The protection oxide thickness of layer 30 is inconsistent: the protection oxide thickness on the sidewall is than thin on the basement top.On basement top 11, between protection oxide layer 30 and silicon base 10, also comparison diagram 3 of oxide layer 20(is arranged).In order to show more clearly the boundary between substrate 10 shown in broken lines among Figure 12, oxide layer 20 and the protection oxide layer 30.
Although coupling apparatus has been described some aspects, still to the description of correlation method, this point is self-evident in these aspects, so the chunk of device or structural detail also design as corresponding method step or as the feature of method step.Similarly, associated methods step or also described corresponding chunk or details or the feature of related device as the aspect that method step is described.Individual other or all method steps can pass through hardware instruments (or under condition of using hardware instruments), and for example microprocessor, programmable computer or electronic circuit are implemented.In certain embodiments, some or a plurality of most important method step can be implemented by this instrument.
Embodiment described above has just illustrated principle of the present invention.The modification of device described here and details and variant scheme are understandable for other professional, and this point is self-evident.So, present invention is designed to be and limited by the protection domain of claims, and be not subjected to limit according to the specific detail that the description of embodiment and explanation have been set forth.
From the detailed description of preamble, can find out, the various features among the embodiment be organized into groups jointly.This publicity pattern should not be understood to such intention, and namely desired embodiment need to be than the more feature of clearly being mentioned in the respective right requirement.Or rather, original content may appear in the Partial Feature of independent disclosed embodiment.Thereby claims should be listed in the description, and wherein, each claim self can be used as an independent embodiment.Although each claim self can be used as independent embodiment, still be noted that namely-although dependent claims can relate to particular combinations with one or more claims-other embodiment and also can comprise or contain the combination of theme of this dependent claims and any other dependent claims or the combination of any feature and other subordinate and independent claims in each claim.At this, as long as no clearly indicating to adopt particular combinations, just recommend foregoing this combination.Be contemplated that also that in addition even claim self does not directly depend on independent claims, the feature of claim also can be listed in any other independent claims.
In addition, need to prove that disclosed method can realize by device in description or claim, this device has for the corresponding steps of this method of enforcement or the instrument of behavior.
In addition, in certain embodiments, single step/behavior can be divided into a plurality of substeps or comprise a plurality of substeps.This substep can be included in the disclosure of single substep and be the part of the disclosure of single substep.

Claims (29)

1. one kind is used in the inner method that forms at least one cavity of semiconductor base, and described method comprises:
From semiconductor-based basal surface, at the empty cavity position place of at least one expection described semiconductor base is carried out dry etching, in order to obtain at least one interim cavity;
In view of follow-up wet etch process deposits protective material at the cavity surface place of described semiconductor-based basal surface and described at least one interim cavity;
At least remove described protective material at a section section place of the bottom of described at least one interim cavity, in order to expose described semiconductor base; With
Described the section place of exposing in the described bottom of described at least one interim cavity carries out chemical etching to described semiconductor base.
2. method according to claim 1 also comprises: before described dry etching, be the described dry etching deposition oxide mask of described semiconductor base.
3. method according to claim 1 and 2, wherein said dry etching comprise at least one in the following process: reactive ion etching (RIE), deep reaction ion(ic) etching (DRIE) and win the process of executing.
4. each described method in 3 according to claim 1, wherein, described protective material is oxide, silica or isolation oxide.
5. each described method in 4 according to claim 1, wherein, the described deposition of described protective material comprises the combination of plasma deposition, thermal oxide deposition or described plasma deposition and described thermal oxide deposition.
6. each described method in 5 according to claim 1, wherein, the described removal of described protective material comprises plasma etching.
7. each described method in 6 according to claim 1, described method also comprised deposition mask and makes the described mask structure of deposition before the described removal of described protective material.
8. each described method in 7 according to claim 1 wherein, is that described chemical etching uses the alkali etching medium.
9. each described method in 8 according to claim 1, wherein, described chemical etching provides the etch stop technology.
10. each described method in 9 according to claim 1, also comprise: implement photoetching process and injection subsequently, so that the depth in described semiconductor base inside forms the pn knot, wherein, the described degree of depth of described pn knot is the function of the described bottom depth desired of described at least one cavity.
11. each described method in 10 according to claim 1, wherein said chemical etching comprises very first time section and the second time period, and in the section of the described very first time, the voltage that is applied on the described semiconductor base raises therein.
12. each described method in 11 according to claim 1, wherein, comprise the combination of the aqueous solution, hydrazine, potassium hydroxide (KOH) or the above-mentioned substance of TMAH (TMAH), ethylenediamine and catechol (EDP) for the etching media of described chemical etching.
13. one kind is used in the inner method that forms at least one cavity of semiconductor base, described method comprises:
Implement richly to execute process at the substrate surface of described semiconductor base, in order to form at least one interim cavity;
Implement the PCVD of silica in the cavity surface of described substrate surface and described at least one interim cavity;
At least at a section section place of the bottom of described at least one interim cavity described silica is carried out anisotropic etching; With
Be subjected in use under the condition of pn etch stop of electrochemical control, described semiconductor base is carried out electrochemistry, anisotropic etching, wherein, at least carry out described electrochemistry, anisotropic etching at described section place of the described bottom of described at least one interim cavity, and widen in this way described at least one interim cavity.
14. method according to claim 13 also comprises: rich be the described rich process deposition oxidation mask of executing before executing process described.
15. according to claim 13 or 14 described methods, wherein, the anisotropic described etching of described silica comprises plasma etching.
16. each described method also comprises in 15 according to claim 13: deposition mask before the anisotropic described etching of described silica, and make the described mask structure of deposition.
17. each described method in 16 wherein, is that the alkali etching medium is used in electrochemistry, anisotropic described etching according to claim 13.
18. each described method also comprises in 17 according to claim 13: implement photoetching process and injection subsequently, so that the degree of depth in described semiconductor base inside forms the pn knot, wherein, the described degree of depth of described pn knot is according to the depth desired of the described bottom of described at least one cavity and selected.
19. each described method in 18 according to claim 13, wherein, electrochemistry, anisotropic described etching comprise very first time section and the second time period, and in described very first time section, the voltage that is applied on the described semiconductor base raises.
20. each described method in 19 according to claim 13, wherein, comprise the combination of the aqueous solution, hydrazine, potassium hydroxide (KOH) or the above-mentioned substance of TMAH (TMAH), ethylenediamine and catechol (EDP) for electrochemistry, anisotropic described etched etching media.
21. the method for the production of the micro mechanical sensor system has following characteristics:
The semiconductor base of doping is provided;
In the mix zone of at least one contra-doping of the described semiconductor base inner counter of mixing; With
Implement structurized process for the production of micro electromechanical structure in described semiconductor base and at substrate surface, wherein, at least a portion of the described micro electromechanical structure of setting extends in the zone of described contra-doping; With
It is described in the inner method that forms at least one cavity of described semiconductor base to implement according to claim 1 in 20 each, wherein, the described part adjacency of the zone of described cavity and described contra-doping and described micro electromechanical structure, described part extends in the zone of described contra-doping.
22. a MEMS comprises:
Semiconductor base with surface;
The cavity that in described semiconductor base, forms, wherein, the sidewall of described cavity comprises described surface second section far away of First section and the described substrate of distance, wherein, the described surface of described First Duan Yiyu is 70 to be spent to the first angle extension between 110 degree, and described second described surface of Duan Yiyu is 40 degree to the second angle extension between 65 degree.
23. MEMS according to claim 22 also comprises the pn knot that is positioned at described semiconductor base described bottom inner, that be in a described cavity side relative with described cavity.
24. according to claim 22 or 23 described MEMSs, wherein, the described First section of the described sidewall of described cavity more close surface for the described surface of described semiconductor base, and described second section is darker in the position of described semiconductor base inside.
25. each described MEMS in 24 according to claim 22, wherein, described MEMS comprises: sensor, actuator, pressure sensor, acceleration transducer or dynamo-electric converter.
26. each described MEMS in 25 according to claim 22, wherein, the basal part section between the described surface of the described bottom of described cavity and described semiconductor base or other surface consists of diaphragm, beam, cantilever or the mechanical quality element of described MEMS.
27. each described MEMS in 26 according to claim 22, wherein, described substrate mainly comprises silicon.
28. each described MEMS in 27 according to claim 22, wherein, described sidewall has end difference.
29. each described MEMS in 28 according to claim 22, wherein, the aspect rate of described cavity is at least 1.5.
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