CN103377607A - Bridge connection integrated circuit - Google Patents
Bridge connection integrated circuit Download PDFInfo
- Publication number
- CN103377607A CN103377607A CN2012101351557A CN201210135155A CN103377607A CN 103377607 A CN103377607 A CN 103377607A CN 2012101351557 A CN2012101351557 A CN 2012101351557A CN 201210135155 A CN201210135155 A CN 201210135155A CN 103377607 A CN103377607 A CN 103377607A
- Authority
- CN
- China
- Prior art keywords
- signal
- level
- integrated circuit
- specification limit
- bridge joint
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Landscapes
- Tests Of Electronic Circuits (AREA)
Abstract
A bridge connection integrated circuit is suitable for being connected between a grid driver to be tested and a testing machine in a coupling mode and comprises a plurality of first detecting units and a logic unit. A counterpart in each of multiple grid drive signals according to the grid driver to be tested in the first detecting units determines whether the corresponding grid drive signal satisfies a first specification range or not, and produce first detecting signals according to the determining result. The logic unit is connected to the first detecting units in a coupling mode, and responds the first detecting signals supplied by all the first detecting units to produce test result signals. The test result signals are suitable for being provided for the testing machine.
Description
Technical field
The present invention relates to a kind of bridge joint integrated circuit, and be particularly related to a kind of bridge joint integrated circuit that is coupled between gate drivers to be measured and tester table.
Background technology
In the now epoch that development in science and technology is maked rapid progress, liquid crystal display is used in the various electronic products widely, for example be TV, mobile phone, personal digital assistant (Digital Personal Assistant, PAD), multimedia player and satellite navigation machine etc.In general, liquid crystal display uses gate drivers that gate drive signal is provided more, comes each the row display pixel in the activation display sequentially, and the data of correspondence are write wherein.
Development along with technology, the size of liquid crystal display and resolution are all increasing step by step, so that the number of pins that is used in gate drivers wherein is also along with increase, and also need to upgrade accordingly for the rear end board that gate drivers is tested, come the number of pins that day by day increases in response to gate drivers.So, often cause holding testing cost to improve after the gate drivers, and the situation of tester table production capacity deficiency.
Summary of the invention
The disclosure provides a kind of bridge joint integrated circuit, and it can be coupled between at least one gate drivers to be measured and the tester table.This bridge joint integrated circuit can comprise one or more testing circuit, each testing circuit according to a plurality of output signals of a gate drivers to be measured wherein one of them, judge whether it satisfies a specification limit, and produce the first detection signal according to judged result.This output signal for example can comprise gate drive signal, or is the initial pulse output signal, or both.This bridge joint integrated circuit can also comprise logical block, provide this first detection signal to produce the test result signal in response to each testing circuit and offer tester table, one or more output signal of coming gate drivers to be measured is provided via wherein a plurality of the first detecting units is by this carried out testing advanced operation, so that the test result signal is provided to tester table.Accordingly, compared to the traditional test scheme, this bridge joint integrated circuit has and can effectively carry out testing advanced operation, reduce the required number of pins of tester table and the advantage of gate drivers testing cost for gate drivers.
According to one side of the present disclosure, a kind of bridge joint integrated circuit is proposed, be suitable for being coupled between gate drivers to be measured and the tester table, comprising a plurality of the first detecting units and logical block.Each is judged whether corresponding gate drive signal satisfies the first specification limit, and produces the first detection signal according to judged result according to the corresponding person in the middle of a plurality of gate drive signals of gate drivers to be measured in the middle of these a little first detecting units.Logical block couples so far a little the first detecting units, and produces the test result signal in response to the first detection signal that each first detecting unit provides, and the test result signal is suitable for offering tester table.
According to another aspect of the present disclosure, a kind of bridge joint integrated circuit is more proposed, be suitable for being coupled between at least one gate drivers to be measured and the tester table, comprise: a plurality of the first detecting units, corresponding person in the middle of a plurality of gate drive signals of one in the middle of central each this at least one gate drivers to be measured of foundation, judge whether this correspondence gate drive signal satisfies one first specification limit, and produce one first detection signal according to judged result; One second detecting unit is used for reception and judges whether an initial pulse output signal of one in the middle of this at least one gate drivers to be measured satisfies one second specification limit, and produces one second detection signal according to judged result; One logical block is coupled to this a plurality of the first detecting units, and this first detection signal and this second detection signal that provide in response to each these first detecting unit produce a test result signal; And a decoding unit, producing a plurality of passage enable signals, these a plurality of passage enable signals are respectively applied to make this a plurality of first detecting units respectively activations or anergy.
According on the other hand of the present disclosure, a kind of bridge joint integrated circuit is proposed, be suitable for being coupled between at least one gate drivers to be measured and the tester table, comprise: one or more detecting unit, corresponding person in the middle of one or more output signal of one at least in the middle of central each this at least one gate drivers to be measured of foundation, judge whether this corresponding output signal satisfies a specification limit, and produce a detection signal according to judged result; And a logical block, being coupled to this one or more detecting unit, this detection signal that provides in response to this one or more detecting unit respectively produces a test result signal.
For there is better understanding above-mentioned and other aspect of the present invention, preferred embodiment cited below particularly, and cooperation accompanying drawing are described in detail below:
Description of drawings
Fig. 1 illustrates the calcspar of the test macro of the embodiment of the invention.
Fig. 2 illustrates the coherent signal sequential chart of the test macro of Fig. 1.
Fig. 3 illustrates the detailed block diagram of the bridge joint integrated circuit of Fig. 1.
Fig. 4 illustrates the detailed block diagram of the first detecting unit of Fig. 3.
Fig. 5 illustrates the detailed block diagram of multiplex's selector switch of Fig. 4.
Fig. 6 illustrates another calcspar of the test macro of the embodiment of the invention.
Fig. 7 illustrates the detailed block diagram according to the bridge joint integrated circuit of an embodiment Fig. 6.
Fig. 8 illustrates the detailed block diagram according to initial pulse output signal the second detecting unit of an embodiment Fig. 7.
Fig. 9 illustrates an again calcspar of the test macro of the embodiment of the invention.
[main element symbol description]
1,1 ', 2: test macro
100,100 ', 300-500: gate drivers to be measured
101,301,401: the initial pulse output pin
102,302,402: the direction of displacement pin
103,303,403: the initial pulse input pin
104,304,404: the clock pin
105_1-105_N, 305_1-305_N, 405_1-405_N: output pin
10,20,30,40,50: the bridge joint integrated circuit
11,21,31,41,51: the test result signal pins
13,23,33,43,53: the initial pulse input pin
14,24,34,44,54: the clock pin
15_1-15_X, 25_1-25_X, 35_1-35_X, 45_1-55_X, 55_1-55_X: input pin
1000,1000 ', 2000: tester table
U1_1-u1_X: the first detecting unit
U2: shift register cell
U3, u3 ': logical block
U4: decoding unit
CP1, CP3: the first comparator circuit
CP2, CP4: the second comparator circuit
Mx, Mx ': multiplex's selector switch
BF1, BF2, BF3, BF4: output buffer
CX, CX_SPO: control circuit
IN1, IN2: input end
ON: output terminal
INV1, INV2: phase inverter
SW1, SW2: switch
SH: level shifter
U5: the second detecting unit
Embodiment
Please refer to Fig. 1, it illustrates the calcspar of the test macro of the embodiment of the invention.Test macro 1 comprises bridge joint integrated circuit 10, and it can be coupled between gate drivers 100 to be measured and the tester table 1000.Tester table 1000 for example can provide initial pulse input signal SPI, clock signal clk and direction of displacement signal SD (shift direction), with driving grid driver 100, and the gate drive signal that it provides is tested.
Bridge joint integrated circuit 10 comprise initial pulse input signal pin 13, test result signal pins 11, clock pin 14 and X input pin 15_1,15_2 ..., 15_X, wherein X is the natural number greater than 1.Clock pin 14 and initial pulse input signal pin 13 be receive clock signal CLK and initial pulse input signal SPI respectively.Give one example, X equals N, and X input pin 15_1-15_X receives respectively the gate drive signal OUT_1-OUT_N that gate drivers 100 to be measured is exported.10 couples of gate drive signal OUT_1-OUT_N of bridge joint integrated circuit carry out testing advanced operation, and provide according to this test result signal D_OUT to tester table 1000.
Please refer to Fig. 3, it illustrates the detailed block diagram of the bridge joint integrated circuit of Fig. 1.For instance, bridge joint integrated circuit 10 comprise X the first detecting unit u1_1, u1_2 ..., u1_X, shift register cell u2 and logical block u3.Shift register cell u2 carries out shifting function in response to initial pulse input signal SPI to clock signal clk, with produce control signal CTRL_1, CTRL_2 ..., CTRL_X comes the first detecting unit u1_1-u1_X is controlled.For instance, shift register cell u2 carries out the operation identical in fact with gate drivers 100 to be measured, to produce the control signal CTRL_1-CTRL_X identical in fact with gate drive signal OUT_1-OUT_N according to initial pulse input signal SPI and clock signal clk, wherein the oscillogram of control signal CTRL_1-CTRL_X can be as shown in Figure 2.
The central corresponding person of gate drive signal OUT_1-OUT_N that among the first detecting unit u1_1-u1_X each provides according to gate drivers 100 to be measured, judge whether corresponding gate drive signal OUT_1-OUT_N satisfies the first specification limit, and according to judged result produce the first detection signal D1, D2 ..., DX.For each first detecting unit u1_1-u1_X, whether it is for example high in fact or equal one scan activation level REF_1 in activation scan period of correspondence via the level of judging its corresponding gate drive signal OUT_1-OUT_N that receives, and whether low in fact or equal one scan anergy level REF_2 in the level of anergy non-scan period, judge whether corresponding gate drive signal OUT_1-OUT_N satisfies this first specification limit.For example, logical block u3 carries out the computing with (AND) to the first detection signal D1-DX, to produce test result signal D_OUT according to the first detection signal D1-DX accordingly.
Tester table 1000 judges according to the initial pulse output signal SPO that the first detection signal D_OUT and gate drivers to be measured 100 provide whether the operation of gate drivers 100 to be measured is normal.
More than comprehensive as can be known, via the performed testing advanced operation of bridge joint integrated circuit 10, the signal number of tester table 1000 required detections is reduced to 2 (test result signal D_OUT and initial pulse output signal SPO) by N+1 (N gate drive signal OUT_1-OUT_N and initial pulse output signal SPO), effectively to reduce the required number of pins of tester table 1000 and the testing cost of gate drivers to be measured 100.
Next circuit structure and the operation for each subelement in the bridge joint integrated circuit 10 is described further.
With regard to the first detecting unit u1_1-u1_X, it for example has identical in fact circuit structure and operation.Accordingly, next take wherein the 1st the first detecting unit u1_1 as example, come the operation of each the first detecting unit u1_1-u1_X is described further.
Please refer to Fig. 4, it illustrates the detailed block diagram according to the first detecting unit u1_1 of Fig. 3 of an embodiment.The first detecting unit u1_1 comprises first, second comparator circuit CP1, CP2, multiplex's selector switch Mx and output buffer BF1 and BF2.The first comparator circuit CP1 is the level and scanning activation level REF_1 of gate drive signal OUT_1 relatively, and provides comparison signal Scp1 according to comparative result.When the level of gate drive signal OUT_1 was higher than scanning activation level REF_1, comparison signal Scp1 is corresponding paramount signal level for example; When the level of gate drive signal OUT_1 was lower than scanning activation level REF_1, comparison signal Scp1 for example corresponded to low-signal levels.
The second comparator circuit CP2 is the level and scanning anergy level REF_2 of gate drive signal OUT_1 relatively, and provides comparison signal Scp2 according to comparative result.When the level of gate drive signal OUT_1 was higher than scanning anergy level REF_2, comparison signal Scp2 is corresponding paramount signal level for example; When the level of gate drive signal OUT_1 was lower than scanning anergy level REF_2, comparison signal Scp2 for example corresponded to low-signal levels.
Multiplex's selector switch Mx is in response to the corresponding person CTRL_1 in the middle of the control signal CTRL_1-CTRL_X, output comparison signal Scp1 is as selecting output signal Sco in during the activation of the gate drive signal OUT_1 of correspondence, and output comparison signal Scp2 wherein selects output signal Sco to be coupled to the detection output terminal N_OUT of the first detecting unit u1_1 as selecting output signal Sco in during the anergy of the gate drive signal OUT_1 of correspondence.Output buffer BF1 and BF2 are coupled to multiplex's selector switch Mx and detect between the output terminal N_OUT, in order to produce the first detection signal D1 according to selection output signal Sco.
Please refer to Fig. 5, it illustrates the detailed block diagram of multiplex's selector switch Mx of Fig. 4.For instance, multiplex's selector switch Mx comprises input end IN1, IN2, output terminal ON, phase inverter INV1, INV2, interrupteur SW 1, SW2 and level shifter SH.Level shifter SH reception control signal CTRL_1, and provide according to this control signal CTR after boosting, wherein control signal CTRL_1 and boost after control signal CTR in activation scan period of gate drive signal OUT_1, be activation, and be disabled in non-scan period in the anergy of gate drive signal OUT_1.For instance, the voltage swing of control signal CTRL_1 drops between high reference voltage VDD and the low reference voltage VSS, and the voltage swing of the control signal CTR after boosting drops between high reference voltage VP and the low reference voltage VN.Phase inverter INV2 receives the control signal CTR after boosting, and the control signal CTRB after anti-phase the boosting is provided accordingly.
Input end IN1 receives comparison signal Scp1, and is coupled to output terminal ON via interrupteur SW 1.Interrupteur SW 1 is activation in response to the control signal CTR after boosting in activation scan period of gate drive signal OUT_1, to provide comparison signal Scp1 to output terminal ON.In activation scan period of gate drive signal OUT_1, export accordingly comparison signal Scp1 as selecting output signal Sco by this.
Input end IN2 receives comparison signal Scp2, and is coupled to output terminal ON via phase inverter INV1 and interrupteur SW 2, and wherein phase inverter INV1 provides comparison signal Scp2B after anti-phase according to comparison signal Scp2.The control signal CTRB of interrupteur SW 2 after in response to anti-phase boosting is activation in the anergy of gate drive signal OUT_1 in non-scan period, to provide comparison signal Scp2B after anti-phase to output terminal ON.In non-scan period, export accordingly comparison signal Scp2 as selecting output signal Sco at the anergy of gate drive signal OUT_1 by this.
For instance, when gate drive signal OUT_1 satisfies this first specification limit, gate drive signal OUT_1 is activation and high in fact or equal to scan activation level REF_1 in activation scan period, and is disabled and low in fact or equal to scan anergy level REF_2 in non-scan period in anergy.So, comparison signal Scp1 and anti-phase after comparison signal Scp2B correspond to the activation level respectively at activation scan period and anergy in non-scan period, and select output signal Sco and the first detection signal D1 to correspond to constantly the activation level.In other words, when gate drive signal OUT_1 satisfied this first specification limit, the first detecting unit u1_1 in non-scan period, provided the first detection signal D1 that corresponds to the activation level at activation scan period and anergy constantly.
Please referring again to Fig. 3.The performed operation of the first detecting unit u1_1 in the aforementioned paragraphs, remaining first detecting unit u1_2-u1_X carries out identical in fact operation in the bridge joint integrated circuit 10, whether satisfy this first specification limit to detect respectively gate drive signal OUT_2-OUT_N, and produce accordingly the first detection signal D2-DX.When gate drive signal OUT_2-OUT_N satisfied this first specification limit, the first detecting unit u1_2-u1_X provided respectively the first detection signal D2-DX that corresponds to the activation level constantly.In other words, when gate drive signal OUT_1-OUT_N all satisfied this first specification limit, the first detection signal D1-DX had the signal waveform that continues to correspond to the activation level.
Relatively, in case there is any one gate drive signal OUT_1-OUT_N not satisfy this first specification limit, for example correspond to disable level or correspond to the activation level in the anergy of correspondence in non-scan period in activation scan period of correspondence, the first corresponding detection signal D1-DX corresponds to disable level in will be during correspondence.
Logical block u3 carries out and computing the first detection signal D1-DX, comes to produce test result signal D_OUT according to the first detection signal D1-DX.When gate drive signal OUT_1-OUT_N all satisfies this first specification limit, the first detection signal D1-DX corresponds to the activation level constantly, so that test result signal D_OUT corresponds to the activation level constantly constantly in the N of gate drive signal OUT_1-OUT_N section activation scan period, shown in the signal waveform of Fig. 2.In other words, tester table 1000 can be via judging that whether test result signal D_OUT corresponds to the activation level constantly in continuous N section activation scan period, judge accordingly whether gate drive signal OUT_1-OUT_N all satisfies this first specification limit.
In an example, bridge joint integrated circuit 10 also comprises decoding unit u4, its according to channel selecting signal Chan_Slc decoding produce passage enable signal EN1, EN2 ..., ENX, be respectively applied to optionally activation or disabled the first detecting unit u1_1-u1_X.Each first detecting unit u1_1-u1_X more for example comprises control circuit CX, and wherein the first detecting unit u1_1-u1_X controls the level of the first corresponding detection signal D1-DX respectively according to the passage enable signal EN1-ENX of correspondence.
Lift an operational instances, the number of the first detecting unit that has in the bridge joint integrated circuit 10 (=X) in fact greater than the number of 100 gate drive signals that can export of gate drivers to be measured (=N); In other words, bridge joint integrated circuit 10 only needs to come gate drivers 100 to be measured is carried out testing advanced operation with some of the first detecting units.In this operational instances, decoding unit u4 can provide passage enable signal EN1-ENX to come N the first detecting unit (for example being the first detecting unit u1_1-u1_N) in the activation bridge joint integrated circuit 10 and the remaining X-N of disabled the first detecting unit (for example being the first detecting unit u1_N+1-u1_X) according to channel selecting signal Chan_Slec.For instance, first detection signal (for example being the first detection signal DN+1-DX) of the X-N of this disabled the first detecting unit corresponds to the activation level constantly, so that the level of test result signal D_OUT is decided by the first detection signal (for example being the first detection signal D1 to DN) that individual the first detecting unit of the N of activation produces accordingly.
In the present embodiment, though only with bridge joint integrated circuit 10 in order to gate drive signal OUT_1-OUT_N is carried out testing advanced operation, and the situation that provides indication gate drive signal OUT_1-OUT_N whether to satisfy the test result signal D_OUT of this first specification limit is that example explains, yet the bridge joint integrated circuit 10 of present embodiment is not limited to this.In other examples, bridge joint integrated circuit 20 also can carry out preposition detection operation to gate drive signal OUT_1-OUT_N and initial pulse output signal SPO simultaneously, and provide and indicate simultaneously gate drive signal OUT_1-OUT_N whether to satisfy the test result signal D_OUT ' whether this first specification limit and initial pulse output signal SPO satisfy the second specification limit, such as the 6th to shown in Figure 8.
Furthermore, bridge joint integrated circuit 20 is wherein also to comprise initial pulse output signal pin 26, the initial pulse output signal SPO that is provided to receive gate drivers 100 ' to be measured with bridge joint integrated circuit 10 differences shown in Figure 3; Bridge joint integrated circuit 20 also comprises the second detecting unit u5 in addition, and its reception also judges whether the initial pulse output signal SPO of gate drivers 100 ' to be measured satisfies the second specification limit, and produce the second detection signal D_SPO according to judged result.For instance, whether the second detecting unit u5 is for example via high in fact or equal an initial activation level during the level of judging initial pulse output signal SPO is during output displacement, and whether low in fact or equal an initial anergy level in during non-output displacement, judge whether initial pulse output signal SPO satisfies this second specification limit.For instance, the second detecting unit u5 and each the first detecting unit u1_1-u1_X have close circuit structure and operation, also provide accordingly the second detection signal D_SPO to be controlled by enable signal EN_SPO as activation detects initial pulse output signal SPO.At this, and no longer it is given unnecessary details.
The first detection signal D1-DX that the second detection signal D_SPO that logical block u3 ' in the bridge joint integrated circuit 20 of present embodiment for example provides with reference to the second detecting unit u5 and the first detecting unit u1_1-u1_X provide produces test result signal D_OUT '.
When test result signal D_OUT ' corresponds to the activation level, represent that the gate drive signal OUT_1-OUT_N that gate drivers 100 ' to be measured provides all satisfies this first specification limit, and the second detection signal D_SPO that gate drivers to be measured 100 ' provides satisfies this second specification limit.In other words, tester table 1000 ' can correspond to the activation level constantly via judging during test result signal D_OUT ' is whether during activation scan period, disabled scan period and this output displacement of gate drive signal OUT_1-OUT_N, judges accordingly whether gate drive signal OUT_1-OUT_N all satisfies this first specification limit and whether initial pulse output signal SPO satisfies this second specification limit.
In the present embodiment, explain as example though only use situation that bridge joint integrated circuit 10 drives for a gate drivers 100 to be measured take test macro 1, yet the test macro 1 of present embodiment is not limited to this.In other examples, also can test for two or more gate drivers to be measured simultaneously in the test macro of present embodiment, as shown in Figure 9.
Further, comprise bridge joint integrated circuit 30,40 and 50 in the test macro 2, respectively gate drivers 300 to be measured, 400 and 500 is connected to tester table 2000, and respectively gate drivers 300-500 to be measured is carried out testing advanced operation, correspond to test result signal Dout_1, Dout_2 and the Dout_3 of gate drivers 300-500 to be measured with output.
The bridge joint integrated circuit of above-described embodiment is fit to be coupled between gate drivers to be measured and the tester table, comprising one or more detecting unit.This one or more detecting unit can comprise a plurality of the first detecting units, or one second detecting unit, or both.As previously mentioned, whether of can detect respectively in the middle of these signals of these first detecting units satisfies one first specification limit, and this second detecting unit then detects this initial pulse output signal and makes no one second specification limit that satisfies.In other words, this one or more detecting unit can according to one or more output signal of gate drivers to be measured one of them, judge whether it satisfies a specification limit, and produce detection signal according to judged result, wherein this one or more output signal for example can comprise a plurality of gate drive signals, or an initial pulse output signal, or both, and this specification limit for example can comprise the aforesaid first or second specification limit or both.In addition, the bridge joint integrated circuit of above-described embodiment also comprises logical block, this detection signal generation test result signal that provides in response to each detecting unit offers tester table, one or more output signal of coming gate drivers to be measured is provided via wherein one or more testing circuit is by this carried out testing advanced operation, so that test result is provided to tester table.Accordingly, compared to traditional test board solution, the bridge joint integrated circuit of present embodiment has and can effectively carry out testing advanced operation, reduce the required number of pins of tester table and the advantage of gate drivers testing cost for gate drivers.
In sum, although the present invention with preferred embodiment openly as above, so it is not to limit the present invention.Those skilled in the art without departing from the spirit and scope of the present invention, when being used for a variety of modifications and variations.Therefore, protection scope of the present invention is as the criterion when looking the appended claims person of defining.
Claims (21)
1. a bridge joint integrated circuit is suitable for being coupled between at least one gate drivers to be measured and the tester table, comprising:
A plurality of the first detecting units, corresponding person in the middle of a plurality of gate drive signals of one in the middle of central each this at least one gate drivers to be measured of foundation, judge whether this correspondence gate drive signal satisfies one first specification limit, and produce one first detection signal according to judged result; And
One logical block is coupled to this a plurality of the first detecting units, and this first detection signal that provides in response to each these first detecting unit produces a test result signal, and this test result signal is suitable for offering this tester table.
2. test interface circuit as claimed in claim 1, wherein this logical operation circuit carries out one and computing to these first detection signals.
3. test interface circuit as claimed in claim 1, wherein this first specification limit is defined by one scan activation level, and respectively this test interface module judges that the level of this corresponding gate drive signal during an activation be whether high in fact or equal this scanning activation level, and according to this judged result to produce this first detection signal.
4. test interface circuit as claimed in claim 3, wherein this first specification limit is also defined by one scan anergy level, and respectively this test interface module judges that the level of this corresponding gate drive signal during an anergy be whether low in fact or equal this scanning anergy level, and according to this judged result to produce this first detection signal.
5. bridge joint integrated circuit as claimed in claim 1, wherein each comprises in the middle of these a plurality of first detecting units:
One first comparator circuit in order to level and the one scan activation level of the gate drive signal that receives and relatively should correspondence, and provides one first comparison signal according to comparative result;
One second comparator circuit in order to level and the one scan anergy level of the gate drive signal that receives and relatively should correspondence, and provides one second comparison signal according to comparative result;
One multiplex's selector switch, receive this first and this second comparison signal, and select this first or second comparison signal to select output signal as one.
6. bridge joint integrated circuit as claimed in claim 5, wherein this multiplex's selector switch is in response to the corresponding person in the middle of a plurality of control signals, and during an activation of this corresponding gate drive signal with an anergy during in, export respectively this first and second comparison signal and select output signal as one, this selection output signal is coupled to one of this first detecting unit and detects output terminal.
7. bridge joint integrated circuit as claimed in claim 5, wherein respectively each comprises and also comprises an output buffer in the middle of these a plurality of first detecting units, be coupled between this multiplex's selector switch and this detection output terminal, in order to produce this first detection signal according to this selection output signal.
8. bridge joint integrated circuit as claimed in claim 5, also comprise a shift register cell, in response to an initial signal one clock signal is carried out shifting function, to produce a plurality of control signals, this multiplex's selector switch that these a plurality of control signals are controlled respectively these a plurality of the first detecting units is this first or second selection output signal of output.
9. bridge joint integrated circuit as claimed in claim 1 also comprises:
One decoding unit, decoding produces a plurality of passage enable signals according to a channel selecting signal, and these a plurality of passage enable signals are respectively applied to make these a plurality of first detecting units respectively activation or anergy.
10. bridge joint integrated circuit as claimed in claim 1, also comprise one second detecting unit, be used for reception and judge whether an initial pulse output signal of one in the middle of this at least one gate drivers to be measured satisfies one second specification limit, and produce one second detection signal according to judged result, wherein this second detection signal provides to this logical block, and this logical block also produces this test result signal according to this second detection signal.
11. bridge joint integrated circuit as claimed in claim 10, wherein this second specification limit is defined by an initial activation level, and this second detecting unit judges high in fact during whether this initial pulse output signal is during an output displacement or equals this initial activation level, and produces this second detection signal according to judged result.
12. bridge joint integrated circuit as claimed in claim 11, wherein this second specification limit is more defined by an initial anergy level, and this output second detecting unit more judges low in fact during whether this initial pulse output signal is during an output displacement or equals this initial anergy level, and produces this second detection signal according to judged result.
13. a bridge joint integrated circuit is suitable for being coupled between at least one gate drivers to be measured and the tester table, comprising:
A plurality of the first detecting units, corresponding person in the middle of a plurality of gate drive signals of one in the middle of central each this at least one gate drivers to be measured of foundation, judge whether this correspondence gate drive signal satisfies one first specification limit, and produce one first detection signal according to judged result;
One second detecting unit is used for reception and judges whether an initial pulse output signal of one in the middle of this at least one gate drivers to be measured satisfies one second specification limit, and produces one second detection signal according to judged result;
One logical block is coupled to these a plurality of first detecting units and this second detecting unit, and this first detection signal and this second detection signal that provide in response to each these first detecting unit produce a test result signal; And
One decoding unit produces a plurality of passage enable signals, and these a plurality of passage enable signals are respectively applied to make these a plurality of first detecting units respectively activation or anergy.
14. test interface circuit as claimed in claim 13, wherein this first specification limit is defined by one scan activation level, and respectively this test interface module judges that the level of this corresponding gate drive signal during an activation be whether high in fact or equal this scanning activation level, and according to this judged result to produce this first detection signal.
15. test interface circuit as claimed in claim 13, wherein this first specification limit is defined by one scan anergy level, and respectively this test interface module judges that the level of this corresponding gate drive signal during an anergy be whether low in fact or equal this scanning anergy level, and according to this judged result to produce this first detection signal.
16. bridge joint integrated circuit as claimed in claim 13, wherein this second specification limit is defined by an initial activation level, and this second detecting unit judges high in fact during whether this initial pulse output signal is during an output displacement or equals this initial activation level, and produces this second detection signal according to judged result.
17. bridge joint integrated circuit as claimed in claim 13, wherein this second specification limit is more defined by an initial anergy level, and this second detecting unit more judges low in fact during whether this initial pulse output signal is during an output displacement or equals this initial anergy level, and produces this second detection signal according to judged result.
18. a bridge joint integrated circuit is suitable for being coupled between at least one gate drivers to be measured and the tester table, comprising:
One or more detecting unit, in the middle of each according at least the central corresponding person of one or more output signal of one in the middle of this at least one gate drivers to be measured, judge whether this corresponding output signal satisfies a specification limit, and produce one first detection signal according to judged result; And
One logical block is coupled to this one or more detecting unit, and this first detection signal that provides in response to this one or more detecting unit respectively produces a test result signal.
19. bridge joint integrated circuit as claimed in claim 18, wherein this one or more output signal comprises a plurality of gate drive signals, and wherein this specification limit comprises by at least a defined specification limit in the middle of one scan activation level and the one scan anergy level.
20. bridge joint integrated circuit as claimed in claim 18, wherein this one or more output signal comprises an initial pulse output signal, and wherein this specification limit comprises by at least a defined specification limit in the middle of an initial activation level and the initial anergy level.
21. bridge joint integrated circuit as claimed in claim 18, wherein this one or more output signal comprises a plurality of gate drive signals and an initial pulse output signal, and wherein this one or more detecting unit comprises a plurality of the first detecting units, whether one that detects respectively in the middle of these signals satisfied one first specification limit, and one second detecting unit, detect this initial pulse output signal and make no one second specification limit that satisfies.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012101351557A CN103377607A (en) | 2012-04-28 | 2012-04-28 | Bridge connection integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012101351557A CN103377607A (en) | 2012-04-28 | 2012-04-28 | Bridge connection integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN103377607A true CN103377607A (en) | 2013-10-30 |
Family
ID=49462656
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2012101351557A Pending CN103377607A (en) | 2012-04-28 | 2012-04-28 | Bridge connection integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103377607A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111445841A (en) * | 2020-05-14 | 2020-07-24 | 京东方科技集团股份有限公司 | Display device and detection method thereof |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020005722A1 (en) * | 2000-06-14 | 2002-01-17 | Akira Morita | Signal supply apparatus and method for examining the same, and semiconductor device, electro-optical apparatus and electronic apparatus using the same |
| JP2003167265A (en) * | 2001-12-04 | 2003-06-13 | Advanced Display Inc | Liquid crystal display device and its inspecting method |
| CN101203800A (en) * | 2005-05-18 | 2008-06-18 | 统宝香港控股有限公司 | Liquid crystal display device test circuit, liquid crystal display device incorporating this, and liquid crystal display device test method |
| CN101430849A (en) * | 2007-11-09 | 2009-05-13 | 奇景光电股份有限公司 | Test device for display driving circuit |
| WO2013004041A1 (en) * | 2011-07-04 | 2013-01-10 | 深圳市华星光电技术有限公司 | Test circuit applicable to psva and array |
-
2012
- 2012-04-28 CN CN2012101351557A patent/CN103377607A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020005722A1 (en) * | 2000-06-14 | 2002-01-17 | Akira Morita | Signal supply apparatus and method for examining the same, and semiconductor device, electro-optical apparatus and electronic apparatus using the same |
| JP2003167265A (en) * | 2001-12-04 | 2003-06-13 | Advanced Display Inc | Liquid crystal display device and its inspecting method |
| CN101203800A (en) * | 2005-05-18 | 2008-06-18 | 统宝香港控股有限公司 | Liquid crystal display device test circuit, liquid crystal display device incorporating this, and liquid crystal display device test method |
| CN101430849A (en) * | 2007-11-09 | 2009-05-13 | 奇景光电股份有限公司 | Test device for display driving circuit |
| WO2013004041A1 (en) * | 2011-07-04 | 2013-01-10 | 深圳市华星光电技术有限公司 | Test circuit applicable to psva and array |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111445841A (en) * | 2020-05-14 | 2020-07-24 | 京东方科技集团股份有限公司 | Display device and detection method thereof |
| CN111445841B (en) * | 2020-05-14 | 2022-04-08 | 京东方科技集团股份有限公司 | Display device and detection method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103325349B (en) | Liquid crystal display | |
| CN104900211B (en) | A kind of gate driver circuit and its driving method, display device | |
| CN101442312B (en) | Analog to digital converter | |
| CN103400564A (en) | Dynamic power supply adjusting circuit, method for driving touch display, and drive system | |
| US20120188224A1 (en) | Data processing method, data driving circuit performing the same and display apparatus having the data driving circuit | |
| CN101937718A (en) | Bidirectional shift register | |
| CN104360781A (en) | Driving unit of touch control electrode, driving circuit, touch control panel and driving method | |
| US20230121542A1 (en) | Abnormality detection circuit | |
| TW200605010A (en) | TFT LCD source driver with built in test circuit and method for testing the same | |
| CN103151013A (en) | Gate drive circuit | |
| CN101859039B (en) | Touch detection method and flat panel display with embedded type touch panel | |
| US8643582B2 (en) | Driving apparatus for liquid crystal display | |
| CN101339338B (en) | Electric charge sharing mode LCD device, source drive device and electric charge sharing method | |
| TW201539418A (en) | Display panel and gate driver | |
| US6996203B2 (en) | Bidirectional shift register and display device incorporating same | |
| CN100359556C (en) | Source driver of built-in detecting circuit and its detecting method | |
| CN103377607A (en) | Bridge connection integrated circuit | |
| US20100091009A1 (en) | Display driving circuit and test method | |
| CN101645243B (en) | Shift register | |
| US8115786B2 (en) | Liquid crystal driving circuit | |
| TWI466098B (en) | Display driving method and associated driving circuit | |
| JP2005189834A (en) | Semiconductor device and its testing method | |
| CN102902426B (en) | Touch sensing device | |
| CN114220372B (en) | Level conversion circuit, power supply integrated circuit, display device, and level conversion method | |
| CN109461420B (en) | Display, display driving device and driving method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20131030 |