CN103390559A - Method for manufacturing semiconductor device - Google Patents
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- CN103390559A CN103390559A CN2012101434827A CN201210143482A CN103390559A CN 103390559 A CN103390559 A CN 103390559A CN 2012101434827 A CN2012101434827 A CN 2012101434827A CN 201210143482 A CN201210143482 A CN 201210143482A CN 103390559 A CN103390559 A CN 103390559A
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Abstract
The invention provides a method for manufacturing a semiconductor device. The method includes the steps of providing a semiconductor substrate, forming a dielectric layer on the semiconductor substrate, forming a high-K material layer on the dielectric layer, forming a covering layer on the high-K material layer, forming an amorphous silicon layer on the covering layer, carrying out ion implantation on the amorphous silicon layer, and forming a polycrystalline silicon layer on the amorphous silicon layer. According to the method for manufacturing the semiconductor device, the amorphous silicon layer covers the high-K material layer, the amorphous silicon layer is implanted with fluorocarbon, the annealing process enables implantation carbon and implantation fluorine to enter the high-K material layer, the fluorine can reduce dangling bonds in the high-K material layer, and then the drifting of the threshold voltage can be reduced; the carbon can reduce diffusion of doped ions in other doping areas, and therefore the stability of the semiconductor device can be effectively improved; in addition, the carbon implantation and the fluorine implantation are completed only through the one-time ion implantation process, therefore, the implantation dose can be easily controlled, and implantation damage can be reduced.
Description
Technical field
The present invention relates to integrated circuit and make field, relate in particular to a kind of manufacture method of semiconductor device.
Background technology
Along with the integrated level of semiconductor device is more and more higher, the voltage and current of semiconductor device need of work constantly reduces, and the speed of transistor switch is also accelerated thereupon, the semiconductor technology each side is required significantly to improve thereupon.Prior art processes has been accomplished the semiconductor device part of transistor and other kinds the thickness of several molecules and atom, forms semi-conductive material and has reached the limit of physical electrical characteristic.
Therefore, industry has found the material-high dielectric constant material (High-K Material) that has higher dielectric constant and better field effect characteristic than silicon dioxide,, in order to better separation grid and other parts of transistor, significantly reduces electrical leakage quantity.Simultaneously,, for compatible with high dielectric constant material, adopt metal material to replace original polysilicon as the grid conductive layer material, thereby formed new grid structure-metal gates lamination.Simultaneously, correspondence has produced rear grid technology (Gate-last), rear grid technology is for a kind of technology of making metal gate structure, is characterized in forming metal gates after completing Semiconductor substrate being carried out source region, the operation of drain region Implantation and high-temperature annealing process subsequently again.
Yet along with improving constantly of integrated level, in cmos circuit in the PMOS device Negative Bias Temperature Instability effect and in nmos device positive bias temperature instability effect more obvious.Negative Bias Temperature Instability (NBTI, Negative Bias Temperature Instability) effect is a kind of degradation phenomena that in cmos circuit, the PMOS pipe occurs under the effect of high temperature, high field and minus gate voltage, show as that gate current increases, threshold voltage to negative direction drift, sub-threshold slope reduce, the phenomenon such as mutual conductance and leakage current diminish.Same positive bias temperature instability effect is the degradation phenomena that in cmos circuit, the NMOS pipe occurs under the effect of high temperature, high field and positive grid voltage, show as equally that gate current increases, threshold voltage to negative direction drift about, the phenomenon such as sub-threshold slope reduces, mutual conductance and leakage current diminish.
The production process of Negative Bias Temperature Instability effect is mainly due to generation and the passivation of positive charge, be the generation of fixed positive charge in interface trapped charge and oxide layer and the diffusion process of diffusate, hydrogen and steam are two kinds of main matter that cause Negative Bias Temperature Instability.Traditional viewpoint thinks that its reason ascribes the PMOS pipe to and receive thermal excitation in the inversion layer hole under the effect of high temperature minus gate voltage, be tunneling to silicon and silicon dioxide interface, owing to there being a large amount of Si-H keys at interface, the hole of thermal excitation and the effect of Si-H key generate the H atom, thereby at interface, stay dangling bonds, and due to the unsteadiness of H atom, two H atoms will in conjunction with, form with hydrogen molecule discharges, and spreads to grid layer away from interface, thereby causes that the negative sense of threshold voltage drifts about.
In order to can be good at solving the electric leakage problem of semiconductor device, available technology adopting hafnium base high dielectric constant material layer forms the metal gate electrode lamination, the metal gate process of high dielectric constant material layer can make electric leakage reduce 10 times more than, power consumption also can be well controlled, and under identical power consumption, performance can improve 20% more than in theory.But, because high-k gate dielectric and silicon interface have a large amount of interfacial states, these interfacial states can form unsettled chemical bond with hydrogen in manufacture of semiconductor, these unsettled hydrogen bonds can produce a large amount of interfacial states in the course of work of semiconductor device, thereby changed the performance of semiconductor device, especially there is the comparatively serious unstable effect of back bias voltage temperature in the PMOS pipe that has dielectric layer of high dielectric constant, and there is the comparatively serious unstable effect of positive bias temperature in the NMOS pipe that has equally the high dielectric constant material layer.
Because rear grid technology is comparatively complicated, the problem that therefore will solve Negative Bias Temperature Instability in rear grid high dielectric constant material layer and positive bias temperature instability effect becomes the comprehensive problem of a complexity.
Summary of the invention
The purpose of this invention is to provide a kind ofly in rear grid (Gate-last) technique, reduce the manufacture method of Negative Bias Temperature Instability effect and positive bias temperature instability effect semiconductor device in metal gates.
For addressing the above problem, the invention provides a kind of manufacture method of semiconductor device, comprise the following steps: Semiconductor substrate is provided, forms dielectric layer on described Semiconductor substrate; Form the high dielectric constant material layer on described dielectric layer; Form the cover layer on described high dielectric constant material layer; Form amorphous si-layer on described cover layer; Carry out Implantation to described amorphous si-layer, the ion of injection comprises carbon and fluorine; Carry out annealing process, make carbon and fluorine enter the high dielectric constant material layer; Form polysilicon layer on described amorphous si-layer.
Further, in to described amorphous si-layer, carrying out the step of Implantation, the ion of injection is a kind of of tetrafluoromethane and perfluoroethane or its combination.
Further, the material of described cover layer is a kind of or its combination in titanium nitride and tantalum nitride.
Further, the thickness of described cover layer is 50 dusts～500 dusts.
Further, the material of described high dielectric constant material layer is a kind of or its combination in hafnium zirconium oxide and hafnium oxide.
Further, after the step that forms polysilicon layer, further comprising the steps of: the described polysilicon layer of etching, amorphous si-layer, cover layer, high dielectric constant material layer and dielectric layer, to form the dummy gate electrode structure; Form grid curb wall in described dummy gate electrode structure both sides, form source region and drain region in the Semiconductor substrate of dummy gate electrode structure both sides, and between the Semiconductor substrate upper caldding layer of described dummy gate electrode structure both sides dielectric layer; Remove remaining polysilicon layer in the dummy gate electrode structure, form groove; Fill metal gates in described groove, to form metal gate structure.
Further, the material of described dielectric layer is a kind of or its combination in silica and silicon oxynitride.
Further, adopt thermal oxidation method, chemical vapour deposition technique, physical vaporous deposition or atomic layer deposition method to form described dielectric layer, described high dielectric constant material layer and described cover layer.
Further, the thickness of described amorphous si-layer is 50 dusts～500 dusts.
Further, adopt physical vaporous deposition to form described amorphous si-layer.
in sum, the manufacture method of semiconductor device of the present invention, the rear gate fabrication process that can be used for metal gates high dielectric constant material layer, by cover amorphous si-layer on the high dielectric constant material layer, carry out ion implantation technology to described amorphous si-layer Implantation fluorine compounds, and carry out annealing process, make carbon and the fluorine of injection enter the high dielectric constant material layer, fluorine is at the comparatively stable fluoride chemical bond of formation at the interface of high dielectric constant material layer, for example hafnium-fluorine bond (Hf-F) or silicon-fluorine bond (Si-F), can reduce the existence of dangling bonds in the high dielectric constant material layer, and then reduce the drift of threshold voltage, simultaneously, carbon is present in the high dielectric constant material layer, can be reduced in the diffusion of the doping ions such as other doped regions such as boron or phosphorus in source region and drain region, further reduces the drift of threshold voltage, thereby effectively improves the stability of semiconductor device, in addition, because carbon and fluorine only inject and complete in the primary ions injection technology, implantation dosage is easy to control, and can alleviate repeatedly the damage of Implantation to semiconductor device.
Description of drawings
Fig. 1 is the schematic flow sheet of the manufacture method of semiconductor device in one embodiment of the invention.
Fig. 2～10 are the device profile schematic diagram in the manufacture method of semiconductor device in one embodiment of the invention.
Embodiment
, for making content of the present invention more clear understandable, below in conjunction with Figure of description, content of the present invention is described further.Certainly the present invention is not limited to this specific embodiment, and the known general replacement of those skilled in the art also is encompassed in protection scope of the present invention.
Secondly, the present invention utilizes schematic diagram to carry out detailed statement, and when example of the present invention was described in detail in detail, for convenience of explanation, schematic diagram did not amplify according to general ratio is local, should not use this as limitation of the invention.
Fig. 1 is the schematic flow sheet of the manufacture method of semiconductor device in one embodiment of the invention.As shown in Figure 1, the invention provides a kind of manufacture method of semiconductor device, comprise the following steps:
Step S01: Semiconductor substrate is provided, forms dielectric layer on described Semiconductor substrate;
Step S02: form the high dielectric constant material layer on described dielectric layer;
Step S03: form the cover layer on described high dielectric constant material layer;
Step S04: form amorphous si-layer on described cover layer;
Step S05: carry out Implantation to described amorphous si-layer, the ion of injection comprises carbon and fluorine;
Step S06: carry out annealing process, make carbon and fluorine enter the high dielectric constant material layer;
Step S07: form polysilicon layer on described amorphous si-layer.
In addition, after the step that forms polysilicon layer, further comprising the steps of: the described polysilicon layer of etching, amorphous si-layer, cover layer, high dielectric constant material layer and dielectric layer, to form the dummy gate electrode structure; Form grid curb wall in described grid structure both sides, and form source region and drain region in the Semiconductor substrate of grid structure both sides; Remove remaining polysilicon layer in dummy gate electrode, form groove; Fill metal gates in described groove, to form metal gate structure.
Fig. 2～Figure 10 is the device profile schematic diagram in the manufacture method of semiconductor device in one embodiment of the invention.Describe the manufacture process of semiconductor device in one embodiment of the invention in detail below in conjunction with Fig. 2～Figure 10.
As shown in Figure 2, in step S01, at first Semiconductor substrate 100 is provided, and the material of described Semiconductor substrate 100 can be monocrystalline silicon, polysilicon, amorphous si-layer or silicon Germanium compound etc., can also be for such as composite semiconductor materials such as silicon-on-insulators (SOI); Then form dielectric layer 102 on described Semiconductor substrate 100, the material of described dielectric layer 102 can be silicon nitride or silicon oxynitride, the perhaps combination of silicon nitride and silicon oxynitride, described dielectric layer 102 can adopt thermal oxidation method, chemical vapour deposition technique, physical vaporous deposition or atomic layer deposition method to form.
As shown in Figure 3, in step S02, form high dielectric constant material layer 104 on described dielectric layer 102, the material of described high dielectric constant material layer 104 can be a kind of or its combination in hafnium zirconium oxide and hafnium oxide, other dielectric constants are higher than the material of dioxide dielectric constant also within thought range of the present invention, and described high dielectric constant material layer 104 can adopt thermal oxidation method, chemical vapour deposition technique, physical vaporous deposition or atomic layer deposition method to form.
As shown in Figure 4, in step S03, form cover layer 106 on described high dielectric constant material layer 104, the material of described cover layer 106 is a kind of or its combination in titanium nitride and tantalum nitride, the thickness of described cover layer 106 is 50 dusts～500 dusts, better is 100 dusts, and described cover layer 106 can adopt thermal oxidation method, chemical vapour deposition technique, physical vaporous deposition or atomic layer deposition method to form.Described cover layer 106 can form good contact interface with high dielectric constant material layer 104, and can improve dielectric properties.
As shown in Figure 5, in step S04, form amorphous si-layer 108 on described cover layer 106, the thickness range of described amorphous si-layer 108 is 50 dusts～500 dusts, better is 100 dusts, can adopt physical vaporous deposition to form described amorphous si-layer 108, described amorphous si-layer 108 can be reduced in follow-up ion implantation technology the cover layer 106 of its below and the implant damage of high dielectric constant material layer 104 generation.
As shown in Figure 6, in step S05, to described amorphous si-layer 108, carry out Implantation 300, the ion of injection comprises carbon and fluorine.Wherein, ion can be tetrafluoromethane or perfluoroethane, the perhaps combination of tetrafluoromethane and perfluoroethane, and other fluorocarbons, for example tetrafluoroethene can also be as ion.In the present embodiment, to Implantation and fluorine simultaneously in described amorphous si-layer 108, better Implantation Energy is 2KeV～18KeV, and the implantation dosage scope is 2E14/cm
2～1E15/cm
2, above-mentioned Implantation Energy and dosage can reduce the damage of semiconductor device, are conducive to simultaneously make carbon and fluorine to be advanced into high dielectric constant material layer 104 in follow-up annealing.
Continuation, with reference to figure 6, in step S06, is carried out annealing process, makes carbon and fluorine enter high dielectric constant material layer 104.In carrying out annealing process, carbon and fluorine enter in high dielectric constant material layer 104, fluorine is at the comparatively stable fluoride chemical bond of formation at the interface of high dielectric constant material layer 104, for example hafnium-fluorine bond (Hf-F) or silicon-fluorine bond (Si-F), replace unsettled silicon-hydrogen bond (Si-F), avoid the charge carrier substituted for silicon of thermal excitation-hydrogen bond action to generate the H atom, reduced the existence of dangling bonds, and then reduced the drift of threshold voltage; Simultaneously, carbon is present in high dielectric constant material layer 104 diffusion of doping ions such as can being reduced in other doped regions such as boron or phosphorus in source region and drain region, further reduces the drift of threshold voltage, thereby effectively improves the stability of semiconductor device; In addition, because carbon and fluorine only inject and complete in the primary ions injection technology, implantation dosage is easy to control, and can alleviate repeatedly the damage of Implantation to semiconductor device.
As shown in Figure 7, in step S07, form polysilicon layer 110 on described amorphous si-layer 108, described polysilicon layer 110, as the dummy gate electrode conductive layer, was removed before forming metal gates thereafter.
In step after this, the described polysilicon layer 110 of etching, amorphous si-layer 108, cover layer 106, high dielectric constant material layer 104 and dielectric layer 102, to form dummy gate electrode structure 200 as shown in Figure 8; Then, as shown in Figure 9, form grid curb wall 202 in described dummy gate electrode structure 200 both sides, and by ion implantation technology in the Semiconductor substrate of described dummy gate electrode structure 200 both sides, form source region 204 and drain region 206, and utilize depositing operation and chemical mechanical milling tech blanket dielectric layer 208 on the Semiconductor substrate 100 of described grid curb wall 202 both sides; Then, remove remaining polysilicon layer 110 in dummy gate electrode structure 200, form groove (not indicating in figure); And fill metal gate layers 210 in described groove, to form metal gate structure as shown in figure 10, described metal gate layers 210 can comprise the workfunction layers that is covered in trench bottom surfaces and sidewall and be positioned at the metal gates conductive layer of filling described groove on described workfunction layers, the technological means that is well known to those skilled in the art of the formation technique of metal gates 208 wherein, therefore repeat no more.
in sum, the manufacture method of semiconductor device of the present invention, the rear gate fabrication process that can be used for metal gates high dielectric constant material layer, by cover amorphous si-layer on the high dielectric constant material layer, carry out ion implantation technology to described amorphous si-layer, the Implantation fluorine compounds, and carry out annealing process, make carbon and the fluorine of injection enter the high dielectric constant material layer, fluorine is at the comparatively stable fluoride chemical bond of formation at the interface of high dielectric constant material layer, for example hafnium-fluorine bond (Hf-F) or silicon-fluorine bond (Si-F), can reduce the existence of dangling bonds in the high dielectric constant material layer, and then reduce the drift of threshold voltage, simultaneously, carbon is present in the high dielectric constant material layer, can be reduced in the diffusion of the doping ions such as other doped regions such as boron or phosphorus in source region and drain region, further reduces the drift of threshold voltage, thereby effectively improves the stability of semiconductor device, in addition, because carbon and fluorine only inject and complete in the primary ions injection technology, implantation dosage is easy to control, and can alleviate repeatedly the damage of Implantation to semiconductor device.
Although the present invention discloses as above with preferred embodiment; so it is not in order to limit the present invention; have and usually know the knowledgeable in technical field under any; without departing from the spirit and scope of the present invention; when doing a little change and retouching, so protection scope of the present invention is as the criterion when looking claims person of defining.
Claims (10)
1. the manufacture method of a semiconductor device comprises:
Semiconductor substrate is provided, forms dielectric layer on described Semiconductor substrate;
Form the high dielectric constant material layer on described dielectric layer;
Form the cover layer on described high dielectric constant material layer;
Form amorphous si-layer on described cover layer;
Carry out Implantation to described amorphous si-layer, the ion of injection comprises carbon and fluorine;
Carry out annealing process, make carbon and fluorine enter the high dielectric constant material layer;
Form polysilicon layer on described amorphous si-layer.
2. the manufacture method of semiconductor device as claimed in claim 1, is characterized in that, in to described amorphous si-layer, carrying out the step of Implantation, the ion of injection is a kind of of tetrafluoromethane and perfluoroethane or its combination.
3. the manufacture method of semiconductor device as claimed in claim 1, is characterized in that, the material of described cover layer is a kind of or its combination in titanium nitride and tantalum nitride.
4. the manufacture method of semiconductor device as claimed in claim 1, is characterized in that, the thickness of described cover layer is 50 dusts～500 dusts.
5. the manufacture method of semiconductor device as claimed in claim 1, is characterized in that, the material of described high dielectric constant material layer is a kind of or its combination in hafnium zirconium oxide and hafnium oxide.
6. the manufacture method of semiconductor device as claimed in claim 1, is characterized in that, after the step that forms polysilicon layer, also comprises:
The described polysilicon layer of etching, amorphous si-layer, cover layer, high dielectric constant material layer and dielectric layer, to form the dummy gate electrode structure;
Form grid curb wall in described dummy gate electrode structure both sides, form source region and drain region in the Semiconductor substrate of dummy gate electrode structure both sides, and between the Semiconductor substrate upper caldding layer of described dummy gate electrode structure both sides dielectric layer;
Remove remaining polysilicon layer in the dummy gate electrode structure, form groove;
Fill metal gates in described groove, to form metal gate structure.
7., as the manufacture method of the described semiconductor device of any one in claim 1 to 6, it is characterized in that, the material of described dielectric layer is a kind of or its combination in silica and silicon oxynitride.
8. as the manufacture method of the described semiconductor device of any one in claim 1 to 6, it is characterized in that, adopt thermal oxidation method, chemical vapour deposition technique, physical vaporous deposition or atomic layer deposition method to form described dielectric layer, described high dielectric constant material layer and described cover layer.
9., as the manufacture method of the described semiconductor device of any one in claim 1 to 6, it is characterized in that, the thickness of described amorphous si-layer is 50 dusts～500 dusts.
10., as the manufacture method of the described semiconductor device of any one in claim 1 to 6, it is characterized in that, adopt physical vaporous deposition to form described amorphous si-layer.
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| CN103943481A (en) * | 2014-04-22 | 2014-07-23 | 上海华力微电子有限公司 | Method for avoiding negative bias temperature instability of device |
| CN104952783A (en) * | 2014-03-31 | 2015-09-30 | 中芯国际集成电路制造(上海)有限公司 | Shallow trench isolation structure, production method thereof and semiconductor device with shallow trench isolation structure |
| CN108074804A (en) * | 2016-11-18 | 2018-05-25 | 台湾积体电路制造股份有限公司 | The manufacturing method of the gate structure of semiconductor device |
| CN108649043A (en) * | 2018-04-25 | 2018-10-12 | 武汉新芯集成电路制造有限公司 | A method of improving the dangling bonds bonding of silicon atom |
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