CN103390594A - Multichip flip-chip encapsulation module and related manufacturing method - Google Patents
Multichip flip-chip encapsulation module and related manufacturing method Download PDFInfo
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- CN103390594A CN103390594A CN201210141377XA CN201210141377A CN103390594A CN 103390594 A CN103390594 A CN 103390594A CN 201210141377X A CN201210141377X A CN 201210141377XA CN 201210141377 A CN201210141377 A CN 201210141377A CN 103390594 A CN103390594 A CN 103390594A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
Abstract
The invention provides a multichip flip-chip encapsulation module which comprises a plurality of chips. Each chip comprises a plurality of connection points and can be used for being connected to the connection points of another chip by means of a conducting element in a coupled mode or being connected to pins by means of the conducting element in a coupled mode. In addition, the multichip flip-chip encapsulation module comprises dielectric elements which are arranged between the chips and between the chips and the conducting elements to achieve insulation effects. The multichip flip-chip encapsulation module further comprises encapsulated elements for covering the chips and the conducting elements connected between the chips to achieve protection effects. In the multichip flip-chip encapsulation module, the chips can be connected with one another by means of the conducting elements in the encapsulation module and can also be combined with the pins, so the number of the pins needed by the encapsulation module can be reduced, current carrying capacity is enhanced, and heat dissipation performance is better.
Description
Technical field
The relevant a kind of chip package module of the present invention, espespecially a kind of chip package module that is packaged with a plurality of chips.
Background technology
Due to the progress of semiconductor technology, increasing electronic component can be contained in single chip (die or chip), to carry out various required functions.For example, system single chip (system on a chip) is exactly that a needed most of element of system is all integrated the execution mode that is manufactured on one chip.Yet, because system single chip need to comprise various types of elements, for example, analog circuit, digital circuit and memory etc.The fabrication schedule of these elements is widely different, not only can cause the manufacture process of system single chip more complicated, also can reduce the yield of system single chip, thus make the design complexities of system single chip and cost all relatively high.
Therefore, the mode of employing system in package (system in package) is arranged, various elements are fabricated to respectively a plurality of chips, more a plurality of chip packages are become single encapsulation module (package).General system in package is that a plurality of chips are arranged on substrate (substrate), and carries out the signal connection of chip chamber by substrate surface or inner wire.Use the mode that substrate encapsulates usually can take larger package area, encapsulation process is also comparatively numerous and diverse, thus industry the mode of employing chip package (flip chip) is arranged is single encapsulation module with a plurality of chip packages.Yet, when the mode of use chip package encapsulates plural chip, if two chip chambers need to carry out signal and connect, even if can be linked between two chips in modes such as metal clips (clip), also be difficult to metal clip is navigated to each contact (pad) of chip exactly to connect, and can increase the complexity of whole canned program, and the range of application that causes covering brilliant mode package multi sheet is restricted.
In addition, substrate uses several microns (10-6m, um) or thinner plastics to make usually, and wire is subject to the size of substrate and makes the ability of bearing electric current not good, to such an extent as to and temperature is easily too high during the running of the poor chip of the thermal conductivity of substrate, and need to take extra cooling mechanism.Therefore, have a kind of with the chip mode that lead frame (lead frame) encapsulates of arranging in pairs or groups, make because lead frame can use tens of micron to the metal frameworks of hundreds of micron thickness, so its effect of bearing the ability of electric current and heat radiation all is better than using the mode of substrate package.Yet, when the mode of use lead frame encapsulates plural chip, be difficult to equally carry out the signal connection at two chip chambers, and be difficult to be applicable to this type of application.
Yet, a plurality of chip chambers often need many wires to connect, for example, just need many wires to be connected between memory and Memory Controller, connect if the signal of each chip all will be directed to the encapsulation module outside, will cause the number of pins of encapsulation module to increase, not only reduce the advantage of multi-chip package, also can cause the increase of package dimension, and the complexity of total system and hardware cost are all increased.
Summary of the invention
In view of this, how to alleviate or solve in the above association area more than the disappearance of chip package module, real have problem to be solved for industry.
This specification provides a kind of embodiment of manufacture method of multi-chip chip package module, and it comprises: a second surface of a second surface of one first chip and one second chip is engaged to one second support plate; One first dielectric element is arranged at this first chip and this second chip chamber; The one first conducting element group that will include a plurality of conducting elements is arranged at the part contact top of a plurality of contacts of a first surface of this first chip, and the part contact top of a plurality of contacts that is arranged at a first surface of this second chip; Use includes the one second conducting element group of using a plurality of conducting elements, the part contact of these a plurality of contacts of the first surface of this first chip is connected to the part contact of these a plurality of contacts of the first surface of this second chip; A plurality of strip parts with a plurality of engagement to lead frames of this first conducting element group; And use a potted element to coat this first chip, this second chip and this second conducting element group to form a multi-chip chip package module.
This specification separately provides a kind of embodiment of manufacture method of multi-chip chip package module, and it comprises: a second surface of a second surface of one first chip and one second chip is engaged to one second support plate; One first dielectric element is arranged at this first chip and this second chip chamber; The one first conducting element group that will include a plurality of conducting elements is arranged at the part contact top of a plurality of contacts of a first surface of this first chip, and the part contact top of a plurality of contacts that is arranged at a first surface of this second chip; Use includes the one second conducting element group of using a plurality of conducting elements, the part contact of these a plurality of contacts of the first surface of this first chip is connected to the part contact of these a plurality of contacts of the first surface of this second chip; And a plurality of conducting elements that a plurality of pins are connected to respectively this first conducting element group are to form a multi-chip chip package module.
This specification separately provides a kind of embodiment of multi-chip chip package module, and it comprises: one first chip, include a first surface and a second surface, and wherein the first surface of this first chip includes a plurality of contacts; One second chip, include a first surface and a second surface, and wherein the first surface of this second chip includes a plurality of contacts; One first dielectric element, be arranged at this first chip and this second chip chamber; One first conducting element group, include a plurality of conducting elements, is used for the part contact in these a plurality of contacts of the part contact of these a plurality of contacts of this first chip and this second chip is connected to this lead frame; One second conducting element group, include a plurality of conducting elements, for the part contact in these a plurality of contacts that the part contact of these a plurality of contacts of this first chip are connected to this second chip; And a plurality of pins, be respectively coupled to a plurality of conducting elements of this first conducting element group.
One of advantage of above-described embodiment is to improve the radiating effect of multi-chip chip package module and the ability of bearing electric current.Another advantage of above-described embodiment can make each chip connect in multi-chip chip package module, and to reduce the required number of pins of encapsulation module, and the size that can encapsulate is more simplified.Other advantage of the present invention will explain orally in more detail by the following description and accompanying drawing.
Description of drawings
Fig. 1 is the flow chart after the manufacture method of the multi-chip chip package module of one embodiment of the invention is simplified.
Fig. 2,4,6,8,10,12,15 and 17 is the top view of embodiment after different encapsulated phases are simplified of multi-chip chip package module of the present invention.
Fig. 3,5,7,9,11,13,16 and 18 is the profile of embodiment after different encapsulated phases are simplified of multi-chip chip package module of the present invention.
Figure 14 is the flow chart after the manufacture method of the multi-chip chip package module of another embodiment of the present invention is simplified.
Embodiment
Below will coordinate correlative type that the present invention's embodiment is described.In these were graphic, identical label represented same or similar element or flow process/step.
Fig. 1 is the flow chart after the manufacture method of the multi-chip chip package module of one embodiment of the invention is simplified.While according to the method for Fig. 1, making, multi-chip chip package module is shown in Fig. 2～13 in the view of each encapsulated phase.Below will, with Fig. 1 Fig. 2～13 of arranging in pairs or groups, further illustrate multi-chip chip package module of the present invention and manufacture method.
Please refer to Fig. 2 and Fig. 3, Fig. 2 is the top view of multi-chip chip package module 200, and Fig. 3 is multi-chip chip package module 200 profiles along the A-A ' tangent line in Fig. 2.In the flow process 110 of Fig. 1, the first surface 221 that the first chip (die) 220 is had contact (pad) 224 and 227, and the first surface 241 that the second chip 240 has contact 244 and 247 engages with the first support plate (carrier or substrate) 210.For example, can use the material (not illustrating in figure) with tackness to engage.The material manufacturing that support plate 210 can adopt metal or plastics etc. to have enough hardness, with carries chips 220 and 240.Surface 211 in order to the support plate 210 that contacts with 240 with chip 220 is in fact smooth, makes contact 224,227,244 and 247 etc. can be positioned at identical in fact horizontal level, and can connect with conducting element more easily in down-stream.In addition, also can be filled in around chip 220 and 240 with the first dielectric element (dielectric) 230 in flow process 110, to form multi-chip chip package module 200.In the present embodiment, the surface 222 of the surface of dielectric element 230 and chip 220 and 240 and 242 can form the surface of a substantial planar, can engage with the second support plate 410 more easily in down-stream.
Please refer to Fig. 4 and Fig. 5, Fig. 4 is the top view of multi-chip chip package module 400, and Fig. 5 is multi-chip chip package module 400 profiles along the B-B ' tangent line in Fig. 4.In the flow process 120 of Fig. 1, the second surface 242 of the second surface 222 of the dielectric element 230 of multi-chip chip package module 200, chip 220 and chip 240 is engaged to the second support plate 410, to form multi-chip chip package module 400, wherein support plate 410 can adopt metal or plastics etc. to have the material enforcement of enough hardness., with after chip 220 and 240 engages, then with the means of the physics such as etching, grinding, excision or chemistry, remove support plate 210 Deng support plate 410.In Fig. 4 and follow-up view, show respectively the position of chip 220 and 240 with empty frame table.
Please refer to Fig. 6 and Fig. 7, Fig. 6 is the top view of multi-chip chip package module 600, and Fig. 7 is multi-chip chip package module 600 profiles along the C-C ' tangent line in Fig. 6, Fig. 6 and Fig. 7 overturn the multi-chip chip package module 400 of Fig. 4 and make the surface 221 and 241 of chip 220 and 240 be positioned at top, so that explanation.In the flow process 130 of Fig. 1, the second dielectric element 610 is arranged at surface 221 and 241 tops of chip 220 and 240, and make the second dielectric element 610 not cover or not exclusively be covered in the top of contact 223～227 with the contact 243～247 of chip 240 of chip 220, and form multi-chip chip package module 600.
Please refer to Fig. 8 and Fig. 9, Fig. 8 is the top view of multi-chip chip package module 800, and Fig. 9 is multi-chip chip package module 800 profiles along the D-D ' tangent line in Fig. 8.In flow process 140, the first conducting element 811～814 (also can be described as the first conducting element group) is arranged at respectively contact 223,224,243 and 244 top, and connect respectively contact 225 and are connected, connect contact 226 and are connected and connect contact 227 and 247 with the second conducting element 821～823 (also can be described as the second conducting element group), and form multi-chip chip package module 800.
On implementation, conducting element 821～823 can use respectively the wire of various suitable shapes and suitable dimension to realize, to connect respectively contact 225 and to be connected, to connect contact 226 and to be connected and to connect contact 227 and 247, and make these conducting elements 821～823 be positioned in fact same plane.Adopting in the legacy system level packaged type of substrate form encapsulation at other, is to use wire to connect up on the Different Plane of substrate,, to connect each chip, from the method for packing of this case, has significantly different.
Please refer to Figure 10 and Figure 11, Figure 10 is the top view of multi-chip chip package module 1000, and Figure 11 is multi-chip chip package module 1000 profiles along the E-E ' tangent line in Figure 10.in flow process 150, the 3rd dielectric element 1010 is arranged at the top of dielectric element 610, and the top that is arranged at conducting element 821～823, make between the contact that connects chip 220 and 240 conducting element (for example, the conducting element 821 that connects contact 225 and 245, the conducting element 822 that connects contact 226 and 246, and the conducting element 823 that connects contact 227 and 247) all can be covered by dielectric element 1010, and make contact 224, 227, not by dielectric element 1010, not coated at least partly of the conducting element 811～814 of 243 and 247 tops, to form multi-chip chip package module 1000.
Please refer to Figure 12 and Figure 13, Figure 12 is the top view of multi-chip chip package module 1200, and Figure 13 is multi-chip chip package module 1200 profiles along the F-F ' tangent line in Figure 12.In flow process 160, the modes such as use plating are made pin 1211～1214 (only showing 1212 and 1214 in Figure 13), and are connected to respectively conducting element 811～814.For example, pin 1211～1214 can adopt the electric conducting materials such as copper, gold, tin or alloy to implement, and can form the plating pin.Therefore, multi-chip chip package module 1200 just can utilize pin 1211～1214 and be connected in circuit board or other electronic component.
Figure 14 is the flow chart after the manufacture method of the multi-chip chip package module of another embodiment of the present invention is simplified, and the manufacture method of Figure 14 and Fig. 1 is substantially the same in flow process 110～140, for simplicity's sake, below only with regard to different flow processs, partly describes.While according to the method for Figure 14, making, multi-chip chip package module is shown in Fig. 2～9 and Figure 15～18 in the view of each encapsulated phase, below will further illustrate with Figure 15～18 manufacture method of Figure 14.
Please refer to Figure 15 and Figure 16, Figure 15 is the top view of multi-chip chip package module 1500, and Figure 16 is multi-chip chip package module 1500 profiles along the G-G ' tangent line in Figure 15.Multi-chip chip package module 1500 is that 900 upsets of multi-chip chip package module are positioned over lead frame 1510, and wherein lead frame 1510 includes strip part 1511～1514 and outer frame part 1515.In flow process 1450, with being connected in contact 223,224,243 and 244 conducting element 811～814 and being engaged to respectively the strip part 1511～1514 of lead frame 1510, to form multi-chip chip package module 1500.For example, can use the electric conducting materials such as tin or conducting resinl to engage.On implementation,, if be connected in contact 223,224,243 and 244 conducting element 811～814 for lower metals of fusing point such as tin, also conducting element 811～814 hot melts can be engaged with lead frame 1510, with formation multi-chip chip package module 1500.
Please refer to Figure 17 and Figure 18, Figure 17 is the top view of multi-chip chip package module 1700, and Figure 18 is multi-chip chip package module 1700 profiles along the H-H ' tangent line in Figure 17.In flow process 1460, use potted element 1710 to coat multi-chip chip package module 1500, and the outer frame part of lead frame 1,510 1515 is removed, and form multi-chip chip package module 1700.1511～1514 of the remaining strip parts of lead frame 1510 can, as pin, make multi-chip chip package module 1700 can utilize the strip part 1511～1514 of lead frame 1510 to be connected in circuit board or other electronic component.
In other the flow process 110 of embodiment, also can first dielectric element 230 be covered to the surface 222 and 242 of chip 220 and 240, again unnecessary dielectric element 230 is removed, make the surface 242 of the surface 222 of dielectric element 230, chip 220 and chip 240 form the surface of a substantial planar.Perhaps, in flow process 110, dielectric element 230 also can be covered to the surface 222 and 242 of chip 220 and 240, and is formed the surface of a substantial planar by dielectric element 230, and in flow process 120, by dielectric element 230, with support plate 410, is engaged.
In other the flow process 130 of embodiment, also dielectric element 610 can be arranged at chip 220 and 240 surface 221 and 241 whole, then the means of the dielectric element 610 of contact 223～227 and 243～247 tops with the physics such as etching, grinding, excision or chemistry are removed.
In other the flow process 130 of embodiment, also dielectric element 610 can be covered in chip 220 contact 223～227 part and/or be covered in part with the contact 243～247 of chip 240, but still allow contact 223～227 with are connected～247 still have enough surfaces respectively with conducting element 811～814 with are connected～823 are connected.
In other the flow process 140 of embodiment, the conducting element 811～814 of contact 223,224,243 and 244 top, and the conducting element 823 that connects contact 225 and the conducting element 821 of being connected, connection contact 226 and the conducting element 822 of being connected and connection contact 227 and 247, all can use respectively identical or different electric conducting material to implement.
In other embodiment, if the thickness of chip 220 and 240 is identical in fact, can simple flow 110～130, and do not have the surface 222 and 242 of contact to be engaged in support plate 410 chip 220 and 240, with dielectric element 230 be arranged at chip 220 and 240 around, and dielectric element 610 be arranged at chip 220 and 240 have the surface 221 of contact and 241 suitable place.
In flow process 1460 in other embodiments, also can make potted element 1710 not exclusively coat support plate 410, while making 1700 running of multi-chip chip package module, chip 220 and 240 can dispel the heat by support plate 410.
In flow process 1460 in other embodiments, also can first the means of support plate 410 with physics or chemistry be removed, re-use the potted element 1710 remaining multi-chips of coating and cover brilliant module.
In flow process 1460 in other embodiments, the ring-type outer frame part of lead frame 1510 also can be set to other suitable shape, and also can temporarily first not remove or not exclusively remove, so that transport in process, is difficult for damaging.
In the above embodiments, dielectric element 230,610 and 1010 and potted element 1710 all can adopt identical or different insulating material, for example, resin, rubber, polymer etc.
In the above embodiments, support plate 410 can use insulating material or employing to prevent the device that leaks electricity, and to prevent chip 220 and 240, by support plate 410, leaks electricity.
In the above-described embodiment, conducting element 811～814 and 821～823 can adopt the metal materials such as tin, nickel, copper or silver to implement in modes such as printing, sputter, plating or evaporations, and perhaps the electric conducting material of the metal such as graphite, macromolecular material, conducting resinl or nonmetallic materials is implemented.
In the above-described embodiment, lead frame 1510 can adopt the mode such as etching and metal-made is made required shape, and lead frame 1510 can use the metals of tens of microns to hundreds of micron thickness, to increase current carrying capacity.
In addition, because chip chamber does not need to transmit very large electric current usually, therefore, in certain embodiments, the thickness of conducting element 821～823 can be set to much smaller than the thickness of lead frame 1510.
In the above-described embodiment, potted element 1710 can adopt the opaque materials such as resin.
Therefore, in the above-described embodiment, by with the mode of a plurality of chips with chip package, first at chip chamber, with wire, connect, then with these chips incorporate to lead frame, and can realize using lead frame to complete the single encapsulation module of multi-chip, and reduce the size of encapsulation module.And the signal that can realize a plurality of chip chambers in single encapsulation module connects, the contact of each chip can be connected accurately by conducting element, and the quantity of inter-chip signals line is significantly increased, so the hardware design complexity of encapsulation module outside and hardware cost all can reduce.
In addition, the embodiment that above-mentioned collocation lead frame encapsulates, also possesses the advantage of using leadframe package is arranged, that is thermal diffusivity is good and current load power advantages of higher, and usefulness and the useful life that can improve product.
(element) word of mentioned " element " in the middle of specification in the whole text and follow-up claim, comprised the concept in member (component), layer structure (layer) or zone (region).
Illustrating when graphic, the size of some element and relative size can be carried out amplification, so that graphic content can clearly be expressed.In addition, the shape of some element can be simplified to facilitate to illustrate.Therefore, the shape of graphic middle each element that illustrates, size, quantity and relative size,, unless the applicant specializes, otherwise should not be used to limit scope of the present invention.In addition, the present invention can embody with many different forms, is explaining when of the present invention, does not answer the aspect of the exemplary embodiment that limit proposes at this specification.
Used some vocabulary to censure specific element in the middle of specification and follow-up claim.The person of ordinary skill in the field should understand, and same element may be called with different nouns.This specification and follow-up claim are not used as distinguishing the mode of element with the difference of title, but the benchmark that the difference on function is used as distinguishing with element.In the middle of specification and follow-up claim, be open term mentioned " comprising " in the whole text, thus should be construed to " comprise but be not limited to ... "In addition, " couple " word this comprise any directly and indirectly connect means.Therefore, be coupled to the second element if describe the first element in literary composition, represent that the first element can directly (comprise by signal connected modes such as electric connection or wireless transmission, optical delivery) and be connected in this second element, or by other element or connection means indirectly electrically or signal be connected to the second element.
Used herein " and/or " describing mode, comprise cited one of them or the combination in any of a plurality of projects.In addition, unless specialize in this specification, the term of any odd number lattice all comprises the connotation of plural lattice simultaneously.
In the middle of specification in the whole text and follow-up claim, if describe the first element be positioned on the second element, above the second element, connect, engage, be coupled to the second element or with the second element, join, can represent the first element directly position on the second element, directly connect, directly engage, directly be coupled to the second element, also can represent that the first element and the second interelement have other medium element existence.Relatively, if describe the first element directly position on the second element, directly connect, directly engage, directly couple or directly be connected to mutually the second element, represent that the first element and the second interelement do not have other medium element.
For convenience of description, may use some narrations relevant with the relative position in space in specification, for example " in ... on ", " ... top ", " in ... under ", " ... below ", " higher than ... ", " lower than ... ", " making progress ", " downwards " etc., function or this element and other interelement relative space relation of a certain element in graphic are described.The person of ordinary skill in the field should understand, the narration that these are relevant with the relative position in space, not only comprise the points relationship (orientation) of described element in graphic, also comprised the various different points relationships of described element when using, operate, making or assembling.For example,, if with graphic, turn upside down, originally used " in ... on " element described, will become " in ... under ".Therefore, use in specification " in ... on " describing mode, comprised in explanation " in ... under " and " in ... on " two kinds of different points relationships.In like manner, " making progress " used herein word, comprised " making progress " and " downwards " two kinds of different points relationships in explanation.
The foregoing is only the present invention's preferred embodiment, all equalizations of doing according to the claims in the present invention change and modify, and all should belong to the present invention's covering scope.
Claims (17)
1. the manufacture method of a multi-chip chip package module, it comprises:
One second surface of one second surface of one first chip and one second chip is engaged to one second support plate;
One first dielectric element is arranged at this first chip and this second chip chamber;
The one first conducting element group that will include a plurality of conducting elements is arranged at the part contact top of a plurality of contacts of a first surface of this first chip, and the part contact top of a plurality of contacts that is arranged at a first surface of this second chip;
Use includes the one second conducting element group of using a plurality of conducting elements, the part contact of these a plurality of contacts of the first surface of this first chip is connected to the part contact of these a plurality of contacts of the first surface of this second chip;
A plurality of strip parts with a plurality of engagement to lead frames of this first conducting element group; And
Use a potted element to coat this first chip, this second chip and this second conducting element group to form a multi-chip chip package module.
2. manufacture method as claimed in claim 1 separately includes:
After the first surface of the first surface of this first chip and this second chip is engaged to one first support plate, just the second surface of the second surface of this first chip and this second chip is engaged to this second support plate; And
To this second support plate, remove this first support plate when this first chip and this second chip join.
3. manufacture method as claimed in claim 1 separately includes:
After this second support plate is removed, just use this potted element to coat this first chip, this second chip and this second conducting element group.
4. manufacture method as claimed in claim 1 separately includes:
Remove an outer frame part of this lead frame, with the pin of a plurality of strip parts with this lead frame as this multi-chip chip package module.
5., as the manufacture method of claim 1 to 4 any one, separately include:
Be arranged at one second dielectric element between this second conducting element group and this first chip and/or be arranged between this second conducting element group and this second chip.
6. the manufacture method of a multi-chip chip package module, it comprises:
One second surface of one second surface of one first chip and one second chip is engaged to one second support plate;
One first dielectric element is arranged at this first chip and this second chip chamber;
The one first conducting element group that will include a plurality of conducting elements is arranged at the part contact top of a plurality of contacts of a first surface of this first chip, and the part contact top of a plurality of contacts that is arranged at a first surface of this second chip;
Use includes the one second conducting element group of using a plurality of conducting elements, the part contact of these a plurality of contacts of the first surface of this first chip is connected to the part contact of these a plurality of contacts of the first surface of this second chip; And
A plurality of pins are connected to respectively a plurality of conducting elements of this first conducting element group to form a multi-chip chip package module.
7. manufacture method as claimed in claim 6 separately includes:
After the first surface of the first surface of this first chip and this second chip is engaged to one first support plate, just the second surface of the second surface of this first chip and this second chip is engaged to this second support plate; And
To this second support plate, remove this first support plate when this first chip and this second chip join.
8. manufacture method as claimed in claim 6 separately includes:
Remove this second support plate.
9. manufacture method as claimed in claim 6, wherein these a plurality of pins adopt the mode of electroplating to make.
10., as the manufacture method of claim 6 to 9 any one, separately include:
Be arranged at one second dielectric element between this second conducting element group and this first chip and/or be arranged between this second conducting element group and this second chip.
11. the manufacture method as claim 6 to 9 any one separately includes:
Use one the 3rd dielectric element to coat this second conducting element group.
12. a multi-chip chip package module, it comprises:
One first chip, include a first surface and a second surface, and wherein the first surface of this first chip includes a plurality of contacts;
One second chip, include a first surface and a second surface, and wherein the first surface of this second chip includes a plurality of contacts;
One first dielectric element, be arranged at this first chip and this second chip chamber;
One first conducting element group, include a plurality of conducting elements, is used for the part contact in these a plurality of contacts of the part contact of these a plurality of contacts of this first chip and this second chip is connected to this lead frame;
One second conducting element group, include a plurality of conducting elements, for the part contact in these a plurality of contacts that the part contact of these a plurality of contacts of this first chip are connected to this second chip; And
A plurality of pins, be respectively coupled to a plurality of conducting elements of this first conducting element group.
13. the multi-chip chip package module as claim 12 separately comprises:
One potted element, coat this first chip, this second chip and this second conducting element group;
Wherein these a plurality of pins are respectively a plurality of strip parts of a lead frame.
14. the multi-chip chip package module as claim 12 separately comprises:
One the 3rd dielectric element, coat this second conducting element group;
Wherein these a plurality of pins are for electroplating pin.
15. as claim 12,13 or 14 multi-chip chip package module, wherein this second conducting element group is positioned in fact same plane.
16., as claim 12,13 or 14 multi-chip chip package module, separately comprise:
One second dielectric element, be arranged between this second conducting element group and this first chip and/or be arranged between this second conducting element group and this second chip.
17., as claim 12,13 or 14 multi-chip chip package module, separately include:
One second support plate, be engaged in this second surface of this first chip and this second surface of this second chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210141377XA CN103390594A (en) | 2012-05-09 | 2012-05-09 | Multichip flip-chip encapsulation module and related manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210141377XA CN103390594A (en) | 2012-05-09 | 2012-05-09 | Multichip flip-chip encapsulation module and related manufacturing method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN103390594A true CN103390594A (en) | 2013-11-13 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201210141377XA Pending CN103390594A (en) | 2012-05-09 | 2012-05-09 | Multichip flip-chip encapsulation module and related manufacturing method |
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| Country | Link |
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| CN (1) | CN103390594A (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5817540A (en) * | 1996-09-20 | 1998-10-06 | Micron Technology, Inc. | Method of fabricating flip-chip on leads devices and resulting assemblies |
| US6159767A (en) * | 1996-05-20 | 2000-12-12 | Epic Technologies, Inc. | Single chip modules, repairable multichip modules, and methods of fabrication thereof |
| US20100035384A1 (en) * | 2007-06-25 | 2010-02-11 | Epic Technologies, Inc. | Methods of fabricating a circuit structure with a strengthening structure over the back surface of a chip layer |
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2012
- 2012-05-09 CN CN201210141377XA patent/CN103390594A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6159767A (en) * | 1996-05-20 | 2000-12-12 | Epic Technologies, Inc. | Single chip modules, repairable multichip modules, and methods of fabrication thereof |
| US5817540A (en) * | 1996-09-20 | 1998-10-06 | Micron Technology, Inc. | Method of fabricating flip-chip on leads devices and resulting assemblies |
| US20100035384A1 (en) * | 2007-06-25 | 2010-02-11 | Epic Technologies, Inc. | Methods of fabricating a circuit structure with a strengthening structure over the back surface of a chip layer |
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Application publication date: 20131113 |