CN103390652B - Groove charge compensation schottky semiconductor device and manufacture method thereof - Google Patents
Groove charge compensation schottky semiconductor device and manufacture method thereof Download PDFInfo
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- CN103390652B CN103390652B CN201210152685.2A CN201210152685A CN103390652B CN 103390652 B CN103390652 B CN 103390652B CN 201210152685 A CN201210152685 A CN 201210152685A CN 103390652 B CN103390652 B CN 103390652B
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Abstract
The invention discloses a groove charge compensation schottky semiconductor device. The groove charge compensation schottky semiconductor device has a charge compensation structure. When the semiconductor device receives certain reverse bias voltage, a first conductive semiconductor material and a second conductive semiconductor material can form charge compensation, and the reverse blocking characteristic of the device is improved. Electrode metal is led into the upper portion of a groove, so that the peak value electric field intensity of the schottky junction surface during the semiconductor device receives the reverse bias voltage can be reduced, and the reverse blocking characteristic of the device is further improved. The invention further provides a manufacture method of the groove charge compensation schottky semiconductor device.
Description
Technical field
The present invention relates to a kind of groove charge compensation Schottky semiconductor device, the invention further relates to a kind of groove electric charge
The preparation method of compensation Schottky semiconductor device.The semiconductor device of the present invention is the basic knot for manufacturing power rectifier device
Structure.
Background technology
Power semiconductor is widely used on power management and power supply application, is related specifically to the half of schottky junction
Conductor device has become the important trend of device development, and schottky device is fast etc. with the low unlatching turn-off speed of positive cut-in voltage
Advantage, while schottky device also has reverse leakage current big, it is impossible to the shortcomings of being applied to environment under high pressure.
Schottky diode can be the most frequently used for plane figure by various different topologies manufactures, traditional
Planer schottky diode has the Electric Field Distribution curve of mutation in drift region, have impact on the reverse breakdown characteristics of device, while
Traditional planer schottky diode has higher conducting resistance.
The content of the invention
The present invention is proposed for the problems referred to above, there is provided a kind of groove charge compensation Schottky semiconductor device and its preparation side
Method.
A kind of groove charge compensation Schottky semiconductor device, it is characterised in that：Including：Substrate layer, is semi-conducting material
Constitute；Drift layer, is that the first conducting semiconductor material is constituted, on substrate layer；Multiple groove structures, groove is located at drift
In layer, trench wall region is abutted against in drift layer and is provided with the second conducting semiconductor material, it is under-filled in groove to have insulation material
Material, groove internal upper part filling electrode metal；Schottky barrier junction, positioned at the first conducting semiconductor material upper surface.
A kind of preparation method of groove charge compensation Schottky semiconductor device, it is characterised in that：Comprise the steps：
Substrate layer surface forms the first conducting semiconductor material layer, and then surface forms insulation material layer；Carry out lithography corrosion process to go
Except surface portion dielectric, then etch and remove partial denudation semi-conducting material formation groove；Carry out second in groove to lead
Electric impurity diffusion；The deposition insulating material in groove, anti-etching insulating material, and remove surface insulation material；Deposit potential barrier gold
Category, is sintered to form schottky barrier junction.
When semiconductor device connects certain reverse biased, the first conducting semiconductor material and the second conducting semiconductor material
Charge compensation can be formed, the breakdown reverse voltage of device is improved.Therefore the impurity doping concentration of drift region can also be improved, from
And the forward conduction resistance of device can be reduced, improve the forward conduction characteristic of device.
Electrode metal is introduced by groove top, schottky junction surface when semiconductor device connects reverse biased can be reduced
Peak electric field strength, so as to further improve the reverse blocking voltage of device.
Description of the drawings
Fig. 1 is a kind of groove charge compensation Schottky semiconductor device generalized section of the present invention；
Fig. 2 is a kind of groove charge compensation Schottky semiconductor device generalized section of the present invention.
Wherein,
1st, substrate layer；
2nd, silicon dioxide；
3rd, the first conducting semiconductor material；
4th, the second conducting semiconductor material；
5th, schottky barrier junction；
6th, silicon nitride；
10th, upper surface metal level；
11st, lower surface metal layer.
Specific embodiment
Embodiment 1
Fig. 1 is a kind of groove charge compensation Schottky semiconductor device profile of the present invention, with reference to Fig. 1 specifically
The semiconductor device of the bright present invention.
A kind of Schottky semiconductor device, including：Substrate layer 1, be N conductive type semiconductor silicon materials, and phosphorus atoms are mixed
Miscellaneous concentration is 1E19/CM3, in the lower surface of substrate layer 1, by the extraction electrode of lower surface metal layer 11；First conductive semiconductor material
Material 3, is the semiconductor silicon material of N conduction types on substrate layer 1, and the doping content of phosphorus atoms is 1E16/CM3；Second
Conducting semiconductor material 4, is the semiconductor silicon material of P conduction types near trench wall, and the doping content of boron atom is
3E16/CM3；Schottky barrier junction 5, is semiconductor silicon material and barrier metal positioned at the surface of the first conducting semiconductor material 3
The silicide of formation；Silicon dioxide 2, the bottom in groove；Device upper surface and groove internal upper part have upper surface metal level
10, it is that device draws another electrode.
Its processing technology comprises the steps：
The first step, on the surface of substrate layer 1 the first conducting semiconductor material layer is epitaxially formed, and deposit forms silicon nitride layer；
Second step, carries out lithography corrosion process, and semiconductor material surface removes partial silicon nitride, and then etching removes part
Bare semiconductor silicon materials form groove；
3rd step, carries out boron impurity diffusion in groove；
4th step, the deposit in groove forms silicon dioxide 2, anti-etching silicon dioxide 2, erosion removal silicon nitride layer；
5th step, in semiconductor material surface barrier metal is deposited, and is sintered to form schottky barrier junction 5, Ran Hou
Surface deposition metal forms upper surface metal level 10；
6th step, carries out back side metallization technology, overleaf forms lower surface metal layer 11, as shown in Figure 1.
Embodiment 2
Fig. 2 is a kind of groove charge compensation Schottky semiconductor device profile of the present invention, with reference to Fig. 2 specifically
The semiconductor device of the bright present invention.
A kind of Schottky semiconductor device, including：Substrate layer 1, be N conductive type semiconductor silicon materials, and phosphorus atoms are mixed
Miscellaneous concentration is 1E19/CM3, in the lower surface of substrate layer 1, by the extraction electrode of lower surface metal layer 11；First conductive semiconductor material
Material 3, is the semiconductor silicon material of N conduction types on substrate layer 1, and the doping content of phosphorus atoms is 1E16/CM3；Second
Conducting semiconductor material 4, is the semiconductor silicon material of P conduction types near trench wall, and the doping content of boron atom is
3E16/CM3；Schottky barrier junction 5, is semiconductor silicon material and barrier metal positioned at the surface of the first conducting semiconductor material 3
The silicide of formation；Silicon dioxide 2, positioned at trench wall；Silicon nitride 6, the bottom in groove；In device upper surface and groove
Top has upper surface metal level 10, is that device draws another electrode.
Its processing technology comprises the steps：
The first step, on the surface of substrate layer 1 the first conducting semiconductor material layer is epitaxially formed, and deposit forms silicon nitride layer；
Second step, carries out lithography corrosion process, and semiconductor material surface removes partial silicon nitride, and then etching removes part
Bare semiconductor silicon materials form groove；
3rd step, carries out boron impurity diffusion in groove, while forming silicon dioxide 2 in trench wall；
4th step, the deposit in groove forms silicon nitride 6, anti-etch silicon nitride 6；
5th step, in semiconductor material surface barrier metal is deposited, and is sintered to form schottky barrier junction 5, Ran Hou
Surface deposition metal forms upper surface metal level 10；
6th step, carries out back side metallization technology, overleaf forms lower surface metal layer 11, as shown in Figure 2.
The present invention is elaborated by examples detailed above, while the present invention, not office of the invention can also be realized using other examples
It is limited to above-mentioned instantiation, therefore the present invention is limited by scope.
Claims (8)
1. a kind of groove charge compensation Schottky semiconductor device, it is characterised in that：Including：
Substrate layer, is that the first conducting semiconductor material is constituted；
Drift layer, is that the first conducting semiconductor material is constituted, on substrate layer；It is multiple
Groove structure, groove is located in drift layer, trench wall region is abutted against in drift layer and is provided with the second conductive semiconductor material
Material, under-filled in groove to have insulant, groove internal upper part filling electrode metal, groove internal upper part electrode metal is led with second
Electric semiconductor material sidewalls are connected for ohmic contact regions, or groove internal upper part electrode metal and the second conducting semiconductor material side
Wall is isolated to arrange insulation material layer；
Schottky barrier junction, positioned at the first conducting semiconductor material upper surface.
2. semiconductor device as claimed in claim 1, it is characterised in that：Described substrate layer is the half of high concentration impurities doping
Conductor material.
3. semiconductor device as claimed in claim 1, it is characterised in that：Described substrate layer is included for high concentration impurities doping
Semiconductor material layer and low concentration impurity doping semiconductor material layer superimposed layer.
4. semiconductor device as claimed in claim 1, it is characterised in that：Insulant bag under-filled in described groove
Include as silicon dioxide.
5. semiconductor device as claimed in claim 1, it is characterised in that：The second described conducting semiconductor material upper surface is
Ohmic contact regions.
6. semiconductor device as claimed in claim 1, it is characterised in that：Described the second conducting semiconductor material and drift layer
First conducting semiconductor material includes forming charge compensation structure.
7. semiconductor device as claimed in claim 1, it is characterised in that：Described Schottky barrier becomes barrier metal and
The barrier junction that one conducting semiconductor material is formed.
8. a kind of preparation method of groove charge compensation Schottky semiconductor device as claimed in claim 1, it is characterised in that：
Comprise the steps：
1) constitute substrate layer surface in the first conducting semiconductor material and form the first conducting semiconductor material layer, then surface is formed
Silicon nitride layer；
2) carry out lithography corrosion process and remove surface portion silicon nitride layer, then etching removes partial denudation semi-conducting material and formed
Groove；
3) the second conductive impurity diffusion is carried out in groove；
4) silicon dioxide, anti-etching silicon dioxide, the surfaces nitrided silicon layer of erosion removal are deposited in groove；
5) barrier metal is deposited, is sintered to form schottky barrier junction, then in surface deposition metal, in groove internal upper part shape
Into electrode metal.
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| CN201210152685.2A CN103390652B (en) | 2012-05-07 | 2012-05-07 | Groove charge compensation schottky semiconductor device and manufacture method thereof |
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| CN103390652B true CN103390652B (en) | 2017-04-26 |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6710418B1 (en) * | 2002-10-11 | 2004-03-23 | Fairchild Semiconductor Corporation | Schottky rectifier with insulation-filled trenches and method of forming the same |
| CN102820294A (en) * | 2011-06-03 | 2012-12-12 | 飞兆半导体公司 | Integration of superjunction MOSFET and diode |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050242411A1 (en) * | 2004-04-29 | 2005-11-03 | Hsuan Tso | [superjunction schottky device and fabrication thereof] |
| JP2008034572A (en) * | 2006-07-28 | 2008-02-14 | Matsushita Electric Ind Co Ltd | Semiconductor device and manufacturing method therefor |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6710418B1 (en) * | 2002-10-11 | 2004-03-23 | Fairchild Semiconductor Corporation | Schottky rectifier with insulation-filled trenches and method of forming the same |
| CN102820294A (en) * | 2011-06-03 | 2012-12-12 | 飞兆半导体公司 | Integration of superjunction MOSFET and diode |
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Effective date of registration: 20210426 Address after: Room 301, 3rd floor, building 16, Guangxi Huike Technology Co., Ltd., No. 336, East extension of Beihai Avenue, Beihai Industrial Park, 536000, Guangxi Zhuang Autonomous Region Patentee after: Beihai Huike Semiconductor Technology Co.,Ltd. Address before: 113200 Liaoning Province Xinbin Manchu Autonomous County Federation of disabled persons Patentee before: Zhu Jiang |