CN103413761A - Insulated gate bipolar transistor and manufacturing method thereof - Google Patents
Insulated gate bipolar transistor and manufacturing method thereof Download PDFInfo
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- CN103413761A CN103413761A CN2013103633285A CN201310363328A CN103413761A CN 103413761 A CN103413761 A CN 103413761A CN 2013103633285 A CN2013103633285 A CN 2013103633285A CN 201310363328 A CN201310363328 A CN 201310363328A CN 103413761 A CN103413761 A CN 103413761A
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Abstract
The invention relates to the field of manufacturing of integrated circuits and discloses an insulated gate bipolar transistor and a manufacturing method of the insulated gate bipolar transistor. The manufacturing method of the insulated gate bipolar transistor includes the following steps of providing a second semiconductor type substrate, generating a first semiconductor type epitaxial layer on the substrate, generating a second semiconductor type trap located in the epitaxial layer, generating a first semiconductor type doping area located in the trap, generating an emitting electrode through hole, and generating a second semiconductor type doping area and an emitting electrode metal electrode through the emitting electrode through hole with the hole injection method. With the hole injection method, the second semiconductor type doping area and the emitting electrode metal electrode are connected together in a short circuit mode, the process of independently generating the second semiconductor type doping area is omitted, the number of photolithographic mask plates used for manufacturing the second semiconductor type doping area with the method is less than that of the photolithographic mask plates used in the traditional process by one, thus, the process development period is shortened, and the process cost is lowered. Meanwhile, the magnification factor of a parasitic transistor is effectively reduced, latching is restrained, and thus the safety of a work area is effectively improved.
Description
Technical field
The present invention relates to integrated circuit and manufacture field, particularly insulated gate bipolar transistor and manufacture method thereof.
Background technology
In recent years, along with the development of integrated circuit, insulated gate bipolar transistor (Insulated Gate Bipolar Transistor, be called for short IGBT) device because its to have tractive effort strong, characteristics low in energy consumption are at high speed motor car, and the domain requirements such as heavy mechanical equipment increase.IGBT is the vertical bipolar transistor work of metal-oxide-semiconductor driving by a planar structure.Wherein the emitter terminal short circuit of the source of MOS device and vertical pnp transistor is in the same place.
Fig. 1 and Fig. 2 are respectively the structural representations of traditional NMOS+SPNP and PMOS+SNPN type IGBT.As shown in Figure 1, this NMOS+SPNP type IGBT comprises P-trap 2, emitter metal electrode 3, groove-shaped gate regions 4, N+ type doped region 5 and the P+ type doped region 6 that is arranged in N-epitaxial loayer 1.
N+ type doped region 5 and P+ type doped region 6 are arranged in P-trap 2, and this N+ type doped region 5 and this P+ type doped region 6 are connected to form PN junction, and the doping depth of P+ type doped region 6 is identical with the doping depth of this N+ type doped region 5.One end of emitter metal electrode 3 is arranged in N+ type doped region 5 and P+ type doped region 6.The doping content of N+ type doped region 5 and P+ type doped region 6 is higher than the doping content of P-trap 2.Groove-shaped grid region 4 is around P-trap 2.
This NMOS+SPNP type IGBT also comprises collector electrode metal electrode 7, P+ type substrate 8, first grid dielectric layer 9, second gate dielectric layer 10 and gate metal electrode 11.
As shown in Figure 2, this PMOS+SNPN type IGBT is as long as exchange above-mentioned N district and P district.
Tradition NMOS+SPNP type IGBT manufacturing process flow comprises the following steps: the first step, growth N-extension on P type silicon chip; Second step, the well region photoetching; The 3rd step, trap are injected and diffusion; The 4th step, trench lithography; The 5th step, etching groove and gate oxidation; The 6th step, polysilicon deposit and photoetching; The 7th step, etching polysilicon; The 8th step, the source region photoetching; The 9th step, N+ source region Implantation and diffusion; The tenth step, the emitter photoetching; The 11 step, P+ emitter region Implantation and diffusion; The 12 step, contact hole forms; The 13 step, metal level deposit, photoetching, etching; The 14 step, thinning back side, inject and metallization.And the manufacturing process flow of traditional PMOS+SNPN type IGBT, as long as above-mentioned N district and P district are exchanged.
Existing IGBT manufacturing process is all that the emitter of bipolar transistor is realized as a lithography layer, has not only extended the development time, and has increased process costs.
How can reduce the time of process exploitation and technique flow, especially can reduce development cost, be to need the problem solved.
Summary of the invention
The object of the present invention is to provide a kind of insulated gate bipolar transistor and manufacture method thereof, the process exploitation cycle of IGBT is shortened, process costs reduces greatly.Simultaneously, effectively reduce the multiplication factor of parasitic transistor, suppress latch phenomenon, and then the safety operation area of effectively improving IGBT.
For solving the problems of the technologies described above, embodiments of the present invention disclose a kind of manufacture method of insulated gate bipolar transistor, comprise the following steps:
The second semiconductor type substrate is provided;
On this substrate, generate the first semiconductor type epitaxial loayer;
Generation is arranged in the second semiconductor type trap of epitaxial loayer;
Generation is arranged in the first semiconductor type doped region of trap;
Generate emitter via, and adopt the method for hole injection to generate the second semiconductor type doped region and emitter metal electrode by emitter via, wherein,
This second semiconductor type doped region is arranged in above-mentioned trap, this the second semiconductor type doped region and the first semiconductor type doped region are connected to form PN junction, the doping depth of this second semiconductor type doped region is darker than the doping depth of this first semiconductor type doped region, and
One end of emitter metal electrode is arranged in this first semiconductor type doped region, and this second semiconductor type doped region is connected with this emitter metal electrode, and this second semiconductor type doped region is positioned at the below of this emitter metal electrode, and
The doping content of above-mentioned the first semiconductor type doped region and the second semiconductor type doped region is higher than the doping content of above-mentioned trap.
Embodiments of the present invention also disclose a kind of insulated gate bipolar transistor, comprise the second semiconductor type trap, emitter metal electrode, groove-shaped gate regions, the first semiconductor type doped region and the second semiconductor type doped region that are arranged in the first semiconductor type epitaxial loayer;
This first semiconductor type doped region and the second semiconductor type doped region are arranged in above-mentioned trap, this the first semiconductor type doped region and the second semiconductor type doped region are connected to form PN junction, and the doping depth of this second semiconductor type doped region is darker than the doping depth of this first semiconductor type doped region;
One end of emitter metal electrode is arranged in above-mentioned the first semiconductor type doped region, and above-mentioned the second semiconductor type doped region is connected with this emitter metal electrode, and this second semiconductor type doped region is positioned at the below of this emitter metal electrode;
Above-mentioned groove-shaped grid region is around above-mentioned trap;
The doping content of above-mentioned the first semiconductor type doped region and the second semiconductor type doped region is higher than the doping content of above-mentioned trap.
Compared with prior art, the main distinction and effect thereof are embodiment of the present invention:
By generating emitter via, the method that adopts hole to inject, generate the second semiconductor type doped region and emitter metal electrode, the second semiconductor type doped region and emitter metal electric pole short circuit are in the same place, saved the technique that independent generation the second semiconductor type doped region needs, thereby the process exploitation cycle of IGBT is shortened, and process costs reduces greatly.Simultaneously, the doping depth of the second semiconductor type doped region is darker than the doping depth of the first semiconductor type doped region, make the base concentration below the first semiconductor type doped region denseer, effectively reduce the multiplication factor of parasitic transistor, suppress latch phenomenon, and then the safety operation area of effectively improving IGBT.
Further, by emitter via, injecting the second semiconductor type doping ion, can be fewer with a mask blank of making the second semiconductor type doped region than traditional handicraft, thus the construction cycle of shortening IGBT greatly reduces production costs.
The accompanying drawing explanation
Fig. 1 is the structural representation of a kind of NMOS+SPNP type insulated gate bipolar transistor in prior art;
Fig. 2 is the structural representation of a kind of PMOS+SNPN type insulated gate bipolar transistor in prior art;
Fig. 3 is the schematic flow sheet of a kind of manufacture method of insulated gate bipolar transistor in first embodiment of the invention;
Fig. 4 is the structural representation of a kind of insulated gate bipolar transistor in four embodiment of the invention.
Fig. 5 is the structural representation of a kind of NMOS+SPNP type insulated gate bipolar transistor in four embodiment of the invention.
Fig. 6 is the structural representation of a kind of PMOS+SNPN type insulated gate bipolar transistor in four embodiment of the invention.
Embodiment
In the following description, in order to make the reader understand the application better, many ins and outs have been proposed.But, persons of ordinary skill in the art may appreciate that even without these ins and outs with based on many variations and the modification of following each execution mode, also can realize each claim of the application technical scheme required for protection.
For making the purpose, technical solutions and advantages of the present invention clearer, below in conjunction with accompanying drawing, embodiments of the present invention are described in further detail.
First embodiment of the invention relates to the manufacture method of a kind of IGBT.Fig. 3 is the schematic flow sheet of the manufacture method of this IGBT.
Specifically, as shown in Figure 3, the manufacture method of this insulated gate bipolar transistor comprises the following steps:
In step 301, provide the second semiconductor type substrate.
After this enter step 302, on this substrate, generate the first semiconductor type epitaxial loayer.
Be appreciated that in the embodiments of the present invention, epitaxy layer thickness can be done comprehensive consideration according to the requirement of puncture voltage, saturation voltage drop and dynamic parameter, makes corresponding variation.
After this enter step 303, generate the second semiconductor type trap that is arranged in above-mentioned epitaxial loayer.
Be appreciated that in the embodiments of the present invention, in the second semiconductor type trap, the dosage of dopant implant ion and energy demand are adjusted according to the needs of bipolar transistor in IGBT and MOSFET.
After this enter step 304, generate the first semiconductor type doped region that is arranged in above-mentioned trap.
This step 304 comprises following sub-step:
By lithographic definition the first semiconductor type doped region.
The injection of the first semiconductor type ion and diffusion.
Before step 304, further comprising the steps of:
Generate groove-shaped gate regions.
In the step that generates groove-shaped gate regions, comprise following sub-step:
Trench region by photoetching and the groove-shaped gate regions of etching definition.
Carry out the gate oxidation growth.
Depositing polysilicon in trench region.
Photoetching and etch polysilicon are to form groove-shaped gate regions.
In addition, be appreciated that the etch stages in groove-shaped gate regions, the degree of depth and the puncture voltage of etching groove have correlation, need to etch according to performance requirement the groove of different depth.
After this enter step 305, generate emitter via, and adopt the method for hole injection to generate the second semiconductor type doped region and emitter metal electrode by emitter via, wherein,
This second semiconductor type doped region is arranged in above-mentioned trap, this the second semiconductor type doped region and the first semiconductor type doped region are connected to form PN junction, the doping depth of this second semiconductor type doped region is darker than the doping depth of this first semiconductor type doped region, and
One end of above-mentioned emitter metal electrode is arranged in this first semiconductor type doped region, and above-mentioned the second semiconductor type doped region is connected with this emitter metal electrode, and this second semiconductor type doped region is positioned at the below of this emitter metal electrode, and
The doping content of this first semiconductor type doped region and the second semiconductor type doped region is higher than the doping content of trap.
This step 305 comprises following sub-step:
Generate first grid insulating medium layer and second gate insulating medium layer.
Photoetching and etching emitter via.
In emitter via, inject the second semiconductor type doping ion.
Metal level deposit, photoetching and etching, form the emitter metal electrode.
In the present embodiment, emitter via and gate via adopt the same mask plate through photoetching and etching, to generate simultaneously, thereby, when metal level deposit, photoetching and etching, when forming the emitter metal electrode, have also formed the gate metal electrode.
In addition, be appreciated that the gate metal electrode also can generate separately in other execution modes of the present invention.
In the present embodiment, first grid dielectric layer is silicon dioxide, and the second gate dielectric layer is boron-phosphorosilicate glass.
In addition, be appreciated that in other execution modes of the present invention, first grid medium and second gate medium can be other dielectric materials, as silicon nitride, silicon oxynitride etc.
In addition, be appreciated that if need larger multiplication factor, can adopt after repeatedly injecting the method spread again to obtain dark and uniform the second semiconductor type doped region of CONCENTRATION DISTRIBUTION.
By in emitter via, injecting the second semiconductor type doping ion, can be fewer with a mask blank of making the second semiconductor type doped region than traditional handicraft, thus the construction cycle of shortening IGBT greatly reduces production costs.
After step 305, further comprising the steps of:
Silicon chip back side attenuate and injection.
Metallization spanning set electrode metal electrode.
By generating emitter via, the method that adopts hole to inject, generate the second semiconductor type doped region and emitter metal electrode, the second semiconductor type doped region and emitter metal electric pole short circuit are in the same place, saved the technique that independent generation the second semiconductor type doped region needs, thereby the process exploitation cycle of IGBT is shortened, and process costs reduces greatly.Simultaneously, the doping depth of the second semiconductor type doped region is darker than the doping depth of the first semiconductor type doped region, make the base concentration below the first semiconductor type doped region denseer, effectively reduce the multiplication factor of parasitic transistor, suppress latch phenomenon, and then the safety operation area of effectively improving IGBT.
Second embodiment of the invention relates to the manufacture method of a kind of IGBT.The first semiconductor type of this IGBT is N-type, namely manufactures NMOS+SPNP type IGBT.
Present embodiment is manufactured the method for NMOS+SPNP type IGBT, comprises the following steps:
The first step, epitaxial growth N-type epitaxial loayer on P type silicon chip;
Second step, carry out high pressure P trap (HVPW) and inject;
The 3rd step, carry out trench lithography, etching;
The 4th step, carry out gate oxide growth;
The 5th step, polysilicon gate deposit, etching polysilicon;
The 6th step, source region (i.e. the first semiconductor type doped region) photoetching;
The 7th step, source region are injected and diffusion;
The 8th step, contact hole (being emitter via) photoetching;
The 9th step, contact hole oxide layer etching, then carry out contact hole silicon etching and contact hole and inject;
The tenth step, metal level deposit, photoetching and etching;
The 11 step, the silicon chip back side attenuate, inject and metallization.
Specifically, in present embodiment, the detailed process of this NMOS+SPNP type of manufacture IGBT is as follows:
At first growth N-type epitaxial loayer on P type backing material, according to the different requirements of puncture voltage, epitaxy layer thickness is done corresponding variation.The thickness of epitaxial loayer will be according to puncture voltage, saturation voltage drop, and comprehensive consideration is done in the requirement of dynamic parameter.Secondly, carry out the injection of P trap, the dosage of injection and energy will meet the needs of bipolar transistor and MOSFET.In the etching groove stage, the degree of depth and the puncture voltage of etching groove have correlation, need to etch according to performance requirement the groove of different depth.Carry out subsequently gate oxide growth, gate polysilicon deposit, etching form gate electrode (being groove-shaped grid region).Carry out again source region photoetching (i.e. the first semiconductor type doped region photoetching), inject and diffusion.Carry out again undoped silicon dioxide deposit, boron-phosphorosilicate glass deposit and backflow, the contact hole photoetching, contact hole oxide layer etching, the contact hole silicon etching also carries out emitter region (i.e. the second semiconductor type doped region) injection and the diffusion of the PNP transistor in this IGBT.Because emitter (i.e. the second semiconductor type doped region) injection of this PNP transistor is injected after contact hole etching silicon, make i.e. the first semiconductor type doped region of N+() below base concentration denseer, effectively reduce the multiplication factor of parasitic NPN transistor, suppress latch-up, and then effectively improved the safety operation area of IGBT.Thinning back side is carried out in the final step of technique, injects and metallization.
Present embodiment is that manufacture the first semiconductor type proposed on the basis of the first execution mode is the more specifically method of the IGBT of N-type, the correlation technique details of mentioning in the first execution mode is still effective in the present embodiment, in order to reduce repetition, repeat no more here.Correspondingly, the correlation technique details of mentioning in present embodiment also can be applicable in the first execution mode.
Third embodiment of the invention relates to the manufacture method of a kind of IGBT.The first semiconductor type of this IGBT is the P type, namely manufactures PMOS+SNPN type IGBT.
Present embodiment is manufactured the method for PMOS+SNPN type IGBT, comprises the following steps:
The first step, at the upper epitaxial growth P type epitaxial loayer of N-type silicon chip (being the N-type substrate);
Second step, carry out high pressure N trap (HVNW) and inject;
The 3rd step, carry out trench lithography, etching;
The 4th step, carry out gate oxide growth;
The 5th step, polysilicon gate deposit, etching polysilicon;
The 6th step, source region (i.e. the first semiconductor type doped region) photoetching;
The 7th step, source region are injected and diffusion;
The 8th step, contact hole (being emitter via) photoetching;
The 9th step, contact hole oxide layer etching, then carry out contact hole silicon etching and contact hole and inject;
The tenth step, metal level deposit, photoetching and etching;
The 11 step, the silicon chip back side attenuate, inject, and metallization.
Specifically, in present embodiment, the detailed process of this PMOS+SNPN type of manufacture IGBT is as follows:
At first growing P-type epitaxial loayer on the N-type backing material, according to the different requirements of puncture voltage, epitaxy layer thickness is done corresponding variation.Secondly, carry out the injection of N trap, the dosage of injection and energy will meet the needs of bipolar transistor and MOSFET.In the etching groove stage, the degree of depth and the puncture voltage of etching groove have correlation, need to etch according to performance requirement the groove of different depth.Carry out subsequently gate oxide growth, gate polysilicon deposit, etching form gate electrode (being groove-shaped grid region).Carry out again source region photoetching (i.e. the first semiconductor type doped region photoetching), inject and diffusion.Carry out again undoped silicon dioxide deposit, boron-phosphorosilicate glass deposit and backflow, the contact hole photoetching, finally carry out emitter via etching, injection and metallization.If need larger multiplication factor, can adopt after repeatedly injecting the way spread again to obtain dark and the uniform emitter junction of CONCENTRATION DISTRIBUTION, purpose reduces base width exactly.
Present embodiment is that manufacture the first semiconductor type proposed on the basis of the first execution mode is the more specifically method of the IGBT of P type, the correlation technique details of mentioning in the first execution mode is still effective in the present embodiment, in order to reduce repetition, repeat no more here.Correspondingly, the correlation technique details of mentioning in present embodiment also can be applicable in the first execution mode.
Four embodiment of the invention relates to a kind of IGBT, and Fig. 4 is the structural representation of this IGBT.
Specifically, as shown in Figure 4, this IGBT comprises the second semiconductor type trap 2, emitter metal electrode 3, groove-shaped gate regions 4, the first semiconductor type doped region 5 and the second semiconductor type doped region 6 that is arranged in the first semiconductor type epitaxial loayer 1.
The first semiconductor type doped region 5 and the second semiconductor type doped region 6 are arranged in above-mentioned trap 2, this the first semiconductor type doped region 5 and this second semiconductor type doped region 6 are connected to form PN junction, and the doping depth of this second semiconductor type doped region 6 is darker than the doping depth of this first semiconductor type doped region 5.
One end of emitter metal electrode 3 is arranged in the first semiconductor type doped region 5, the second semiconductor type doped regions 6 and is connected with this emitter metal electrode 3, and this second semiconductor type doped region 6 is positioned at the below of this emitter metal electrode 3.
Groove-shaped grid region 4 is around trap 2.
The doping content of the first semiconductor type doped region 5 and the second semiconductor type doped region 6 is higher than the doping content of trap 2.
In the present embodiment, groove-shaped gate regions 4 is polysilicon, and the polysilicon in groove is interconnected.
In the present embodiment, this IGBT also comprises collector electrode metal electrode 7, the second semiconductor type substrate 8, first grid dielectric layer 9, second gate dielectric layer 10 and gate metal electrode 11.
In the present embodiment, preferably, the first semiconductor type is N-type, and described the second semiconductor type is the P type.Be appreciated that in other execution modes of the present invention, the first semiconductor type also can be the P type, and the second semiconductor type is N-type.
The doping depth of the second semiconductor type doped region 6 is darker than the doping depth of the first semiconductor type doped region 5, make the following base concentration of the first semiconductor type doped region 5 denseer, effectively reduce the multiplication factor of parasitic transistor, suppress latch phenomenon, and then the safety operation area of effectively improving IGBT.
Fig. 5 shows a preference of present embodiment, and namely the first semiconductor type is the structural representation of the NMOS+SPNP type IGBT of N-type.This NMOS+SPNP type IGBT comprises a vertical nmos device and the vertical PNP bipolar transistor driven by this nmos device.
Specifically, as shown in Figure 5, the P+ zone 8(formed after P type trap 2 injection regions and N-type epitaxial loayer 1 and the back of the body inject i.e. the second semiconductor type substrate) formed the vertical PNP bipolar transistor of IGBT device.The groove formed through over etching need to pass through thermal oxidation, and it is groove-shaped gate regions that polysilicon is filled the grid 4(that then forms metal-oxide-semiconductor), the polysilicon in groove is interconnected.N-type epitaxial loayer 1, P type trap 2 and surperficial N+ district 5(are the first semiconductor doping district), formed together nmos device.In figure, also show the first grid dielectric layer 9 that the emitter metal electrode 3, collector electrode metal electrode 7, silicon dioxide of this IGBT form, second gate dielectric layer 10 and the gate metal electrode 11 that boron-phosphorosilicate glass forms.
Fig. 6 shows a preference of present embodiment, and namely the first semiconductor type is the structural representation of the PMOS+SNPN type IGBT of P type.
Specifically, as shown in Figure 6, this IGBT drives a bipolar npn transistor by a PMOS pipe.There is shown the first grid dielectric layer 9 that the P type epitaxial loayer 1, N-type trap 2, emitter metal electrode 3, groove-shaped grid region 4, P type doped region 5, N-type doped region 6, collector electrode metal electrode 7, N type semiconductor substrate 8, silicon dioxide of this IGBT form, second gate dielectric layer 10 and the gate metal electrode 11 that boron-phosphorosilicate glass forms.Electric current by the PMOS pipe is as the base current of bipolar transistor.Because the area of bipolar npn transistor junction Area Ratio PMOS inversion layer is many greatly, so this IGBT can bear very large current density.
First, second, third execution mode is the method execution mode corresponding with present embodiment, present embodiment can with the enforcement of working in coordination of first, second, third execution mode.The correlation technique details of mentioning in first, second, third execution mode is still effective in the present embodiment, in order to reduce repetition, repeats no more here.Correspondingly, the correlation technique details of mentioning in present embodiment also can be applicable in first, second, third execution mode.
It should be noted that, in the claim and specification of this patent, relational terms such as the first and second grades only is used for an entity or operation are separated with another entity or operating space, and not necessarily requires or imply between these entities or operation the relation of any this reality or sequentially of existing.And, term " comprises ", " comprising " or its any other variant are intended to contain comprising of nonexcludability, thereby make the process, method, article or the equipment that comprise a series of key elements not only comprise those key elements, but also comprise other key elements of clearly not listing, or also be included as the intrinsic key element of this process, method, article or equipment.In the situation that not more restrictions, the key element that " comprises " and limit by statement, and be not precluded within process, method, article or the equipment that comprises described key element and also have other identical element.
Although pass through with reference to some of the preferred embodiment of the invention, the present invention is illustrated and describes, but those of ordinary skill in the art should be understood that and can to it, do various changes in the form and details, and without departing from the spirit and scope of the present invention.
Claims (10)
1. the manufacture method of an insulated gate bipolar transistor, is characterized in that, comprises the following steps:
The second semiconductor type substrate is provided;
On this substrate, generate the first semiconductor type epitaxial loayer;
Generation is arranged in the second semiconductor type trap of described epitaxial loayer;
Generation is arranged in the first semiconductor type doped region of described trap;
Generate emitter via, and adopt the method that hole is injected to generate the second semiconductor type doped region and emitter metal electrode by described emitter via, wherein,
This second semiconductor type doped region is arranged in described trap, this the second semiconductor type doped region and described the first semiconductor type doped region are connected to form PN junction, the doping depth of this second semiconductor type doped region is darker than the doping depth of this first semiconductor type doped region, and
One end of described emitter metal electrode is arranged in this first semiconductor type doped region, and described the second semiconductor type doped region is connected with this emitter metal electrode, and this second semiconductor type doped region is positioned at the below of this emitter metal electrode, and
The doping content of described the first semiconductor type doped region and described the second semiconductor type doped region is higher than the doping content of described trap.
2. the manufacture method of insulated gate bipolar transistor according to claim 1, it is characterized in that, in described generation emitter via, and adopt the method that hole is injected by described emitter via, to generate the step of the second semiconductor type doped region and emitter metal electrode, comprise following sub-step:
Generate first grid insulating medium layer and second gate insulating medium layer;
The described emitter via of photoetching and etching;
In emitter via, inject the second semiconductor type doping ion;
Metal level deposit, photoetching and etching, form described emitter metal electrode.
3. the manufacture method of insulated gate bipolar transistor according to claim 1, is characterized in that, in described generation, is arranged in the step of the first semiconductor type doped region of described trap, comprises following sub-step:
By lithographic definition the first semiconductor type doped region;
The injection of the first semiconductor type ion and diffusion.
4. the manufacture method of insulated gate bipolar transistor according to claim 1, is characterized in that, before in described generation, being arranged in the step of the first semiconductor type doped region of described trap, further comprising the steps of:
Generate groove-shaped gate regions.
5. the manufacture method of insulated gate bipolar transistor according to claim 1, it is characterized in that, in described generation emitter via, and after adopting the step of method by described emitter via generation the second semiconductor type doped region and emitter metal electrode of hole injection, further comprising the steps of:
Silicon chip back side attenuate and injection;
Metallization spanning set electrode metal electrode.
6. the manufacture method of insulated gate bipolar transistor according to claim 4, is characterized in that, in the step of the groove-shaped gate regions of described generation, comprises following sub-step:
Trench region by photoetching and the described groove-shaped gate regions of etching definition;
Carry out the gate oxidation growth;
Depositing polysilicon in described trench region;
Photoetching and etch polysilicon are to form described groove-shaped gate regions.
7. according to the manufacture method of the described insulated gate bipolar transistor of any one in claim 1 to 6, it is characterized in that, described first grid dielectric layer is silicon dioxide, and described second gate dielectric layer is boron-phosphorosilicate glass.
8. insulated gate bipolar transistor, it is characterized in that, comprise the second semiconductor type trap, emitter metal electrode, groove-shaped gate regions, the first semiconductor type doped region and the second semiconductor type doped region that are arranged in the first semiconductor type epitaxial loayer;
Described the first semiconductor type doped region and described the second semiconductor type doped region are arranged in described trap, this the first semiconductor type doped region and this second semiconductor type doped region are connected to form PN junction, and the doping depth of this second semiconductor type doped region is darker than the doping depth of this first semiconductor type doped region;
One end of described emitter metal electrode is arranged in described the first semiconductor type doped region, and described the second semiconductor type doped region is connected with this emitter metal electrode, and this second semiconductor type doped region is positioned at the below of this emitter metal electrode;
Described groove-shaped grid region is around described trap;
The doping content of described the first semiconductor type doped region and described the second semiconductor type doped region is higher than the doping content of described trap.
9. insulated gate bipolar transistor according to claim 8, is characterized in that, also comprises collector electrode metal electrode, the second semiconductor type substrate, first grid dielectric layer, second gate dielectric layer and gate metal electrode.
10. insulated gate bipolar transistor according to claim 9, is characterized in that, described groove-shaped gate regions is polysilicon.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN114497308A (en) * | 2022-01-27 | 2022-05-13 | 宁波安芯美半导体有限公司 | Semiconductor structure, preparation method and application |
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| US5637898A (en) * | 1995-12-22 | 1997-06-10 | North Carolina State University | Vertical field effect transistors having improved breakdown voltage capability and low on-state resistance |
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| CN114497308B (en) * | 2022-01-27 | 2023-11-28 | 宁波安芯美半导体有限公司 | Semiconductor structure, preparation method and application |
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Application publication date: 20131127 |