CN103427795A - Matrix pulse signal generation circuit and generation method - Google Patents
Matrix pulse signal generation circuit and generation method Download PDFInfo
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- CN103427795A CN103427795A CN2013103495213A CN201310349521A CN103427795A CN 103427795 A CN103427795 A CN 103427795A CN 2013103495213 A CN2013103495213 A CN 2013103495213A CN 201310349521 A CN201310349521 A CN 201310349521A CN 103427795 A CN103427795 A CN 103427795A
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Abstract
The invention discloses a matrix pulse signal generation circuit. The matrix pulse signal generation circuit comprises a frequency-adjustable annular oscillator and a pulse generation circuit, wherein the input end of the frequency-adjustable annular oscillator is connected to an enable signal and is connected to frequency adjusting signals c1-cj respectively while the output end outputs a periodic output frequency signal and is connected to an input end of the pulse generation circuit; the input end of the pulse generation circuit is also connected with a pulse generation control signal while the output end outputs a matrix pulse signal. A matrix pulse signal generation method comprises the following steps: A, setting the frequency adjusting signals c1-cj and outputting the frequency adjusting signals to the input end of the frequency-adjustable annular oscillator; B, setting the pulse generation control signal to carry out setting and resetting operations for the pulse generation circuit, and setting the pulse generation control signal at a high electric level after the setting and resetting operations are finished; C, setting an allowable enable signal for the frequency-adjustable annular oscillator to enable the frequency-adjustable annular oscillator to oscillate so as to generate and output a frequency signal, outputting the frequency signal to the pulse generation circuit, and then generating the rectangular pulse signal.
Description
Technical field
The present invention relates to the semiconductor integrated circuit field, be specifically related to a kind of matrix pulse signal generating circuit and production method.
Background technology
Pulse signal refers to that shorter, width of duration and amplitude have voltage or the current signal of specific change rule, and common pulse signal has rectangle, zigzag, bell and digital coding sequence etc.Pulse signal generating circuit is widely used in the fields such as switch control, digital circuit dynamic characteristic test.
Pulse signal generator of a great variety, performance is different, but most of pulse signal generators are all adopt Analog Circuit Design or adopt existing circuit elements device to be built, this pulse signal generating circuit structure can't be compatible mutually with the digital CMOS integrated circuit fabrication process of current main flow, can not be integrated in the middle of Design of Digital Integrated Circuit.Certainly, by the High Frequency Digital PLL circuit, can realize pulse-generating circuit, but this mode is not only former assorted, and cost is higher, needs accurate low frequency input clock; Simultaneously, the method realizes that the nanosecond pulse width signal is also more difficult.Also having some pulse-generating circuits is to utilize input signal and do a logical operation through the signal after postponing to produce, but it does not consider how to realize the detection of pulse-width, especially when pulse duration, need pulse-width to monitor in real time during with technique, voltage, variations in temperature.
Summary of the invention
The object of the present invention is to provide a kind of matrix pulse signal generating circuit and production method, solving the existing circuit that produces can't be compatible mutually with digital CMOS process, and the pulse-width regulated scope is little, realizes nanosecond pulsewidth difficulty, needs the problem of external frequency input.
The present invention is achieved through the following technical solutions:
A kind of matrix pulse signal generating circuit, is characterized in that, comprises frequency tunable ring oscillator and pulse-generating circuit; The input of frequency tunable ring oscillator is connected with enable signal, and with frequency adjusted signal c1～cj, is connected respectively; Frequency tunable ring oscillator output is exported periodic output frequency signal, and is connected with the input of pulse-generating circuit; The input of pulse-generating circuit also produces control signal with pulse and is connected, the output output rectangular pulse signal of pulse-generating circuit;
Described frequency tunable ring oscillator comprises k inverter, two input nand gates and j alternative circuit, and wherein, k is even number; The output of the first inverter connects respectively the input of the second inverter and the input a of alternative circuit M1～Mj, and the corresponding rate of connections of the selecting side s of alternative circuit M1～Mj is adjusted signal c1～cj; The output of the second inverter connects the input of the 3rd inverter, the output of the 3rd inverter connects the input b of alternative circuit M1, the output y of alternative circuit M1～Mj-1 is connected with the input b of the alternative circuit M2～Mj of next stage by the inverter of two cascades successively, the output y of alternative circuit Mj connects the input of q inverter, the output cascade k-q level inverter of q inverter; The output of k inverter is connected with the first input end of two input nand gates, the second input of two input nand gates is connected with enable signal, the output of two input nand gates is connected with the input of the first inverter, simultaneously as the output of frequency tunable ring oscillator, and export periodic output frequency signal.
Preferably, described pulse-generating circuit comprises a trigger with the set end and m-1 the trigger with reset terminal; Pulse produce control signal respectively with pulse-generating circuit in the set end of trigger DFF1, and in pulse-generating circuit, the reset terminal of trigger DFF2～DFFm is connected; The output frequency signal of frequency tunable ring oscillator is connected with the input end of clock of trigger DFF1～DFFm in pulse-generating circuit respectively;
The data output end of trigger DFF1～DFFm-1 is connected with the data input pin of the trigger DFF2～DFFm of next stage successively; The data output end of trigger DFFm is connected with the data input pin of DFF1, and the while is as the output of pulse-generating circuit, and the output rectangular pulse signal.
Preferably, also comprise for original frequency being adjusted to signal a
1～a
nChange and be output as the frequency regulating circuit of frequency adjusted signal c1～cj.
Further, described frequency regulating circuit adopts the n-2 of standard
nDecoding circuit; The input of frequency regulating circuit and original frequency are adjusted signal a
1～a
nBe connected, the output output frequency is adjusted signal c1～cj, wherein, and j=2
n.
Preferably, the output of described frequency tunable ring oscillator also is connected with the frequency output monitoring circuit for output frequency signal is monitored.
Further, described frequency output monitoring circuit adopts the X frequency dividing circuit, and its input is connected with enable signal with the output frequency signal of frequency tunable ring oscillator respectively, output output frequency pilot signal.
A kind of matrix pulse signal genration method, is characterized in that, comprises the steps:
A. setpoint frequency is adjusted signal c1～cj and is outputed to the input of frequency tunable ring oscillator;
B. given pulse generation control signal paired pulses generation circuit carries out set and reset operation, after completing, pulse is produced to control signal and is set to high level;
C. to the enable signal of the given permission of frequency tunable ring oscillator, the starting of oscillation of frequency tunable ring oscillator produces the periodic output frequency signal of frequency of oscillation, and outputs to pulse-generating circuit from output; Frequency adjusted signal c1 by setting in the A step～cj, control the frequency of output frequency signal; Producing control signal by the pulse in the B step makes to produce rectangular pulse signal after the pulse-generating circuit operation.
Preferably, by adjusting in pulse-generating circuit with the number of reset terminal trigger, can adjust the duty ratio of rectangular pulse signal.
Preferably, described frequency adjusted signal c1～cj adjusts signal a by original frequency
1～a
nOutput after the frequency regulating circuit conversion.
Preferably, described enable signal and output frequency signal frequency division are connected to the input of frequency output monitoring circuit, by the pilot signal of frequency output monitoring circuit frequency reducing output, realize the monitoring to output frequency signal.
Compared with prior art, the present invention has following useful technique effect:
A kind of matrix pulse signal generating circuit of the present invention, utilization comprises k inverter, the frequency tunable ring oscillator of two input nand gates and j alternative circuit produces periodic oscillation frequency signal as output frequency signal by the vibration of self, without external incoming frequency source, circuit structure is simple, and together form pure digi-tal with pulse-generating circuit, can be fully compatible with digital CMOS process.
Further, utilize the shift register chain structure generation rectangular pulse in pulse-generating circuit, and can obtain the rectangular pulse signal of different duty by the number that trigger in the shift register chain structure is set, increased the adaptability of the rectangular pulse signal of output.
Further, utilize frequency regulating circuit n the original frequency as initial control signal can be adjusted to signal a
1～a
nDecoding converts j frequency adjusted signal c1～cj to as direct control signal, n<j wherein, therefore reduce the number of drawing of initial control signal, realized obtaining more pulse duration state by the least possible control signal, and then can adjust signal a by the original frequency less to number
1～a
nAdjustment realize that narrow pulse width precision reaches nanosecond; N-2 when frequency regulating circuit employing standard
nDuring decoding circuit, j=2
n.
Further, utilize frequency output monitoring circuit to carry out frequency division to the output frequency signal of frequency tunable ring oscillator, mode by frequency reducing is exported output frequency signal indirectly, realize the monitoring to output frequency signal with the frequency monitoring signal of output, thereby can access the concrete width of pulsewidth, realize feedback or subsequent operation.
A kind of matrix pulse signal genration of the present invention method, realize the FREQUENCY CONTROL to the output frequency signal of frequency tunable ring oscillator by the change to frequency adjusted signal, thereby realize the adjustment to the rectangular pulse width, simple to operate.
Further, by change, adjust the number with the reset terminal trigger in pulse-generating circuit, change the duty ratio of rectangular pulse signal; By original frequency is adjusted to signal a
1～a
nDecoding conversion, increased direct control signal number, can reduce the number of drawing of control signal, also realized the control of nanosecond width simultaneously; By the frequency division to output frequency signal, utilize the mode of frequency reducing indirectly output frequency signal to be realized to output, realize the monitoring to output frequency signal with the pilot signal of output, can be real-time monitor the variation that pulsewidth produces with factors such as technique, temperature, voltages, thereby can adjust in time and change, applying flexible is convenient, applied widely.
The accompanying drawing explanation
The waveform schematic diagram that Fig. 1 is the various signals that produce under condition described in example of the present invention.
Fig. 2 produces the structural principle block diagram of circuit described in example of the present invention.
Fig. 3 produces the structure chart of circuit described in example of the present invention.
In figure: 811 is frequency regulating circuit; 812 is frequency output monitoring circuit; 813 is the frequency tunable ring oscillator; 814 is pulse-generating circuit; En is enable signal; b
1For pulse produces control signal; f
outFor output frequency signal; P
outFor rectangular pulse signal; f
monFor the frequency monitoring signal; Inv1, inv2 ..., invq ... invk is the first inverter, the second inverter ..., the q inverter ..., the k inverter; S is the set end; R is reset terminal; CK is input end of clock; Q is data output end; D is data input pin.
Embodiment
Below in conjunction with specific embodiment, the present invention is described in further detail, and the explanation of the invention is not limited.
Referring to Fig. 2, a kind of matrix pulse signal generating circuit of the present invention, it comprises frequency tunable ring oscillator 813 and pulse-generating circuit 814; The input of frequency tunable ring oscillator 813 is connected with enable signal en, and with frequency adjusted signal c1～cj, is connected respectively; Frequency tunable ring oscillator 813 outputs are exported periodic output frequency signal f
out, and be connected with the input of pulse-generating circuit 814; The input of pulse-generating circuit 814 also produces control signal b with pulse
1Be connected, the output output rectangular pulse signal P of pulse-generating circuit 814
outWherein, in this preferred embodiment, as shown in Figure 2, also comprise for original frequency being adjusted to signal a
1～a
nChange and be output as the frequency regulating circuit 811 of frequency adjusted signal c1～cj.Frequency regulating circuit 811 adopts the n-2 of standard as shown in Figure 3
nDecoding circuit, realize original frequency is adjusted to signal a
1～a
nDecoding; The input of frequency regulating circuit 811 and original frequency are adjusted signal a
1～a
nBe connected, the output output frequency is adjusted signal c1～cj, wherein, and j=2
n.The effect of frequency regulating circuit 811 is that n the original frequency as control signal adjusted to signal a
1～a
n Convert 2 to
nIndividual frequency adjusted signal c1～cj, as control signal, reduces control signal and draws number, realizes obtaining more pulse duration state by the least possible control signal.
Enable signal en is for whether starting of oscillation of control frequency tunable ring oscillator 813; Frequency adjusted signal c1～cj, for changing the output frequency of frequency tunable ring oscillator 813, realizes the width of regulating impulse signal; Original frequency is adjusted signal a
1～a
nFor initial control signal is provided, control frequency is adjusted the order of magnitude of signal c1～cj; Pulse produces control signal b
1Realize that paired pulses produces the reset function of circuit 814; The output signal P of pulse-generating circuit 814
outPulse output signals for nanosecond rectangular pulse width adjustable signal generation circuit.
As shown in Figure 3, frequency tunable ring oscillator 813 comprises k inverter, two input nand gates and j alternative circuit, and wherein, k is even number; Correspondence preferred embodiment, wherein, j=2
nThe output of the first inverter inv1 connects respectively the input of the second inverter inv2 and the input a of alternative circuit M1～Mj, and the corresponding rate of connections of the selecting side s of alternative circuit M1～Mj is adjusted signal c1～cj; The output of the second inverter inv2 connects the input of the 3rd inverter inv3, the output of the 3rd inverter inv3 connects the input b of alternative circuit M1, the output y of alternative circuit M1～Mj-1 is connected with the input b of the alternative circuit M2～Mj of next stage by the inverter of two cascades successively, wherein, the inverter of two cascades can slow down hunting speed when not changing sense, improves the controllability of circuit; The output y of alternative circuit Mj connects the input of q inverter invq, the output cascade k-q level inverter of q inverter invq; The output of k inverter invk is connected with the first input end of two input nand gates, the second input of two input nand gates is connected with enable signal en, the output of two input nand gates is connected with the input of the first inverter inv1, simultaneously as the output of frequency tunable ring oscillator 813, and export periodic output frequency signal f
out.
Preferably, as shown in Figure 3, pulse-generating circuit 814 comprises a trigger with set end S and m-1 the trigger with reset terminal R; Pulse produces control signal b
1Respectively with pulse-generating circuit 814 in the set end S of trigger DFF1, and in pulse-generating circuit 814, the reset terminal R of trigger DFF2～DFFm is connected; The output frequency signal f of frequency tunable ring oscillator 813
outWith the input end of clock CK of trigger DFF1～DFFm in pulse-generating circuit 814, be connected respectively; The data output end Q of trigger DFF1～DFFm-1 is connected with the data input pin D of the trigger DFF2～DFFm of next stage successively; The data output end Q of trigger DFFm is connected with the data input pin D of DFF1, and the while is as the output of pulse-generating circuit 814, and output rectangular pulse signal P
out.
Preferably, the output of frequency tunable ring oscillator 813 also is connected with for to output frequency signal f
outThe frequency output monitoring circuit 812 of being monitored.Frequency output monitoring circuit 812 adopts the X frequency dividing circuit, realizes frequency tunable ring oscillator 813 output frequency signal f
outFrequency reducing; Its input respectively with the output frequency signal f of frequency tunable ring oscillator 813
outWith enable signal, en is connected, output output frequency pilot signal f
mon.The level of enable signal en during also for control frequency output monitoring circuit 812 non operating state; Frequency monitoring signal f
monWith pulse-generating circuit 814, be connected for monitoring the width of pulse signal.
A kind of matrix pulse signal genration of the present invention method, comprise the steps:
A. setpoint frequency is adjusted signal c1～cj and is outputed to the input of frequency tunable ring oscillator 813;
B. given pulse produces control signal b
1Paired pulses produces circuit 814 and carries out set and reset operation, after completing, pulse is produced to control signal b
1Be set to high level;
C. to the enable signal en of the given permission of frequency tunable ring oscillator 813,813 starting of oscillations of frequency tunable ring oscillator produce the periodic output frequency signal f of frequency of oscillation
out, and output to pulse-generating circuit 814 from output; Frequency adjusted signal c1 by setting in the A step～cj, control output frequency signal f
outFrequency; Produce control signal b by the pulse in the B step
1Make to produce rectangular pulse signal P after pulse-generating circuit 814 operations
out.
Wherein, by adjusting in pulse-generating circuit 814 with the number of reset terminal trigger, can adjust rectangular pulse signal P
outDuty ratio.Frequency adjusted signal c1～cj adjusts signal a by original frequency
1～a
nOutput after frequency regulating circuit 811 conversions.Enable signal en and output frequency signal f
outFrequency division is connected to the input of frequency output monitoring circuit 812, by the pilot signal f of frequency output monitoring circuit 812 frequency reducing outputs
monRealization is to output frequency signal f
outMonitoring.
Below in conjunction with as shown in Figure 1, Figure 2 with the structure of the described preferred embodiment of Fig. 3, the present invention is further done and explains, carrying out circuit structure while selecting, according to rectangular pulse P
outThe width demand, determine the progression of alternative circuit, then determine the quantity of frequency adjusted signal c1～cj, finally determine that original frequency adjusts signal a
1～a
nNumber and the type of frequency regulating circuit 812, carrying out rectangular pulse while producing, carry out original frequency by demand and adjust signal a
1～a
nInput, in this preferred embodiment, wherein select j=2
n, therefore in order to narrate conveniently, and and the accompanying drawing correspondence, directly use 2
nReplace j to be narrated.
Original frequency is adjusted signal a
1～a
nWith frequency regulating circuit 811, be connected, enable signal en is connected with frequency output monitoring circuit 812, frequency tunable ring oscillator 813 respectively; 2 of frequency regulating circuit 811 outputs
nIndividual frequency adjusted signal c1～cj is connected with the input of frequency tunable ring oscillator 813; Pulse produces control signal b
1With the input of pulse-generating circuit 814, be connected; The output of frequency tunable ring oscillator 813 is connected with the input of pulse-generating circuit 814 with frequency output monitoring circuit 812 respectively; Frequency output monitoring circuit 812 output frequency pilot signal f
mon, pulse-generating circuit 814 rectangular pulse signal P
out
Frequency regulating circuit 811 adopts the n-2 of a standard
nDecoding circuit, the input of frequency regulating circuit 811 and original frequency are adjusted signal a
1～a
nBe connected, the output end signal of frequency regulating circuit 811 is c1～c2
n, output signal c1～c2
nWith the input of frequency tunable ring oscillator 814, be connected.The effect of frequency regulating circuit 811 is to convert n control signal to 2
nIndividual control signal, reduce control signal and draw number, realizes obtaining more pulse duration state by the least possible control signal.
Frequency output monitoring circuit 812 adopts an X frequency dividing circuit, the input of frequency output monitoring circuit 812 respectively with the output frequency signal f of frequency tunable ring oscillator 813
outWith enable signal, en is connected, frequency output monitoring circuit 812 output rate of connections pilot signal f
mon.The effect of frequency output monitoring circuit 812 is the output frequency signal f to frequency tunable ring oscillator 813
outCarry out frequency division, the mode by frequency reducing is indirectly to output frequency signal f
outRealize output, with frequency monitoring signal f
monRealization is to output frequency signal f
outMonitoring.
Frequency tunable ring oscillator 813 comprises k inverter, two input nand gates, 2
nindividual transmission gate, wherein, k is even number, the input of frequency tunable ring oscillator 813 respectively with the output frequency adjusted signal c1～c2 of frequency regulating circuit 811
nwith enable signal, en is connected, the output frequency signal f of frequency tunable ring oscillator 813
outwith the input of pulse-generating circuit 814, with the input of frequency output monitoring circuit 812, be connected respectively, output frequency signal f in frequency tunable ring oscillator 813
outthe input that connects the first inverter inv1, the output of the first inverter inv1 connects respectively input and the alternative circuit M1～M2 of the second inverter inv2
ninput a, the output of the second inverter inv2 connects the input of the 3rd inverter inv3, the output of the 3rd inverter inv3 connects the input b of alternative circuit M1, the selecting side s rate of connections of alternative circuit M1 is adjusted signal c1, the output y of alternative circuit M1 connects the input of the 4th inverter inv4, the output of the 4th inverter inv4 connects the input of the 5th inverter 5, the output of the 5th inverter inv5 connects the input b of alternative circuit M2, the selecting side s rate of connections of alternative circuit M2 is adjusted signal c2, the output y of alternative circuit M2 connects the input of hex inverter inv6, by that analogy, the output of q-3 inverter invq-3 connects alternative circuit M2
n-1 input b, alternative circuit M2
n-1 selecting side s rate of connections is adjusted signal c2
n-1, alternative circuit M2
n-1 output y connects the input of q-2 inverter invq-2, and the output of q-2 inverter invq-2 connects the input of q-1 inverter invq-1, and the output of q-1 inverter invq-1 connects alternative circuit M2
ninput b, alternative circuit M2
nselecting side s rate of connections adjust signal c2
n, alternative circuit M2
noutput y connect the input of q inverter invq, pass through again several grades of inverter cascades, the output of k-1 inverter invk-1 connects the input of k inverter invk, the output of k inverter invk connects the first input end of two input nand gates, and the second input of two input nand gates is connected with X frequency dividing circuit input a with enable signal en respectively, the output signal of two input nand gates, namely output frequency signal f
outwith the input of the first inverter inv1 and the input b of X frequency dividing circuit, be connected respectively.Frequency tunable ring oscillator 813 is cores that whole nanosecond rectangular pulse width adjustable signal produces circuit, and its function is to produce periodic output frequency signal f
out, and realize frequency f by the progression that changes ring oscillator alternative circuit
outAdjustment, and then realize rectangular pulse P
outThe adjustment of width.
The living circuit 814 that pulse is produced as required comprises a trigger with the set end and m-1 the trigger with reset terminal; Pulse produces control signal b
1With the set end S end of trigger DFF1 in pulse-generating circuit 814, and in pulse-generating circuit 814, the reset terminal R end of trigger DFF2～DFFm is connected; The output frequency signal f of frequency tunable ring oscillator 813
outWith the input end of clock CK of trigger DFF1～DFFm in pulse-generating circuit 814, be connected; The data input pin D of trigger DFF1 is connected with the data output end Q of DFFm, the data output end Q of DFF1 is connected with the data input pin D of DFF2, the data output end Q of DFF2 is connected with the data input pin D of DFF3, by that analogy, the data output end Q of DFFm-1 is connected with the data input pin D of DFFm, and the data output end Q of DFFm is connected with the data input pin D of DFF1, and the while is as the output rectangular pulse signal P of pulse-generating circuit
out.The function of pulse-generating circuit 814 is to utilize pulse signal of shift register chain structure generation, simultaneously, by arrange with set end trigger with the number of reset terminal trigger, can adjust the duty ratio of pulse signal, to obtain suitable pulse signal, increased the adaptability of rectangular pulse signal.Whole circuit is totally digital circuit, fully compatible with digital CMOS process, and pulse duration is adjustable, can monitor, and circuit structure is simple, applying flexible is convenient, suitable application area is extensive.
When this pulse duration adjustable signal produces circuit working, at first setpoint frequency is adjusted signal a
1～a
nValue, obtain suitable oscillator frequency output frequency signal f
outThen utilize pulse to produce control signal b
1Trigger DFF1～DFFm that paired pulses produces circuit 814 carries out set, reset operation, completes after set, reset operation signal b
1Be set to high level; Finally, enable signal en is effective, and frequency tunable ring oscillator 813 starts starting of oscillation and produces rectangular pulse signal P by pulse-generating circuit 814
out, simultaneously by frequency monitoring signal f
monThe frequency of oscillation of monitoring frequency tunable ring oscillator 813, namely frequency output signal f
out.When the X frequency dividing circuit is selected four frequency divisions, when the progression m of trigger selects 6 grades, the enable signal en produced, pulse produce control signal b
1, and the work wave schematic diagram of output signal as shown in Figure 1.
Above content is in conjunction with concrete preferred implementation further description made for the present invention; can not assert that the specific embodiment of the present invention only limits to this; technical staff for digital integrated circuit nanosecond pulse signal generating circuit under the present invention; under the prerequisite that does not break away from thinking of the present invention; can also design some pulse signal generating circuits, all should be considered as belonging to the definite scope of patent protection of claims that the present invention submits to.
Claims (10)
1. a matrix pulse signal generating circuit, is characterized in that, comprises frequency tunable ring oscillator (813) and pulse-generating circuit (814); The input of frequency tunable ring oscillator (813) is connected with enable signal (en), and with frequency adjusted signal c1～cj, is connected respectively; Frequency tunable ring oscillator (813) output is exported periodic output frequency signal (f
out), and be connected with the input of pulse-generating circuit (814); The input of pulse-generating circuit (814) also produces control signal (b with pulse
1) be connected, the output output rectangular pulse signal (P of pulse-generating circuit (814)
out);
Described frequency tunable ring oscillator (813) comprises k inverter, two input nand gates and j alternative circuit, and wherein, k is even number; The output of the first inverter (inv1) connects respectively the input of the second inverter (inv2) and the input a of alternative circuit M1～Mj, and the corresponding rate of connections of the selecting side s of alternative circuit M1～Mj is adjusted signal c1～cj; The output of the second inverter (inv2) connects the input of the 3rd inverter (inv3), the output of the 3rd inverter (inv3) connects the input b of alternative circuit M1, the output y of alternative circuit M1～Mj-1 is connected with the input b of the alternative circuit M2～Mj of next stage by the inverter of two cascades successively, the output y of alternative circuit Mj connects the input of q inverter (invq), the output cascade k-q level inverter of q inverter (invq); The output of k inverter (invk) is connected with the first input end of two input nand gates, the second input of two input nand gates is connected with enable signal (en), the output of two input nand gates is connected with the input of the first inverter (inv1), simultaneously as the output of frequency tunable ring oscillator (813), and export periodic output frequency signal (f
out).
2. a kind of matrix pulse signal generating circuit according to claim 1, is characterized in that, described pulse-generating circuit (814) comprises the trigger of a band set end (S) and the trigger of m-1 band reset terminal (R); Pulse produces control signal (b
1) respectively with pulse-generating circuit (814) in the set end (S) of trigger DFF1, and in pulse-generating circuit (814), the reset terminal (R) of trigger DFF2～DFFm is connected; Output frequency signal (the f of frequency tunable ring oscillator (813)
out) with the input end of clock (CK) of trigger DFF1～DFFm in pulse-generating circuit (814), be connected respectively;
The data output end of trigger DFF1～DFFm-1 (Q) is connected with the data input pin (D) of the trigger DFF2～DFFm of next stage successively; The data output end of trigger DFFm (Q) is connected with the data input pin (D) of DFF1, and the while is as the output of pulse-generating circuit (814), and output rectangular pulse signal (P
out).
3. a kind of matrix pulse signal generating circuit according to claim 1 and 2, is characterized in that, also comprises for original frequency being adjusted to signal a
1～a
nChange and be output as the frequency regulating circuit (811) of frequency adjusted signal c1～cj.
4. a kind of matrix pulse signal generating circuit according to claim 3, is characterized in that, described frequency regulating circuit (811) adopts the n-2 of standard
nDecoding circuit; The input of frequency regulating circuit (811) and original frequency are adjusted signal a
1～a
nBe connected, the output output frequency is adjusted signal c1～cj, wherein, and j=2
n.
5. a kind of matrix pulse signal generating circuit according to claim 1 and 2, is characterized in that, the output of described frequency tunable ring oscillator (813) also is connected with for to output frequency signal (f
out) the frequency output monitoring circuit (812) monitored.
6. a kind of matrix pulse signal generating circuit according to claim 5, is characterized in that, described frequency output monitoring circuit (812) adopts the X frequency dividing circuit, its input respectively with the output frequency signal (f of frequency tunable ring oscillator (813)
out) with enable signal (en), be connected, output output frequency pilot signal (f
mon).
7. a matrix pulse signal genration method, is characterized in that, it is based on the described matrix pulse signal generating circuit of any one in claim 1-6, and comprise the steps:
A. setpoint frequency is adjusted signal c1～cj and is outputed to the input of frequency tunable ring oscillator (813);
B. given pulse produces control signal (b
1) paired pulses produces circuit (814) and carry out set and reset operation, after completing, pulse produced to control signal (b
1) be set to high level;
C. to the enable signal (en) of the given permission of frequency tunable ring oscillator (813), frequency tunable ring oscillator (813) starting of oscillation produces the periodic output frequency signal (f of frequency of oscillation
out), and output to pulse-generating circuit (814) from output; Frequency adjusted signal c1 by setting in the A step～cj, control output frequency signal (f
out) frequency; Produce control signal (b by the pulse in the B step
1) make to produce rectangular pulse signal (P after pulse-generating circuit (814) operation
out).
8. a kind of matrix pulse signal genration method according to claim 7, is characterized in that, by adjusting in pulse-generating circuit (814) with the number of reset terminal trigger, can adjust rectangular pulse signal (P
out) duty ratio.
9. a kind of matrix pulse signal genration method according to claim 7, is characterized in that, described frequency adjusted signal c1～cj adjusts signal a by original frequency
1～a
nOutput after frequency regulating circuit (811) conversion.
10. a kind of matrix pulse signal genration method according to claim 7, is characterized in that described enable signal (en) and output frequency signal (f
out) frequency division is connected to the input of frequency output monitoring circuit (812), by the pilot signal (f of frequency output monitoring circuit (812) frequency reducing output
mon) realize output frequency signal (f
out) monitoring.
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| CN201310349521.3A CN103427795B (en) | 2013-08-12 | 2013-08-12 | A kind of rectangular pulse signal generating circuit and production method |
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|---|---|---|---|
| CN201310349521.3A CN103427795B (en) | 2013-08-12 | 2013-08-12 | A kind of rectangular pulse signal generating circuit and production method |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103902930A (en) * | 2014-03-10 | 2014-07-02 | 杭州晟元芯片技术有限公司 | Physical unclonable function circuit structure based on ring oscillators |
| CN104901655A (en) * | 2015-06-16 | 2015-09-09 | 成都宜川电子科技有限公司 | Signal generator |
| CN107636967A (en) * | 2015-05-20 | 2018-01-26 | 思睿逻辑国际半导体有限公司 | Ring divider |
| CN109167571A (en) * | 2018-08-13 | 2019-01-08 | 中科芯集成电路股份有限公司 | A kind of low-power consumption ring oscillator and its implementation |
| CN110851331A (en) * | 2019-11-13 | 2020-02-28 | 中国电子科技集团公司第五十八研究所 | On-chip monitoring circuit of antifuse Field Programmable Gate Array (FPGA) |
| CN114679158A (en) * | 2022-05-30 | 2022-06-28 | 石家庄市鹿泉区精诚通信科技有限公司 | Periodic signal generating device, signal processing system and periodic signal generating method thereof |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5671179A (en) * | 1994-10-19 | 1997-09-23 | Intel Corporation | Low power pulse generator for smart voltage flash eeprom |
| CN1459683A (en) * | 2002-05-24 | 2003-12-03 | 三星电子株式会社 | Circuit and method for producing internal clock signal |
| CN101521498A (en) * | 2008-02-29 | 2009-09-02 | 北京芯慧同用微电子技术有限责任公司 | Voltage controlled oscillator |
| CN202309679U (en) * | 2011-11-18 | 2012-07-04 | 深圳市梓晶微科技有限公司 | Integrated circuit with built-in oscillation frequency controller |
| CN102890529A (en) * | 2011-07-21 | 2013-01-23 | 英赛瑟库尔公司 | Clock frequency adjusting method and circuit |
| US8401600B1 (en) * | 2010-08-02 | 2013-03-19 | Hypres, Inc. | Superconducting multi-bit digital mixer |
-
2013
- 2013-08-12 CN CN201310349521.3A patent/CN103427795B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5671179A (en) * | 1994-10-19 | 1997-09-23 | Intel Corporation | Low power pulse generator for smart voltage flash eeprom |
| CN1459683A (en) * | 2002-05-24 | 2003-12-03 | 三星电子株式会社 | Circuit and method for producing internal clock signal |
| CN101521498A (en) * | 2008-02-29 | 2009-09-02 | 北京芯慧同用微电子技术有限责任公司 | Voltage controlled oscillator |
| US8401600B1 (en) * | 2010-08-02 | 2013-03-19 | Hypres, Inc. | Superconducting multi-bit digital mixer |
| CN102890529A (en) * | 2011-07-21 | 2013-01-23 | 英赛瑟库尔公司 | Clock frequency adjusting method and circuit |
| CN202309679U (en) * | 2011-11-18 | 2012-07-04 | 深圳市梓晶微科技有限公司 | Integrated circuit with built-in oscillation frequency controller |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103902930A (en) * | 2014-03-10 | 2014-07-02 | 杭州晟元芯片技术有限公司 | Physical unclonable function circuit structure based on ring oscillators |
| CN103902930B (en) * | 2014-03-10 | 2016-09-07 | 杭州晟元数据安全技术股份有限公司 | The unclonable functional circuit structure of physics based on ring oscillator |
| CN107636967A (en) * | 2015-05-20 | 2018-01-26 | 思睿逻辑国际半导体有限公司 | Ring divider |
| CN104901655A (en) * | 2015-06-16 | 2015-09-09 | 成都宜川电子科技有限公司 | Signal generator |
| CN109167571A (en) * | 2018-08-13 | 2019-01-08 | 中科芯集成电路股份有限公司 | A kind of low-power consumption ring oscillator and its implementation |
| CN110851331A (en) * | 2019-11-13 | 2020-02-28 | 中国电子科技集团公司第五十八研究所 | On-chip monitoring circuit of antifuse Field Programmable Gate Array (FPGA) |
| CN114679158A (en) * | 2022-05-30 | 2022-06-28 | 石家庄市鹿泉区精诚通信科技有限公司 | Periodic signal generating device, signal processing system and periodic signal generating method thereof |
| CN114679158B (en) * | 2022-05-30 | 2022-08-05 | 石家庄市鹿泉区精诚通信科技有限公司 | Periodic signal generating device, signal processing system and periodic signal generating method thereof |
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