CN103441081B - semiconductor composite structure and semiconductor process - Google Patents
semiconductor composite structure and semiconductor process Download PDFInfo
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- CN103441081B CN103441081B CN201310399828.4A CN201310399828A CN103441081B CN 103441081 B CN103441081 B CN 103441081B CN 201310399828 A CN201310399828 A CN 201310399828A CN 103441081 B CN103441081 B CN 103441081B
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- contact
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 44
- 238000000034 method Methods 0.000 title abstract description 3
- 239000002131 composite material Substances 0.000 title 1
- 239000004020 conductor Substances 0.000 claims abstract description 78
- 239000000758 substrate Substances 0.000 claims abstract description 67
- 229910052751 metal Inorganic materials 0.000 claims description 78
- 239000002184 metal Substances 0.000 claims description 78
- 239000000463 material Substances 0.000 claims description 61
- 239000010410 layer Substances 0.000 claims description 53
- 239000011241 protective layer Substances 0.000 claims description 21
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 16
- 238000005516 engineering process Methods 0.000 claims description 13
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 12
- 229910052737 gold Inorganic materials 0.000 claims description 12
- 239000010931 gold Substances 0.000 claims description 12
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 11
- 229910052802 copper Inorganic materials 0.000 claims description 11
- 239000010949 copper Substances 0.000 claims description 11
- 229910001096 P alloy Inorganic materials 0.000 claims description 9
- 229910000756 V alloy Inorganic materials 0.000 claims description 9
- HBVFXTAPOLSOPB-UHFFFAOYSA-N nickel vanadium Chemical compound [V].[Ni] HBVFXTAPOLSOPB-UHFFFAOYSA-N 0.000 claims description 9
- OFNHPGDEEMZPFG-UHFFFAOYSA-N phosphanylidynenickel Chemical compound [P].[Ni] OFNHPGDEEMZPFG-UHFFFAOYSA-N 0.000 claims description 9
- 239000000853 adhesive Substances 0.000 claims description 8
- 230000001070 adhesive effect Effects 0.000 claims description 8
- 229910052759 nickel Inorganic materials 0.000 claims description 8
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 claims description 4
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical group [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 4
- 229910052804 chromium Inorganic materials 0.000 claims description 4
- 239000011651 chromium Substances 0.000 claims description 4
- 239000010936 titanium Substances 0.000 claims description 4
- 229910052719 titanium Inorganic materials 0.000 claims description 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 4
- 229910052721 tungsten Inorganic materials 0.000 claims description 4
- 239000010937 tungsten Substances 0.000 claims description 4
- 239000003292 glue Substances 0.000 claims description 3
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 claims 2
- 239000003566 sealing material Substances 0.000 claims 2
- 229910052725 zinc Inorganic materials 0.000 claims 2
- 239000011701 zinc Substances 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 8
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 4
- 239000004642 Polyimide Substances 0.000 description 4
- 229920001721 polyimide Polymers 0.000 description 4
- 239000004593 Epoxy Substances 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- -1 PI) Polymers 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 2
- 229910017052 cobalt Inorganic materials 0.000 description 2
- 239000010941 cobalt Substances 0.000 description 2
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910052763 palladium Inorganic materials 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Abstract
The invention relates to a semiconductor combination structure and a semiconductor process. The semiconductor assembly structure comprises a substrate, at least one conductor, a baffle wall part and a first chip. The substrate has at least one electrical connection point. The conductor is located on the electrical connection position. The retaining wall is used for supporting the conductor. The first chip has at least one bump. The first chip is approximately vertical to the substrate, and the bump contacts the conductor. Therefore, the joint reliability between the bump and the conductor can be improved, so as to ensure the electrical connection between the first chip and the substrate.
Description
Technical field
The invention relates to a kind of semiconductor combinations structure and semiconductor technology. In detail, the invention relates toA kind of semiconductor combinations structure and semiconductor technology that comprises rectilinear joint chip.
Background technology
Known packets is by a rectilinear core containing the manufacture method of the semiconductor combinations structure of rectilinear joint chipChip bonding to one substrate, a wherein first surface of vertical this substrate of the first surface of this rectilinear chip, andThe first surface of this rectilinear chip has chip connecting pad, and a first surface of this substrate has substrate connecting pad.Vertical this substrate connecting pad of this chip connecting pad, and the two is very close. Then, utilize a scolder to contact this simultaneouslyChip connecting pad and this substrate connecting pad, to be electrically connected this chip connecting pad and this substrate connecting pad. The shortcoming of this modeFor reliability is low because the position of this chip connecting pad must be very near the lower edge of this rectilinear chip, abilityMake this scolder touch this chip connecting pad and this substrate connecting pad simultaneously. In addition, this chip connecting pad is vertical direction,When this scolder is can flow regime during at high temperature, it is not easy to be attached in this chip connecting pad. On improvingState problem, a solution is suggested.
Summary of the invention
The one side of this exposure is about a kind of semiconductor combinations structure. In one embodiment, this semiconductor groupClose structure and comprise a substrate, at least one conductor, a barricade portion and one first chip. This substrate has table onFace and at least one electric connection place, this electric connection place is positioned on this upper surface. This conductor is positioned at this and electrically connectsConnect in place. This barricade portion is adjacent to this substrate, and in order to this conductor of contact. This first chip has one firstSurperficial and at least one projection, this projection is positioned at this first surface of this first chip, this of this first chipThis upper surface of one substantially vertical this substrate in surface, this conductor of this bump contact, and the material of this projection and thisThe material difference of conductor.
Therefore, engaging reliability and can improve between this projection and this conductor, and guarantee that this projection and this electrically connectConnect the electric connection between place, guarantee the electric connection between this first chip and this substrate simultaneously.
This exposure be about a kind of semiconductor combinations structure on the other hand. In one embodiment, this semiconductorCombining structure comprises a substrate, at least one conductor, a barricade portion and one first chip. This substrate has on oneSurperficial and at least one electric connection place. This conductor is positioned in this electric connection place. This barricade portion is adjacent to this basePlate, and in order to this conductor of contact. This first chip have a first surface, at least one projection, a protective layer,One connection pad and a ball lower metal layer. One surface of this protective layer is this first surface, and this protective layer has outMouth is to appear this connection pad of part, and this ball lower metal layer is arranged on this protective layer and opening connects to contact thisPad, the material of this connection pad is gold, this projection is positioned on this ball lower metal layer, this first table of this first chipThis upper surface of substantially vertical this substrate of face, this conductor of this bump contact.
This exposure be about a kind of semiconductor technology on the other hand. In one embodiment, this semiconductor technologyComprise the following steps: a substrate (a) is provided, and this substrate has a upper surface and at least one electric connection place; (b)Form at least one conductor in this electric connection place; (c) forming a barricade portion is adjacent to this substrate this is led with contactBody; (d) provide one first chip, this first chip has a first surface and at least one projection, this projection positionIn this first surface of this first chip, and the material of this projection is different with the material of this conductor; (e) engaging shouldThe first chip is to this substrate, wherein, and table on this of substantially vertical this substrate of this first surface of this first chipFace, this conductor of this bump contact; And (f) heat, make this projection fusing cave in and be attached to this conductorOn.
Brief description of the drawings
Fig. 1 shows the cross-sectional schematic of an embodiment of semiconductor combinations structure of the present invention. .
Fig. 2 shows the signal of overlooking of this conductor and this first electric connection place in the semiconductor combinations structure of Fig. 1Figure.
Fig. 3 shows the enlarged diagram of region A in Fig. 1.
Fig. 4 shows the local enlarged diagram of this first chip and this projection in Fig. 1.
Fig. 5 to Figure 14 shows the schematic diagram of an embodiment of semiconductor technology of the present invention.
Detailed description of the invention
With reference to figure 1, show the cross-sectional schematic of an embodiment of semiconductor combinations structure of the present invention. This is partly ledBody combining structure 1 comprises a substrate 10, at least one conductor 12, a barricade portion 14, one first chip 16,Primer (Underfill) 18, one second chip 20, at least one the 3rd chip 24, several bars of the first wires 22,Several the second wires 26 and an adhesive material 28.
This substrate 10 has a upper surface 101, a lower surface 102, one first electric connection place 103 and oneTwo electric connections place 104, wherein, relative this lower surface 102 of this upper surface 101, and this first electric connectionPlace 103 and this second electric connection place 104 are positioned on this upper surface 101. In the present embodiment, this first electricityProperty junction 103 and this second electric connection place 104 are conductive finger (Finger).
This conductor 12 is positioned in this first electric connection place 103. This conductor 12 is conductive material, for example:Gold or copper.
This barricade portion 14 is adjacent to this substrate 10, and in order to this conductor 12 of contact. In the present embodiment, this gearWall portion 14 is positioned in this electric connection place 103, and more covers this upper surface 101 of this substrate 10. This barricade portion14 material is non-conductive glue material, for example: polyimides (Polyimide, PI), epoxy resin (Epoxy)Or benzyl ring butylene (Benzocyclobutene, BCB).
This first chip 16 has a first surface 161, a second surface 162, one the 3rd surface 163 and extremelyA few projection 17. Relative this second surface 162 of this first surface 161, and the 3rd surface 163 in abutting connection with thisOne surface 161 and this second surface 162. This first surface 161 of this first chip 16 is substantially vertical these basesThis upper surface 101 of plate 10, and the 3rd surface 163 of this first chip 16 is these substrates 10 of almost parallelThis upper surface 101. That is this first chip 16 is a rectilinear joint chip.
This projection 17 is positioned at this first surface 161 of this first chip 16, and its number and position are to leadingBody 12, makes this projection 17 these conductors 12 of contact. In the present embodiment, the number of this conductor 12 is 6,It lays respectively in 6 the first electric connections place 103, and therefore, this first chip 16 has 6 projections 17,Wherein each projection 17 each conductor 12 of contact. The material of this projection 17 is different from the material of this conductor 12. ?In the present embodiment, the material of this projection 17 is tin. Be noted that the not ball of this projection 17 in Fig. 1Body, because it has lived through heating steps, and fusing is caved in and is attached on this conductor 12.
Coated this projection 17 of this primer 18. In the present embodiment, the 3rd surface 163 of this first chip 16Have a gap with this upper surface 101 of this substrate 10, make this primer 18 can from this first chip 16 shouldSecond surface 162 is coated this projection 17 through this gap to this first surface 161 of this first chip 16. AndThis primer 18 is different with the material of this barricade portion 14, illustrates further, and the coefficient of viscosity of this barricade portion 14 is largeIn the coefficient of viscosity of this primer 18. This second chip 20 is attached to this substrate 10 and is electrically connected to this substrate10, in the present embodiment, this second chip 20 utilizes a mucigel 21 to be adhered to this upper surface of this substrate 10On 101, and utilize these first wires 22 to be electrically connected to the second electric connection place 104 on this substrate 10.
The 3rd chip 24 is attached to this second chip 20 and is electrically connected to this second chip 20. In this enforcementIn example, the 3rd chip 24 utilizes a mucigel 25 to be adhered on this second chip 20, and utilize these secondWire 26 is electrically connected to this second chip 20. Preferably, this second chip 20 is Application Specific Integrated Circuit(ApplicationSpecificIntegratedCircuit, ASIC) chip, and the 3rd chip 24 is sensingDevice (Sensor).
This adhesive material 28 is positioned at this upper surface 101 of this substrate 10, and is coated this first chip 16, this endGlue 18, this second chip 20, the 3rd chip 24, these first wires 22 and these the second wires 26. EnterOne step explanation, this adhesive material 28 directly contacts with this barricade portion 14 and this primer 18.
With reference to figure 2, in the semiconductor combinations structure of demonstration Fig. 1, this conductor and this first electric connection place overlooksSchematic diagram. In the present embodiment, the length L of this first electric connection place 103 is 60 μ m, and width W is 30μ m. The Breadth Maximum D of this conductor 12 is 20 μ m.
With reference to figure 3, show the enlarged diagram of region A in Fig. 1. In the present embodiment, this conductor 12 is ballShape or column, it has a maximum height H, and this maximum height H is 15 to 30 μ m. This barricade portion 14 and thisConductor 12 contacts and forms a contact-making surface 121, and the peak 1211 of this contact-making surface 121 is own lower than this conductor 12Peak 123. That is the peak 123 of this conductor 12 can not covered in this barricade portion 14. Therefore, this gearThe thickness T of wall portion 14 is less than this maximum height H of this conductor 12, and this contact-making surface 121 is less than outside this conductor 12The half on surface. By this, this barricade portion 14 just can not affect being connected between this projection 17 and this conductor 12. ?Good ground, the thickness T of this barricade portion 14 be about this conductor 12 this maximum height H 1/3 to 2/3.
This projection 17 contacts with this conductor 12 not covered by this barricade portion 14 and forms a contact-making surface 122, shouldContact-making surface 122 can extend beyond the peak 123 of this conductor 12. That is this contact-making surface 122 is greater than this conductor 12Outer surface over half. This barricade portion 14 has a barrier effect, can avoid projection 17 to live through heating stepAfter rapid, all fusing cave in be attached on this conductor 12 and overflow to substrate 10, make projection 17 depart from the first coreSheet 16, causes electrical property efficiency not good. Therefore, engaging reliability and can improve between this projection 17 and this conductor 12,And guarantee the electric connection between this projection 17 and this first electric connection place 103, guarantee this first chip simultaneously16 and this substrate 10 between electric connection.
With reference to figure 4, the local enlarged diagram of this first chip 16 and this projection 17 in demonstration Fig. 1. In this realityExecute in example, this first chip 16 has more a protective layer 164, a connection pad 165 and a ball lower metal layer (UBM)166. The material of this connection pad 165 is gold. The surface of this protective layer 164 be this first chip 16 this firstSurface 161. This protective layer 164 has an opening 1641 to appear this connection pad 165 of part. This ball lower metal layer(UBM) 166 be arranged on this protective layer 164 and opening 1641 to contact this connection pad 165. This projection 17Be positioned on this ball lower metal layer (UBM) 166.
This ball lower metal layer (UBM) 166 sequentially comprises a first metal layer 1661, one second metal level 1662And one the 3rd metal level 1663. These the first metal layer 1661 these connection pads 165 of contact, and this projection 17 is positioned at thisOn the 3rd metal level 1663. In the present embodiment, the material of this first metal layer 1661 be titanium, chromium, tungsten orZinc, the material of this second metal level 1662 is nickel, nickel-vanadium alloy or nickel-phosphorus alloy, and the 3rd metal level 1663Material be copper. In another embodiment, the material of this first metal layer 1661 is palladium or cobalt, this second gold medalThe material that belongs to layer 1662 is nickel, nickel-vanadium alloy or nickel-phosphorus alloy, and the material of the 3rd metal level 1663 is copper.In another embodiment, this ball lower metal layer (UBM) 166 sequentially comprises a first metal layer and one secondMetal level, this first metal layer contacts this connection pad 165, and this projection 17 is positioned on this second metal level. ShouldThe material of the first metal layer is nickel, nickel-vanadium alloy or nickel-phosphorus alloy, and the material of this second metal level is copper.The material of above-mentioned this ball lower metal layer (UBM) 166 can be strengthened this projection 17 and this ball lower metal layer (UBM)166 adhesion, even if for example make, through repeatedly reflow (more than 10 times), this projection 17 still can be firmBe engaged on this ball lower metal layer (UBM) 166.
To Figure 14, show the schematic diagram of an embodiment of semiconductor technology of the present invention with reference to figure 5. With reference to figure 5,One substrate 10 is provided. This substrate 10 has a upper surface 101, a lower surface 102, one first electric connection place103 and one second electric connection place 104, wherein, relative this lower surface 102 of this upper surface 101, and this firstElectric connection place 103 and this second electric connection place 104 are positioned on this upper surface 101. In the present embodiment,This first electric connection place 103 and this second electric connection place 104 are conductive finger (Finger).
Then, form at least one conductor 12 in this first electric connection place 103. This conductor 12 is for conducting electricityMaterial, for example: gold or copper.
With reference to figure 6, form a barricade portion 14 and be adjacent to this substrate 10 with this conductor 12 of contact. At the present embodimentIn, this barricade portion 14 is positioned in this electric connection place 103, and more covers this upper surface 101 of this substrate 10.The material of this barricade portion 14 is non-conductive glue material, for example: polyimides (Polyimide, PI), epoxy treeFat (Epoxy) or benzyl ring butylene (Benzocyclobutene, BCB), and it is necessary for high viscosity.This barricade portion 14 contacts with this conductor 12 and forms a contact-making surface 121, the peak 1211 of this contact-making surface 121Lower than the peak 123 of this conductor 12 own. That is the highest of this conductor 12 can not covered in this barricade portion 14Point 123. Therefore, the thickness T of this barricade portion 14 is less than this maximum height H of this conductor 12, and this contact-making surface121 are less than the half of these conductor 12 outer surfaces. By this, this barricade portion 14 just can not affect follow-up electrically connectingConnect. Preferably, the thickness T of this barricade portion 14 be about this conductor 12 this maximum height H 1/3 to 2/3. Connect, solidify this barricade portion 14.
With reference to figure 7, provide one first chip 16. This first chip 16 has a first surface 161, one secondSurface 162, one the 3rd surface 163 and at least one projection 17. Relative this second surface 162 of this first surface 161,And the 3rd surface 163 is in abutting connection with this first surface 161 and this second surface 162. This projection 17 be positioned at this firstThis first surface 161 of chip 16, and its number and position are to should conductor 12. The bottom of this projection 17 withThe distance d on the 3rd 163, surface is substantially equal to the maximum of thickness and this conductor 12 of this electric connection place 103Height H sum.
With reference to figure 8, the local enlarged diagram of this first chip and this projection in demonstration Fig. 7. At the present embodimentIn, this first chip 16 has more a protective layer 164, a connection pad 165 and a ball lower metal layer (UBM)166. The material of this projection 17 is different from the material of this conductor 12. In the present embodiment, the material of this projection 17Matter is tin. Be noted that this projection 17 in this figure is a spheroid. The material of this connection pad 165 is gold.The surface of this protective layer 164 is this first surface 161 of this first chip 16. This protective layer 164 has oneOpening 1641 is to appear this connection pad 165 of part. This ball lower metal layer (UBM) 166 is positioned at this protective layer 164In upper and opening 1641 to contact this connection pad 165. This projection 17 is positioned at this ball lower metal layer (UBM) 166On.
This ball lower metal layer (UBM) 166 sequentially comprises a first metal layer 1661, one second metal level 1662And one the 3rd metal level 1663. These the first metal layer 1661 these connection pads 165 of contact, and this projection 17 is positioned at thisOn the 3rd metal level 1663. In the present embodiment, the material of this first metal layer 1661 be titanium, chromium, tungsten orZinc, the material of this second metal level 1662 is nickel, nickel-vanadium alloy or nickel-phosphorus alloy, and the 3rd metal level 1663Material be copper. In another embodiment, the material of this first metal layer 1661 is palladium or cobalt, this second gold medalThe material that belongs to layer 1662 is nickel, nickel-vanadium alloy or nickel-phosphorus alloy, and the material of the 3rd metal level 1663 is copper.In another embodiment, this ball lower metal layer (UBM) 166 sequentially comprises a first metal layer and one secondMetal level, this first metal layer contacts this connection pad 165, and this projection 17 is positioned on this second metal level. ShouldThe material of the first metal layer is nickel, nickel-vanadium alloy or nickel-phosphorus alloy, and the material of this second metal level is copper.The material of above-mentioned this ball lower metal layer (UBM) 166 can be strengthened this projection 17 and this ball lower metal layer (UBM)166 adhesion, even if for example make, through repeatedly reflow (more than 10 times), this projection 17 still can be firmBe engaged on this ball lower metal layer (UBM) 166.
With reference to figure 9, engage this first chip 16 to this substrate 10. This first surface 161 of this first chip 16This upper surface 101 of substantially vertical this substrate 10, and the 3rd surperficial 163 almost parallels of this first chip 16This upper surface 101 of this substrate 10. That is this first chip 16 is a rectilinear joint chip. Now,This projection 17 these conductors 12 of contact, its two be some contact. In the present embodiment, being somebody's turn to do of this first chip 16There is a gap on the 3rd surface 163 with this upper surface 101 of this substrate 10.
With reference to Figure 10, carry out reflow heating, make these projection 17 fusings cave in and be attached to not by this barricade portionOn 14 these conductors 12 that cover. This projection 17 contacts with this conductor 12 and forms a contact-making surface 122(Fig. 3),This contact-making surface 122 can extend beyond the peak 123 of this conductor 12. That is this contact-making surface 122 is greater than this leadsBody 12 outer surfaces over half. Therefore, engaging reliability and can improve between this projection 17 and this conductor 12,And guarantee the electric connection between this projection 17 and this first electric connection place 103, guarantee this first chip simultaneously16 and this substrate 10 between electric connection.
Then, form a primer 18 to be coated this projection 17. In the present embodiment, this primer 18 can be from thisThis second surface 162 of the first chip 16 through this gap to this first surface 161 of this first chip 16 andCoated this projection 17. Then, solidify this primer 18.
With reference to Figure 11, adhere to one second chip 20 to this substrate 10. In the present embodiment, be first to form one to stickGlue-line 21, on this upper surface 101 of this substrate 10, then, is put this second chip 20 in this mucigel 21On. Afterwards, dry this mucigel 21. In the present embodiment, this second chip 20 is the long-pending body electricity of special applicationsRoad (ApplicationSpecificIntegratedCircuit, ASIC) chip.
With reference to Figure 12, adhere at least one the 3rd chip 24 to this second chip 20. In the present embodiment, be firstForming a mucigel 25 attaches on this second chip 20. Then, put the 3rd chip 24 in this mucigelOn 25. Afterwards, dry this mucigel 25. In the present embodiment, the 3rd chip 24 is sensor (Sensor).
With reference to Figure 13, be electrically connected this second chip 20 to this substrate 10, and be electrically connected the 3rd chip 24To this second chip 20. In the present embodiment, utilize several the first wires 22 to be electrically connected this second chip20 to the second electric connection place 104 on this substrate 10, and utilize several the second wires 26 to be electrically connected shouldThe 3rd chip 24 is to this second chip 20.
With reference to Figure 14, form an adhesive material 28 in this upper surface 101 of this substrate 10 to be coated this first coreSheet 16, this primer 18, this second chip 20, the 3rd chip 24, these first wires 22 and these secondWire 26. Then, solidify this adhesive material 28. Then, carry out cutting step, to form several semiconductorsCombining structure 1.
Only above-described embodiment is only explanation principle of the present invention and effect thereof, but not in order to limit the present invention. CauseThis, practise in the personage of this technology and above-described embodiment modified and change still not de-spirit of the present invention. ThisThe interest field of invention should be as listed in claims.
Claims (20)
1. a semiconductor combinations structure, comprising:
One substrate, has a upper surface and at least one electric connection place, and this electric connection place is positioned on this upper surface;
At least one conductor, is positioned in this electric connection place;
One barricade portion, is adjacent to this substrate, and in order to this conductor of contact; And
One first chip, has a first surface and at least one projection, this projection be positioned at this first chip thisOne surface, this upper surface that this first surface of this first chip is substantially vertical this substrate, this leads this bump contactBody, and the material of this projection is different with the material of this conductor.
2. semiconductor combinations structure as claimed in claim 1, is characterized in that, this electric connection place is conductive finger,And this barricade portion is positioned in this electric connection place.
3. semiconductor combinations structure as claimed in claim 1, is characterized in that, the material of this barricade portion is non-conductiveGlue material.
4. semiconductor combinations structure as claimed in claim 1, is characterized in that, this barricade portion and this conductor contact andForm a contact-making surface, the peak of this contact-making surface is lower than the peak of this conductor itself.
5. semiconductor combinations structure as claimed in claim 1, is characterized in that, this first chip has more a protectionLayer, a connection pad and a ball lower metal layer, this protective layer has an opening to appear this connection pad of part, metal under this ballLayer be arranged on this protective layer and opening to contact this connection pad, this projection is positioned on this ball lower metal layer, wherein shouldThe material of connection pad is gold.
6. semiconductor combinations structure as claimed in claim 5, is characterized in that, this ball lower metal layer sequentially comprises oneThe first metal layer, one second metal level and one the 3rd metal level, this first metal layer contacts this connection pad, this first gold medalThe material that belongs to layer is titanium, chromium, tungsten or zinc, and the material of this second metal level is nickel, nickel-vanadium alloy or nickel-phosphorus alloy,And the material of the 3rd metal level is copper.
7. semiconductor combinations structure as claimed in claim 1, is characterized in that, more comprises a primer and a sealingMaterial, this primer is coated this projection, this adhesive material be positioned at this upper surface of this substrate and coated this first chip,This primer and this barricade portion.
8. a semiconductor combinations structure, comprising:
One substrate, has a upper surface and at least one electric connection place;
At least one conductor, is positioned in this electric connection place;
One barricade portion, is adjacent to this substrate, and in order to this conductor of contact; And
One first chip, has gold under a first surface, at least one projection, a protective layer, a connection pad and a ballBelong to layer, a surface of this protective layer is this first surface, and this protective layer has an opening to appear this connection pad of part,This ball lower metal layer be arranged on this protective layer and opening to contact this connection pad, the material of this connection pad be gold, this is protrudingPiece is positioned on this ball lower metal layer, and this upper surface of substantially vertical this substrate of this first surface of this first chip shouldThis conductor of bump contact.
9. semiconductor combinations structure as claimed in claim 8, is characterized in that, this electric connection place is conductive finger,And this barricade portion is positioned in this electric connection place.
10. semiconductor combinations structure as claimed in claim 8, is characterized in that, this conductor is spherical or column,It has a maximum height, and this maximum height is 15 to 30 μ m.
11. semiconductor combinations structures as claimed in claim 8, is characterized in that, the material of this barricade portion is not for leadingElectricity glue material.
12. semiconductor combinations structures as claimed in claim 8, is characterized in that, this barricade portion and this conductor contactAnd forming a contact-making surface, the peak of this contact-making surface is lower than the peak of this conductor itself.
13. semiconductor combinations structures as claimed in claim 8, is characterized in that, this ball lower metal layer sequentially comprisesOne the first metal layer, one second metal level and one the 3rd metal level, this first metal layer contacts this connection pad, and this is first years oldThe material of metal level is titanium, chromium, tungsten or zinc, and the material of this second metal level is nickel, nickel-vanadium alloy or nickel-phosphorus alloy,And the material of the 3rd metal level is copper.
14. semiconductor combinations structures as claimed in claim 8, is characterized in that, this ball lower metal layer sequentially comprisesOne the first metal layer and one second metal level, this first metal layer contacts this connection pad, and the material of this first metal layer isNickel, nickel-vanadium alloy or nickel-phosphorus alloy, and the material of this second metal level is copper.
15. semiconductor combinations structures as claimed in claim 8, is characterized in that, more comprise a primer and a sealingMaterial, coated this adhesive material of this projection of this primer be positioned at this upper surface of this substrate and coated this first chip, shouldPrimer and this barricade portion.
16. 1 kinds of semiconductor technologies, comprise the following steps:
(a) provide a substrate, this substrate has a upper surface and at least one electric connection place;
(b) form at least one conductor in this electric connection place;
(c) form a barricade portion and be adjacent to this substrate with this conductor of contact;
(d) provide one first chip, this first chip has a first surface and at least one projection, this projection positionIn this first surface of this first chip, and the material of this projection is different with the material of this conductor;
(e) engage this first chip to this substrate, wherein, this first surface of this first chip is substantially verticalThis upper surface of this substrate, this conductor of this bump contact; And
(f) heat, make this projection fusing cave in and be attached on this conductor.
17. as the semiconductor technology of claim 16, it is characterized in that, and in step (c), this barricade portion and thisConductor contact and form a contact-making surface, the peak of this contact-making surface is lower than the peak of this conductor itself.
18. as the semiconductor technology of claim 16, it is characterized in that, in step (d), this first chip moreThere is one the 3rd surface, the 3rd substantially vertical this first surface in surface, and the bottom of this projection and the 3rd surfaceBetween distance be substantially equal to the height sum of thickness and this conductor of this electric connection place.
19. as the semiconductor technology of claim 16, it is characterized in that, in step (d), this first chip moreHave a protective layer, a connection pad and a ball lower metal layer, this protective layer has an opening to appear this connection pad of part,This ball lower metal layer be arranged on this protective layer and opening to contact this connection pad, this projection is positioned at this ball lower metal layerUpper, wherein the material of this connection pad is gold.
20. as the semiconductor technology of claim 16, it is characterized in that, step (f) more comprises afterwards:
(g) form a primer to be coated this projection;
(h) adhere to one second chip to this substrate;
(i) adhere at least one the 3rd chip to this second chip;
(j) be electrically connected this second chip to this substrate, and be electrically connected the 3rd chip to this second chip;
(k) form an adhesive material in this upper surface of this substrate be coated this first chip, this second chip andThe 3rd chip; And
(l) carry out cutting step, to form several semiconductor combinations structures.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW102124282A TWI512908B (en) | 2013-07-05 | 2013-07-05 | Semiconductor assembly structure and semiconductor process |
| TW102124282 | 2013-07-05 |
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| Publication Number | Publication Date |
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| CN103441081A CN103441081A (en) | 2013-12-11 |
| CN103441081B true CN103441081B (en) | 2016-05-04 |
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| TW (1) | TWI512908B (en) |
Citations (6)
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|---|---|---|---|---|
| US6472305B1 (en) * | 1999-04-08 | 2002-10-29 | Casio Computer Co., Ltd. | Method of manufacturing bonded structure of film substrate and semiconductor chip |
| TW569403B (en) * | 2001-04-12 | 2004-01-01 | Siliconware Precision Industries Co Ltd | Multi-chip module and its manufacturing method |
| TW200636882A (en) * | 2005-04-11 | 2006-10-16 | Siliconware Precision Industries Co Ltd | Semiconductor device with under bump metallurgy structure |
| CN1893051A (en) * | 2005-06-28 | 2007-01-10 | 富士通株式会社 | Semiconductor device |
| TW201308563A (en) * | 2011-08-05 | 2013-02-16 | Chipmos Technologies Inc | Chip package structure |
| TW201324628A (en) * | 2011-12-14 | 2013-06-16 | Advanced Semiconductor Eng | Semiconductor package and method for making semiconductor substrate |
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2013
- 2013-07-05 TW TW102124282A patent/TWI512908B/en active
- 2013-09-05 CN CN201310399828.4A patent/CN103441081B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6472305B1 (en) * | 1999-04-08 | 2002-10-29 | Casio Computer Co., Ltd. | Method of manufacturing bonded structure of film substrate and semiconductor chip |
| TW569403B (en) * | 2001-04-12 | 2004-01-01 | Siliconware Precision Industries Co Ltd | Multi-chip module and its manufacturing method |
| TW200636882A (en) * | 2005-04-11 | 2006-10-16 | Siliconware Precision Industries Co Ltd | Semiconductor device with under bump metallurgy structure |
| CN1893051A (en) * | 2005-06-28 | 2007-01-10 | 富士通株式会社 | Semiconductor device |
| TW201308563A (en) * | 2011-08-05 | 2013-02-16 | Chipmos Technologies Inc | Chip package structure |
| TW201324628A (en) * | 2011-12-14 | 2013-06-16 | Advanced Semiconductor Eng | Semiconductor package and method for making semiconductor substrate |
Also Published As
| Publication number | Publication date |
|---|---|
| TW201503293A (en) | 2015-01-16 |
| TWI512908B (en) | 2015-12-11 |
| CN103441081A (en) | 2013-12-11 |
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