CN103500729A - Silicon pinboard structure and wafer level manufacturing method of silicon pinboard structure - Google Patents
Silicon pinboard structure and wafer level manufacturing method of silicon pinboard structure Download PDFInfo
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- CN103500729A CN103500729A CN201310492853.7A CN201310492853A CN103500729A CN 103500729 A CN103500729 A CN 103500729A CN 201310492853 A CN201310492853 A CN 201310492853A CN 103500729 A CN103500729 A CN 103500729A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
Abstract
The invention provides a silicon pinboard structure and a wafer level manufacturing method of the silicon pinboard structure. The method at least comprises the following steps that S1, a silicon wafer is provided, a wet process is adopted for corroding at least one pair of grooves distributed in upper and lower positions at the front side and the back side of the silicon wafer, and the pair of grooves share the groove bottom; S2, the wet process is adopted for corroding at least one silicon through hole formed in the groove bottom, the silicon through hole is formed by connecting an upper through hole and a lower through hole which are symmetrical at top and bottom, and the upper through hole and the lower through hole have inclined side walls; S3, through hole dielectric layers are formed on the surfaces of the side walls of the silicon through hole; S4, through hole metal layers are formed on the surfaces of the through hole dielectric layers; S5, finally, scribing is carried out for forming the independent pinboard. In the silicon pinboard provided by the invention, the silicon through hole has the inclined side walls, a one-hole multi-wire structure can be formed, the interconnection wire density can be improved, and the groove structure is favorable for realizing the system integration at higher density. The manufacturing method provided by the invention also has the advantages that the process difficulty is low, and the method is suitable for industrial production.
Description
Technical field
The invention belongs to three-dimensional high-density packaging interconnection technical field, relate to a kind of silicon adapter plate structure and wafer level manufacture method thereof.
Background technology
21 century, electronic product was tending towards more and more pursuing high-performance, high reliability, multifunction, miniaturization and low manufacturing cost, especially in recent years the arriving in multi-media network epoch, the wilderness demand of the handheld terminals such as laptop computer, smart mobile phone and panel computer, the capacity of communication is increased, require signal transmission and disposal ability at a high speed.Under this background, the integrated level of integrated circuit and performance are also by the every rule development doubled in 18 months of mole law (Moore ' s law).But along with the limitation of semiconductor scaled down day by day highlights, traditional two-dimentional integrated technology makes in the situation that the problems such as distorted signals, delay are day by day serious, and system integration teacher start to turn to more and more three-dimensional integrated (3D Integration), system-level integrated technology.
The silicon keyset, utilize through-silicon via structure can realize the perpendicular interconnection of the chip chamber signal of telecommunication, shortened the transmission path of the signal of telecommunication; Simultaneously, as the package carrier of flip-chip, two-sided can integrated variety classes, the chip of difference in functionality, realize the three-dimensional stacked integrated of chip, be the integrated technology that represents of three dimension system.Wherein, passive keyset can realize that the density three-dimensional mixing of different components is integrated under the prerequisite that does not change original layout, therefore, is topmost packing forms in the three-dimensional integrated application of coming 10 years.
Key in silicon keyset and corresponding 3D encapsulation technology thereof is the making of silicon perforation (Through Silicon Vias, TSV) structure, and its effect is to realize perpendicular interconnection positive and reverse side.In making the TSV process, the TSV that the deep hole sidewall is vertical profile is the emphasis of research at present, because the TSV of vertical profile can control minimumly due to its size, therefore can realize the 3D high integration interconnection of fine pith (fine pitch).But because the TSV manufacturing process of vertical profile is very complicated, particularly dry etching forms vertical long hole, PVD realizes continuous uniform covering, the flash plate of deep hole sidewall and bottom seed layer are realized the zero defect of deep hole is filled, and follow-up TSV wafer planarization metallization processes etc., all traditional microelectronic technique is difficult to successfully realize, and poor reliability, with high costs, this is also the key point that current TSV technology is difficult to realize application.
Summary of the invention
The shortcoming of prior art, the object of the present invention is to provide a kind of silicon adapter plate structure and wafer level manufacture method thereof in view of the above, for solving the problem that prior art is with high costs, manufacture difficulty is high.
Reach for achieving the above object other relevant purposes, the invention provides a kind of wafer level manufacture method of silicon adapter plate structure, at least comprise the following steps:
S1 a: silicon wafer is provided, adopts wet etching in described silicon wafer front and the back side forms at least one pair of groove distributed up and down; A pair of groove shares bottom portion of groove;
S2: adopt wet etching to form at least one silicon through hole in described bottom portion of groove; Described silicon through hole is formed by connecting by laterally zygomorphic upper through hole and lower through-hole; Described upper through hole and lower through-hole have sloped sidewall;
S3: the sidewall surfaces at described silicon through hole forms the through hole dielectric layer;
S4: on described through hole dielectric layer surface, form the via metal layer;
S5: last scribing forms independently silicon keyset.
Alternatively, the longitudinal section of described upper through hole is inverted trapezoidal; The longitudinal section of described lower through-hole is trapezoidal.
Alternatively, the angle on the sidewall of described upper through hole and plane, described bottom portion of groove place is 54.7 degree, and the angle on the sidewall of described lower through-hole and plane, described bottom portion of groove place is 54.7 degree.
Alternatively, the cross section of described silicon through hole is rectangle or square.
Alternatively, in described step S4, described via metal layer is for covering the metal level of full four sidewall surfaces of described through hole, or described via metal layer is at least one wires that is distributed in described one of them sidewall surfaces of silicon through hole, or described via metal layer is at least two discrete metal wires that are distributed at least two sidewall surfaces of described silicon through hole.
Alternatively, (100) crystal face silicon chip that described silicon wafer is twin polishing.
Alternatively, adopt the first etching mask to form described groove, when photoetching forms described the first etching mask by the graphic limit of the first optical mask plate and described (100) crystal face silicon chip<110 > crystal orientation align; Adopt the second etching mask to form described silicon through hole, when photoetching forms described the second etching mask by the graphic limit of the second optical mask plate and described (100) crystal face silicon chip<110 > crystal orientation align.
Alternatively, in described step S3, when forming described through hole dielectric layer, form the groove dielectric layer in described groove surfaces simultaneously; In described step S4, when forming the via metal layer, form metal reroute layer and metal pad on described groove dielectric layer surface simultaneously.
Alternatively, in described step S1 and step S2, described wet etching all adopts the anisotropic etchant of silicon.
Alternatively, described groove has sloped sidewall.
The present invention also provides a kind of silicon adapter plate structure, comprising:
Silicon wafer;
At least one pair of groove distributed up and down, be formed at respectively described silicon wafer front and the back side; A pair of groove shares bottom portion of groove;
Be formed at least one the silicon through hole in described bottom portion of groove;
Be formed at the through hole dielectric layer on described through-silicon via sidewall surface;
And be formed at the via metal layer on described through hole dielectric layer surface;
Described silicon through hole is formed by connecting by laterally zygomorphic upper through hole and lower through-hole; Described upper through hole and lower through-hole have sloped sidewall.
Alternatively, described via metal layer is for covering the metal level of full four sidewall surfaces of described through hole, or described via metal layer is at least one wires that is distributed in described one of them sidewall surfaces of silicon through hole, or described via metal layer is at least two discrete metal wires that are distributed at least two sidewall surfaces of described silicon through hole.
As mentioned above, silicon adapter plate structure of the present invention and wafer level manufacture method thereof have following beneficial effect: with the silicon through hole keyset of making based on dry etching of main flow, compare, the present invention has the advantage of low cost, high reliability; The silicon through hole that the present invention is based on the wet etching making has sloped sidewall, be conducive to form high-quality through hole insulating barrier on the through-silicon via sidewall surface, and be conducive to form graphical via metal layer in through hole, thereby can form a hole multiple line structure, improve interconnection line density; There is at least one pair of groove structure in silicon keyset of the present invention, can reduce the thickness of silicon through hole, be conducive to reduce aperture, improve the silicon via densities, simultaneously can embedding chip in groove, thereby reduce the thickness of three-dimensional stacked rear whole package module, realize the more system integration of high density, small size; The wafer level manufacture method of silicon adapter plate structure of the present invention also has advantages of that technology difficulty is low, is suitable for suitability for industrialized production.
The accompanying drawing explanation
Fig. 1 is shown as the schematic diagram of silicon wafer in the wafer level manufacture method of silicon adapter plate structure of the present invention.
Fig. 2 is shown as the schematic diagram that forms graphical the first photoresist layer in the wafer level manufacture method of silicon adapter plate structure of the present invention.
Fig. 3 is shown as the schematic diagram that forms groove in the wafer level manufacture method of silicon adapter plate structure of the present invention.
Fig. 4 is shown as the schematic diagram that forms graphical the second photoresist layer in the wafer level manufacture method of silicon adapter plate structure of the present invention.
Fig. 5 is shown as the schematic diagram that forms the silicon through hole in the wafer level manufacture method of silicon adapter plate structure of the present invention.
Fig. 6 is shown as the schematic diagram that forms the through hole dielectric layer in the wafer level manufacture method of silicon adapter plate structure of the present invention.
Fig. 7 is shown as the schematic diagram of silicon adapter plate structure of the present invention.
Fig. 8 is shown as the schematic diagram that forms hole one line structure in the wafer level manufacture method of silicon adapter plate structure of the present invention.
Fig. 9 is shown as the schematic diagram that forms hole four line structures in the wafer level manufacture method of silicon adapter plate structure of the present invention.
Figure 10 is shown as the schematic diagram that forms hole eight line structures in the wafer level manufacture method of silicon adapter plate structure of the present invention.
Figure 11 is shown as the schematic diagram that forms another kind of hole eight line structures in the wafer level manufacture method of silicon adapter plate structure of the present invention.
Figure 12 is shown as the three-dimensional stacked encapsulating structure schematic diagram of silicon adapter plate structure of the present invention and chip.
Figure 13 is shown as the system-in-package structure schematic diagram of silicon adapter plate structure of the present invention and chip and pcb board.
The element numbers explanation
1 silicon wafer
2 first silicon dioxide passivation layer
3 graphical the first photoresist layers
4 grooves
5 bottom portion of groove
6 second silicon dioxide passivation layer
7 graphical the second photoresist layers
8 silicon through holes
9 through hole dielectric layers
10 groove dielectric layers
11 via metal layers
The 12 metals layer that reroutes
13 metal pads
14 first chips
15 second chips
16 lead-in wires
17 solder bumps
18 the 3rd chips
19 ball grid array
20 pcb boards
Embodiment
Below, by specific instantiation explanation embodiments of the present invention, those skilled in the art can understand other advantages of the present invention and effect easily by the disclosed content of this specification.The present invention can also be implemented or be applied by other different embodiment, and the every details in this specification also can be based on different viewpoints and application, carries out various modifications or change not deviating under spirit of the present invention.
Refer to Fig. 1 to Figure 13.It should be noted that, the diagram provided in the present embodiment only illustrates basic conception of the present invention in a schematic way, satisfy in graphic and only show with assembly relevant in the present invention but not component count, shape and size drafting while implementing according to reality, during its actual enforcement, kenel, quantity and the ratio of each assembly can be a kind of random change, and its assembly layout kenel also may be more complicated.
The invention provides a kind of wafer level manufacture method of silicon adapter plate structure, at least comprise the following steps:
S1 a: silicon wafer is provided, adopts wet etching in described silicon wafer front and the back side forms at least one pair of groove distributed up and down; A pair of groove shares bottom portion of groove;
S2: adopt wet etching to form at least one silicon through hole in described bottom portion of groove; Described silicon through hole is formed by connecting by laterally zygomorphic upper through hole and lower through-hole; Described upper through hole and lower through-hole have sloped sidewall;
S3: the sidewall surfaces at described silicon through hole forms the through hole dielectric layer;
S4: on described through hole dielectric layer surface, form the via metal layer;
S5: last scribing forms independently silicon keyset.
At first refer to Fig. 1 to Fig. 3, execution step S1: a silicon wafer 1 is provided, adopts wet etching in described silicon wafer front and the back side forms at least one pair of groove 4 distributed up and down; A pair of groove shares bottom portion of groove 5.
Concrete, described silicon wafer 1 preferably adopts (100) silicon chip of twin polishing, and Fig. 1 is shown as the structural representation of described silicon wafer 1.
Concrete, at first described silicon wafer 1 is carried out to standard cleaning, then the silicon wafer 1 Double-side hot oxidation after cleaning, front and the back side at described silicon wafer 1 form the first silicon dioxide passivation layer 2, spin coating the first photoresist layer on described the first silicon dioxide passivation layer 2 again, and exposed and develop, obtain graphical the first photoresist layer 3, as shown in Figure 2.
Then the figure on described graphical the first photoresist layer 3 is transferred on described the first silicon dioxide passivation layer 2, obtained being used to form first etching mask (not giving diagram herein) of described groove 5.Then remove again described graphical the first photoresist layer 3, and silicon wafer is put into to the anisotropic etchant of silicon, corrode to certain depth and take out, thereby make, obtain described groove 4.Finally remove described the first etching mask, the groove structure obtained as shown in Figure 3.
It is pointed out that a pair of groove can be symmetrical up and down, center is symmetrical and measure-alike, and bottom portion of groove overlaps fully; In addition, positive groove and the groove center at the back side can be asymmetric, and size also can be different, and bottom portion of groove only partially overlaps, and wherein, shared bottom portion of groove partly is used to form the silicon through hole.The present embodiment is depicted as the upper and lower symmetrical situation of a pair of groove.
Concrete, described the first photoresist layer adopts the photoresist that model is LC100A, its thickness is preferably 1.7 microns, wherein, the front baking technique of first surface photoresist is carried out on hot plate or in baking oven, and the front baking technique of second photoresist can only be carried out in baking oven, if this is that the photoetching offset plate figure of first surface is by destroyed because of front baking on hot plate.In photoetching process, adopt the first optical mask plate during exposure, and by the graphic limit of described the first optical mask plate and described (100) crystal face silicon chip<110 > crystal orientation align.After development, the post bake temperature and time of first surface photoresist is respectively 135 ℃ and 10 minutes, and the post bake temperature and time of second photoresist is respectively 135 ℃ and 30 minutes.Be only example, the parameters such as photoresist thickness, post bake temperature and time can be adjusted as required herein, and this common practise that is this area, should too not limit the scope of the invention.
Concrete, thereby the figure on described graphical the first photoresist layer 3 is transferred on described the first silicon dioxide passivation layer 2 to the method for the first etching mask that obtains being used to form described groove 5, can adopt BOE corrosive liquid (HF:NH4F:H2O), also can adopt reactive ion etching (RIE).In actual production process, can select a kind of wherein method according to the requirement of dimension of picture precision, speed and the cost requirement of reaction rate.The BOE corrosion of take in the present embodiment describes as example.Before adopting the BOE corrosion, need be by silicon wafer etching one minute (being commonly called as the bottoming film) in the plasma ashing system, to remove the residual photoresist in photoetching window place, and then corrosion a period of time obtains described the first etching mask.Corrosion temperature and etching time are determined according to the thickness of described the first silicon dioxide passivation layer 2, and the thickness of the first silicon dioxide passivation layer 2 described in the present embodiment be take 2 microns as example, and at 35 ℃ of temperature, the corrosion required time is about 10 minutes.
Concrete, the method for removing described graphical the first photoresist layer 3 is preferably boils 10 minutes in the concentrated sulfuric acid of 120 ℃, can certainly adopt other method, this common practise that is this area.Described anisotropic etchant is preferably the KOH corrosive liquid, and this solution is 40%(wt. at 50 ℃, concentration) under condition to the about 10-12.5 micron of the corrosion rate of (100) crystal face/hour, and there is corrosion surface pattern preferably.In the present embodiment, the groove corrosion depth is preferably 90 microns, and in actual applications, the chip size that can be interconnected is as required adjusted depth of groove.Described groove 4 has sloped sidewall, it is trapezoidal that longitudinal section is, adopt (100) crystal face silicon chip in the present embodiment, and during photoetching optical mask plate graphic limit and (100) crystal face silicon chip<110 > crystal orientation align, therefore { the 111} crystal face that the sidewall of the final groove 4 formed is silicon, with bottom surface (100) crystal face angle be 54.7 degree, with the angle on plane, described bottom portion of groove place, be 54.7 degree.
Concrete, remove described the first etching mask and preferably adopt the BOE solution corrosion.
Then refer to Fig. 4 and Fig. 5, execution step S2: adopt wet etching to form at least one silicon through hole 8 at described bottom portion of groove 5; Described silicon through hole is formed by connecting by laterally zygomorphic upper through hole and lower through-hole; Described upper through hole and lower through-hole have sloped sidewall.
Concrete, first by the oxidation again of silicon wafer surface, form the second silicon dioxide passivation layer 6, then spraying photoresist graphical on described second silicon dioxide passivation layer 6 at front and the back side, form patterned the second photoresist layer 7, as shown in Figure 4.Then the figure on described graphical the second photoresist layer 7 is transferred on described the second silicon dioxide passivation layer 6, obtained being used to form second etching mask (not giving diagram herein) of described silicon through hole 8.Then remove again described graphical the second photoresist layer 7, and silicon wafer is put into to the anisotropic etchant of silicon, the silicon wafer corruption is worn to rear taking-up, thereby make, obtain described silicon through hole 8.Finally remove described the second etching mask, the through-silicon via structure obtained as shown in Figure 5.
Concrete, the cross section of described silicon through hole 8 is rectangle or square.When photoetching forms described the second etching mask by the graphic limit of the second optical mask plate and described (100) crystal face silicon chip<110 > crystal orientation align.Adopt described the second etching mask to form in the process of described silicon through hole 8, silicon wafer front and the back side start corrosion simultaneously, and the silicon through hole 8 obtained is formed by connecting by laterally zygomorphic upper through hole and lower through-hole; Described upper through hole and lower through-hole have sloped sidewall.Wherein, the longitudinal section of described upper through hole is inverted trapezoidal; The longitudinal section of described lower through-hole is trapezoidal, and described silicon through hole 8 presents large, the middle little design feature in two ends.Due to graphic limit and described (100) crystal face silicon chip<110 > crystal orientation align, therefore the sidewall of described upper through hole and the angle on plane, described bottom portion of groove place are 54.7 degree, and the angle on the sidewall of described lower through-hole and plane, described bottom portion of groove place is also 54.7 degree.
Concrete, the instrument that the spraying photoresist is used on described second silicon dioxide passivation layer 6 at front and the back side is the EVG101 spraying colloid system, this system can realize the coating technique of three-dimensional structure, and the surface of three-dimensional structure and sidewall are realized covering comprehensively, and glue is thick simultaneously reaches ten microns left and right.Implement, in spray-bonding craft and exposure technology subsequently, because of the existence of silicon wafer upper groove structure, disk to be attached on a slide glass, to realize disk fixing on sucker.The concrete steps that form described graphical the second photoresist layer 7 are:
1) use high temperature gummed tape that silicon wafer is attached on a slide glass;
2) simultaneously spray photoresist at silicon wafer, photoresist is realized comprehensive uniform fold to described the second silicon dioxide passivation layer 6;
3) silicon wafer is separated with slide glass, and described silicon wafer is put into to the baking oven front baking 8 minutes of 120 ℃;
4) use high temperature gummed tape to be attached to conversely on slide glass by silicon wafer;
5) spray photoresist on the silicon wafer another side;
6) silicon wafer is separated with slide glass, and silicon wafer is put into to the baking oven front baking 10 minutes of 120 ℃;
7) after silicon wafer is cooling, reuse high temperature gummed tape silicon wafer is attached on slide glass, and to the one side exposure;
8) silicon wafer is used conversely high temperature gummed tape paste slide glass, another side is exposed;
9) developed together in silicon wafer front and the back side, then wash by water, dry, obtain patterned the second photoresist layer 7.
Concrete, thereby the figure on described graphical the second photoresist layer 7 is transferred on described the second silicon dioxide passivation layer 6 to the method for the second etching mask that obtains being used to form described silicon through hole 8, can adopt BOE corrosive liquid (HF:NH4F:H2O), also can adopt reactive ion etching (RIE).The method of removing described graphical the second photoresist layer 7 is preferably boils 10 minutes in the concentrated sulfuric acid of 120 ℃.The anisotropic etchant of described silicon is KOH solution, in this enforcement, preferably adopts 40%(wt.) the KOH corrosive liquid, the silicon through hole 8 obtained has good surface topography.After forming the silicon through hole, remove described the second etching mask and preferably adopt the BOE solution corrosion.
Then refer to Fig. 6, execution step S3: the sidewall surfaces at described silicon through hole 8 forms through hole dielectric layer 9.
Concrete, form described through hole dielectric layer 9 by thermal oxidation process, when forming described through hole dielectric layer 9, around reaching, described groove surfaces forms groove dielectric layer 10 simultaneously.The thickness range of described through hole dielectric layer 9 and described groove dielectric layer 10 is 1～2 micron.Described through hole dielectric layer 9 is for the insulation of described silicon through hole 8.
Refer to again Fig. 7, execution step S4: on described through hole dielectric layer 9 surfaces, form via metal layer 11.
Concrete, when forming described via metal layer 10, form metals reroute layer 12 and metal pad 13 on described groove dielectric layer 9 surfaces simultaneously.The formation method is: at silicon wafer tow sides splash-proofing sputtering metal layer, carry out the glue spraying photoetching simultaneously, and litho pattern is transferred to described metal level, thereby form described via metal layer 11, metal reroute layer 12 and metal pad 13.
Concrete, state via metal layer 11 for covering the metal level of full four sidewall surfaces of described silicon through hole, or described via metal layer 11 is for being distributed at least one wires of described one of them sidewall surfaces of silicon through hole, or described via metal layer 11 is for being distributed at least two discrete metal wires of at least two sidewall surfaces of described silicon through hole.In other words, can form hole one line structure or a hole multiple line structure.Refer to Fig. 8 to Figure 11, wherein, Fig. 8 is shown as hole one line structure, as shown in Figure 8, via metal layer 11 covers full four sidewall surfaces of described silicon through hole, and the outer metal of silicon through hole reroutes layer 12 for wire and contacts with described via metal layer 11, forms hole one line structure; In another embodiment, described via metal layer 11 also can be for being distributed in a wires of described one of them sidewall surfaces of silicon through hole, and just for hole one line structure, this kind of technique is comparatively complicated, is unfavorable for saving cost.Fig. 9 is shown as hole four line structures, and Figure 10 and Figure 11 are shown as hole eight line structures.Be only example herein, can also carry out more changeableization, as hole six lines, ten lines etc., and on different lateral, the distribution number can be changed, and should too not limit the scope of the invention herein.
Concrete, described metal level comprises TiW layer and formation and the Cu layer on it, and wherein, the TiW layer is as adhesion layer and diffusion impervious layer, and the Cu layer is as the conducting function layer.In the present embodiment, the thickness of TiW layer/Cu layer is preferably 50 nanometers/300 nanometers.The instrument that the spraying photoresist is used on described metal level is the EVG101 spraying colloid system, implements, in spray-bonding craft and exposure technology subsequently, silicon wafer to be attached on slide glass, to realize silicon wafer fixing on sucker.The concrete steps that litho pattern is transferred on described metal level are:
1) silicon wafer is put into to plasma ashing system etching one minute, to remove the residual photoresist in photoetching window place;
2) silicon wafer is put into to two-sided electroplating bath, carried out two-sided Cu electroplating technology;
3), after having electroplated, use acetone soln that photoresist layer is soaked and removes;
4) use plasma etching (IBE) technique successively to silicon wafer front and back-etching, to remove metal seed layer.
Finally perform step S5: scribing forms independently silicon keyset.
So far, the wafer level that has completed the silicon adapter plate structure is made.
The wafer level manufacture method of silicon adapter plate structure of the present invention is compared with the silicon through hole of making based on the dry etching switching class of main flow, has the advantage of low cost, high reliability; And the through-silicon via structure of making based on wet etching in the present invention, there is sloped sidewall, be conducive to make the insulating barrier of silicon through hole and form patterned via metal layer, realize that a hole is multi-thread, improve interconnection density; And manufacture method technology difficulty of the present invention is low, be applicable to suitability for industrialized production.
The present invention also provides a kind of silicon adapter plate structure, refers to Fig. 7, is shown as the generalized section of described silicon adapter plate structure, comprising:
At least one pair of groove 4 distributed up and down, be formed at respectively described silicon wafer 1 front and the back side; A pair of groove shares bottom portion of groove 5;
Be formed at least one the silicon through hole 8 in described bottom portion of groove 5;
Be formed at the through hole dielectric layer 9 of described silicon through hole 8 sidewall surfaces;
And be formed at the via metal layer 11 on described through hole dielectric layer 9 surfaces;
Described silicon through hole 8 is formed by connecting by laterally zygomorphic upper through hole and lower through-hole; Described upper through hole and lower through-hole have sloped sidewall.
Concrete, the cross section of described silicon through hole 8 is square or rectangle, and described silicon through hole 8 presents large, the middle little design feature in two ends, and the longitudinal section of described upper through hole is inverted trapezoidal, and the longitudinal section of described lower through-hole is trapezoidal.The angle on the sidewall of described upper through hole and plane, described bottom portion of groove place is 54.7 degree, and the angle on the sidewall of described lower through-hole and plane, described bottom portion of groove place is 54.7 degree.
Concrete, state the via metal layer for covering the metal level of full four sidewall surfaces of described silicon through hole, or described via metal layer is at least one wires that is distributed in described one of them sidewall surfaces of silicon through hole, or described via metal layer is at least two discrete metal wires that are distributed at least two sidewall surfaces of described silicon through hole, form hole one line or a hole multiple line structure.Described groove surfaces and around there is groove dielectric layer 10, be formed with the metal layer 12 and metal pad 13 that reroutes on described groove dielectric layer.
In order to show the beneficial effect of silicon adapter plate structure of the present invention, the three-dimensional stacking structure figure of described silicon adapter plate structure and chip also is provided in the present embodiment, as shown in figure 12, and described silicon adapter plate structure and chip and the structure chart of pcb board after integrated, as shown in figure 13.
At first refer to Figure 12, be shown as the three-dimensional stacked encapsulation (3D Stacked Package) of described silicon adapter plate structure and chip, as shown in the figure, the first chip 14 and the second chip 15 are fixed in the groove of described silicon adapter plate structure, wherein, described the first chip 14 and described silicon adapter plate structure 16 carry out being connected of electricity by going between, use be Wire Bonding Technology (Wire Bonding); Described the second chip 15 carries out electricity with described silicon keyset by solder bump 17 and is connected, use be flip chip bonding (Flip Chip) technology.
In silicon adapter plate structure of the present invention, the existence of described groove 4 makes the degree of depth of the silicon through hole 8 of making reduce, and its respective transversal size also reduces thereupon, can significantly improve packaging density; Simultaneously, this Structure Decreasing the thickness of three-dimensional stacked rear whole package module; And a hole multiple line structure can improve interconnection line density.Whole three-dimensional stacked package module realized higher density the system integration, dwindled the system in package volume and improved systematic function; Simultaneously, whole package module technical process is simple, cost is lower.
Refer to again Figure 13, demonstration be the system in package (System InPackage, SIP) of described silicon keyset and chip and pcb board.Described the first chip 14 also can adopt the mode of flip chip bonding and described silicon keyset to be interconnected; Simultaneously, utilize described the first chip 14 to be embedded in the characteristics in described groove 4, stacking the 3rd chip 18 again on it, make that system is compacter, packaging density is higher.And whole stack module can be connected with pcb board 20 by ball grid array 19.
In sum, silicon adapter plate structure of the present invention and wafer level manufacture method thereof have the advantage of low cost, high reliability; The silicon through hole that the present invention is based on the wet etching making has sloped sidewall, be conducive to form high-quality through hole insulating barrier on the through-silicon via sidewall surface, and be conducive to form figure via metal layer in through hole, thereby can form a hole multiple line structure, improve interconnection line density; There is at least one pair of groove structure in silicon keyset of the present invention, can reduce the thickness of silicon through hole, be conducive to reduce aperture, improve the silicon via densities, simultaneously can embedding chip in groove, thus the thickness of three-dimensional stacked rear whole package module reduced, realize the more highdensity system integration; The manufacture method of silicon adapter plate structure of the present invention also has advantages of that technology difficulty is low, is suitable for suitability for industrialized production.So the present invention has effectively overcome various shortcoming of the prior art and the tool high industrial utilization.
Above-described embodiment is illustrative principle of the present invention and effect thereof only, but not for limiting the present invention.Any person skilled in the art scholar all can, under spirit of the present invention and category, be modified or be changed above-described embodiment.Therefore, such as in affiliated technical field, have and usually know that the knowledgeable, not breaking away from all equivalence modifications that complete under disclosed spirit and technological thought or changing, must be contained by claim of the present invention.
Claims (12)
1. the wafer level manufacture method of a silicon adapter plate structure, is characterized in that, at least comprises the following steps:
S1 a: silicon wafer is provided, adopts wet etching in described silicon wafer front and the back side forms at least one pair of groove distributed up and down; A pair of groove shares bottom portion of groove;
S2: adopt wet etching to form at least one silicon through hole in described bottom portion of groove; Described silicon through hole is formed by connecting by laterally zygomorphic upper through hole and lower through-hole; Described upper through hole and lower through-hole have sloped sidewall;
S3: the sidewall surfaces at described silicon through hole forms the through hole dielectric layer;
S4: on described through hole dielectric layer surface, form the via metal layer;
S5: last scribing forms independently silicon keyset.
2. the wafer level manufacture method of silicon adapter plate structure according to claim 1, it is characterized in that: the longitudinal section of described upper through hole is inverted trapezoidal; The longitudinal section of described lower through-hole is trapezoidal.
3. the wafer level manufacture method of silicon adapter plate structure according to claim 2, it is characterized in that: the angle on the sidewall of described upper through hole and plane, described bottom portion of groove place is 54.7 degree, and the angle on the sidewall of described lower through-hole and plane, described bottom portion of groove place is 54.7 degree.
4. the wafer level manufacture method of silicon adapter plate structure according to claim 1, it is characterized in that: the cross section of described silicon through hole is rectangle or square.
5. the wafer level manufacture method of silicon adapter plate structure according to claim 4, it is characterized in that: in described step S4, described via metal layer is for covering the metal level of full four sidewall surfaces of described through hole, or described via metal layer is at least one wires that is distributed in described one of them sidewall surfaces of silicon through hole, or described via metal layer is at least two discrete metal wires that are distributed at least two sidewall surfaces of described silicon through hole.
6. the wafer level manufacture method of silicon adapter plate structure according to claim 1, is characterized in that: (100) crystal face silicon chip that described silicon wafer is twin polishing.
7. the wafer level manufacture method of silicon adapter plate structure according to claim 6, it is characterized in that: adopt the first etching mask to form described groove, when photoetching forms described the first etching mask by the graphic limit of the first optical mask plate and described (100) crystal face silicon chip<110 > crystal orientation align; Adopt the second etching mask to form described silicon through hole, when photoetching forms described the second etching mask by the graphic limit of the second optical mask plate and described (100) crystal face silicon chip<110 > crystal orientation align.
8. the wafer level manufacture method of silicon adapter plate structure according to claim 1 is characterized in that: in described step S3, when forming described through hole dielectric layer, form the groove dielectric layer in described groove surfaces simultaneously; In described step S4, when forming the via metal layer, form metal reroute layer and metal pad on described groove dielectric layer surface simultaneously.
9. the wafer level manufacture method of silicon adapter plate structure according to claim 1, it is characterized in that: in described step S1 and step S2, described wet etching all adopts the anisotropic etchant of silicon.
10. the wafer level manufacture method of silicon adapter plate structure according to claim 1, it is characterized in that: described groove has sloped sidewall.
11. a silicon adapter plate structure comprises:
Silicon wafer;
At least one pair of groove distributed up and down, be formed at respectively described silicon wafer front and the back side; A pair of groove shares bottom portion of groove;
Be formed at least one the silicon through hole in described bottom portion of groove;
Be formed at the through hole dielectric layer on described through-silicon via sidewall surface;
And be formed at the via metal layer on described through hole dielectric layer surface;
It is characterized in that:
Described silicon through hole is formed by connecting by laterally zygomorphic upper through hole and lower through-hole; Described upper through hole and lower through-hole have sloped sidewall.
12. silicon adapter plate structure according to claim 1, it is characterized in that: described via metal layer is for covering the metal level of full four sidewall surfaces of described through hole, or described via metal layer is at least one wires that is distributed in described one of them sidewall surfaces of silicon through hole, or described via metal layer is at least two discrete metal wires that are distributed at least two sidewall surfaces of described silicon through hole.
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