CN103500729B - Silicon adapter plate structure and wafer level manufacture method thereof - Google Patents
Silicon adapter plate structure and wafer level manufacture method thereof Download PDFInfo
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- CN103500729B CN103500729B CN201310492853.7A CN201310492853A CN103500729B CN 103500729 B CN103500729 B CN 103500729B CN 201310492853 A CN201310492853 A CN 201310492853A CN 103500729 B CN103500729 B CN 103500729B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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Abstract
The invention provides a kind of silicon adapter plate structure and wafer level manufacture method thereof, the method at least comprises the following steps: S1: provide a silicon wafer, adopts wet etching to form at least one pair of groove distributed up and down in described silicon wafer front and the back side; A pair groove shares bottom portion of groove; S2: adopt wet etching to form at least one silicon through hole in described bottom portion of groove; Described silicon through hole is formed by connecting by laterally zygomorphic upper through hole and lower through-hole; Described upper through hole and lower through-hole have sloped sidewall; S3: form through hole dielectric layer in the sidewall surfaces of described silicon through hole; S4: form via metal layer at described through hole dielectric layer surface; S5: last scribing forms independently silicon keyset.In silicon keyset of the present invention, silicon through hole has sloped sidewall, can form a hole multiple line structure, improves interconnection line density; Groove structure is conducive to realizing the more highdensity system integration; Manufacture method of the present invention also has the advantage that technology difficulty is low, be suitable for suitability for industrialized production.
Description
Technical field
The invention belongs to three-dimensional high-density packaging interconnection technical field, relate to a kind of silicon adapter plate structure and wafer level manufacture method thereof.
Background technology
21 century, electronic product was tending towards more and more pursuing high-performance, high reliability, multifunction, miniaturization and low manufacturing cost, especially the arriving in multi-media network epoch in recent years, the wilderness demand of the handheld terminals such as laptop computer, smart mobile phone and panel computer, the capacity of information transmission is increased, requires Signal transmissions at a high speed and disposal ability.In this context, the integrated level of integrated circuit and performance are also by Moore's Law (Moore ' s law) every rule development doubled for 18 months.But along with the limitation of semiconductor scaled down day by day highlights, when traditional two-dimentional integrated technology makes the problem such as distorted signals, delay day by day serious, system integration teacher start to turn to three-dimensional integrated (3D Integration), system-level integrated technology more and more.
Silicon keyset, utilizes through-silicon via structure can realize the perpendicular interconnection of the chip chamber signal of telecommunication, shortens the transmission path of the signal of telecommunication; Meanwhile, as the package carrier of flip-chip, two-sided can integrated variety classes, difference in functionality chip, realizing the three-dimensional stacked integrated of chip, is the integrated representative technology of three dimension system.Wherein, passive transition plate under the prerequisite not changing original layout, can realize the density three-dimensional hybrid integrated of different components, therefore, is topmost packing forms in the three-dimensional Integrated predict model of coming 10 years.
Key in silicon keyset and corresponding 3D encapsulation technology thereof is the making of silicon perforation (Through Silicon Vias, TSV) structure, and its effect is the perpendicular interconnection realizing front and reverse side.In making TSV process, the emphasis of deep hole sidewall be the TSV of vertical profile be research at present, because the TSV of vertical profile can control minimum due to its size, the 3D high integration that therefore can realize fine pith (fine pitch) interconnects.But because the TSV manufacturing process of vertical profile is very complicated, particularly dry etching forms vertical long hole, PVD realizes covering the continuous uniform of deep hole sidewall and bottom seed layer, flash plate realizes filling the zero defect of deep hole, and follow-up TSV wafer flatening process etc., all that conventional microelectronic technique is difficult to successfully realize, and poor reliability, with high costs, this is also the key point that current TSV technology is difficult to realize application.
Summary of the invention
The shortcoming of prior art in view of the above, the object of the present invention is to provide a kind of silicon adapter plate structure and wafer level manufacture method thereof, for solving with high costs in prior art, that manufacture difficulty is high problem.
For achieving the above object and other relevant objects, the invention provides a kind of wafer level manufacture method of silicon adapter plate structure, at least comprise the following steps:
S1: provide a silicon wafer, adopts wet etching to form at least one pair of groove distributed up and down in described silicon wafer front and the back side; A pair groove shares bottom portion of groove;
S2: adopt wet etching to form at least one silicon through hole in described bottom portion of groove; Described silicon through hole is formed by connecting by laterally zygomorphic upper through hole and lower through-hole; Described upper through hole and lower through-hole have sloped sidewall;
S3: form through hole dielectric layer in the sidewall surfaces of described silicon through hole;
S4: form via metal layer at described through hole dielectric layer surface;
S5: last scribing forms independently silicon keyset.
Alternatively, the longitudinal section of described upper through hole is inverted trapezoidal; The longitudinal section of described lower through-hole is trapezoidal.
Alternatively, the sidewall of described upper through hole and the angle of described bottom portion of groove place plane are 54.7 degree, and the sidewall of described lower through-hole and the angle of described bottom portion of groove place plane are 54.7 degree.
Alternatively, the cross section of described silicon through hole is rectangle or square.
Alternatively, in described step S4, described via metal layer is the metal level covering full described through hole four sidewall surfaces, or described via metal layer is for being distributed at least one wires of described one of them sidewall surfaces of silicon through hole, or described via metal layer is be distributed in the discrete metal wire of at least two of described silicon through hole at least two sidewall surfaces.
Alternatively, described silicon wafer is (100) crystal face silicon chip of twin polishing.
Alternatively, adopt the first etching mask to form described groove, when photoetching forms described first etching mask, is alignd in the <110> crystal orientation of the graphic limit of the first optical mask plate with described (100) crystal face silicon chip; Adopt the second etching mask to form described silicon through hole, when photoetching forms described second etching mask, is alignd in the <110> crystal orientation of the graphic limit of the second optical mask plate with described (100) crystal face silicon chip.
Alternatively, in described step S3, when forming described through hole dielectric layer, form groove dielectric layer in described groove surfaces simultaneously; In described step S4, when forming via metal layer, simultaneously forming metal at described groove dielectric layer surface and to reroute layer and metal pad.
Alternatively, in described step S1 and step S2, described wet etching all adopts the anisotropic etchant of silicon.
Alternatively, described groove has sloped sidewall.
The present invention also provides a kind of silicon adapter plate structure, comprising:
Silicon wafer;
At least one pair of groove distributed up and down, is formed at described silicon wafer front and the back side respectively; A pair groove shares bottom portion of groove;
Be formed at least one the silicon through hole in described bottom portion of groove;
Be formed at the through hole dielectric layer on described through-silicon via sidewall surface;
And be formed at the via metal layer of described through hole dielectric layer surface;
Described silicon through hole is formed by connecting by laterally zygomorphic upper through hole and lower through-hole; Described upper through hole and lower through-hole have sloped sidewall.
Alternatively, described via metal layer is the metal level covering full described through hole four sidewall surfaces, or described via metal layer is for being distributed at least one wires of described one of them sidewall surfaces of silicon through hole, or described via metal layer is be distributed in the discrete metal wire of at least two of described silicon through hole at least two sidewall surfaces.
As mentioned above, silicon adapter plate structure of the present invention and wafer level manufacture method thereof, have following beneficial effect: compared with the silicon through hole keyset made based on dry etching of main flow, the present invention has the advantage of low cost, high reliability; The silicon through hole that the present invention is based on wet etching making has sloped sidewall, be conducive to forming high-quality through hole insulating barrier on through-silicon via sidewall surface, and be conducive in through hole, form graphical via metal layer, thus a hole multiple line structure can be formed, improve interconnection line density; In silicon keyset of the present invention, there is at least one pair of groove structure, the thickness of silicon through hole can be reduced, be conducive to reducing aperture, improve silicon via densities, simultaneously can embedding chip in groove, thus reduce the thickness of three-dimensional stacked rear whole package module, realize the system integration of more high density, small size; The wafer level manufacture method of silicon adapter plate structure of the present invention also has the advantage that technology difficulty is low, be suitable for suitability for industrialized production.
Accompanying drawing explanation
Fig. 1 is shown as the schematic diagram of silicon wafer in the wafer level manufacture method of silicon adapter plate structure of the present invention.
Fig. 2 is shown as the schematic diagram forming graphical first photoresist layer in the wafer level manufacture method of silicon adapter plate structure of the present invention.
Fig. 3 is shown as the schematic diagram forming groove in the wafer level manufacture method of silicon adapter plate structure of the present invention.
Fig. 4 is shown as the schematic diagram forming graphical second photoresist layer in the wafer level manufacture method of silicon adapter plate structure of the present invention.
Fig. 5 is shown as the schematic diagram forming silicon through hole in the wafer level manufacture method of silicon adapter plate structure of the present invention.
Fig. 6 is shown as the schematic diagram forming through hole dielectric layer in the wafer level manufacture method of silicon adapter plate structure of the present invention.
Fig. 7 is shown as the schematic diagram of silicon adapter plate structure of the present invention.
Fig. 8 is shown as in the wafer level manufacture method of silicon adapter plate structure of the present invention the schematic diagram forming hole one line structure.
Fig. 9 is shown as in the wafer level manufacture method of silicon adapter plate structure of the present invention the schematic diagram forming hole four line structure.
Figure 10 is shown as in the wafer level manufacture method of silicon adapter plate structure of the present invention the schematic diagram forming hole eight line structure.
Figure 11 is shown as in the wafer level manufacture method of silicon adapter plate structure of the present invention the schematic diagram forming another kind of hole eight line structure.
Figure 12 is shown as the three-dimensional stacked encapsulating structure schematic diagram of silicon adapter plate structure of the present invention and chip.
Figure 13 is shown as the system-in-package structure schematic diagram of silicon adapter plate structure of the present invention and chip and pcb board.
Element numbers explanation
1 silicon wafer
2 first silicon dioxide passivation layer
3 graphical first photoresist layers
4 grooves
5 bottom portion of groove
6 second silicon dioxide passivation layer
7 graphical second photoresist layers
8 silicon through holes
9 through hole dielectric layers
10 groove dielectric layers
11 via metal layers
12 metals reroute layer
13 metal pads
14 first chips
15 second chips
16 lead-in wires
17 solder bumps
18 the 3rd chips
19 ball grid array
20 pcb boards
Embodiment
Below by way of specific instantiation, embodiments of the present invention are described, those skilled in the art the content disclosed by this specification can understand other advantages of the present invention and effect easily.The present invention can also be implemented or be applied by embodiments different in addition, and the every details in this specification also can based on different viewpoints and application, carries out various modification or change not deviating under spirit of the present invention.
Refer to Fig. 1 to Figure 13.It should be noted that, the diagram provided in the present embodiment only illustrates basic conception of the present invention in a schematic way, then only the assembly relevant with the present invention is shown in graphic but not component count, shape and size when implementing according to reality is drawn, it is actual when implementing, and the kenel of each assembly, quantity and ratio can be a kind of change arbitrarily, and its assembly layout kenel also may be more complicated.
The invention provides a kind of wafer level manufacture method of silicon adapter plate structure, at least comprise the following steps:
S1: provide a silicon wafer, adopts wet etching to form at least one pair of groove distributed up and down in described silicon wafer front and the back side; A pair groove shares bottom portion of groove;
S2: adopt wet etching to form at least one silicon through hole in described bottom portion of groove; Described silicon through hole is formed by connecting by laterally zygomorphic upper through hole and lower through-hole; Described upper through hole and lower through-hole have sloped sidewall;
S3: form through hole dielectric layer in the sidewall surfaces of described silicon through hole;
S4: form via metal layer at described through hole dielectric layer surface;
S5: last scribing forms independently silicon keyset.
First refer to Fig. 1 to Fig. 3, perform step S1: provide a silicon wafer 1, adopt wet etching to form at least one pair of groove 4 distributed up and down in described silicon wafer front and the back side; A pair groove shares bottom portion of groove 5.
Concrete, described silicon wafer 1 preferably adopts (100) silicon chip of twin polishing, and Fig. 1 is shown as the structural representation of described silicon wafer 1.
Concrete, first described silicon wafer 1 is carried out standard cleaning, then by the silicon wafer 1 Double-side hot oxidation after cleaning, the first silicon dioxide passivation layer 2 is formed in the front of described silicon wafer 1 and the back side, spin coating first photoresist layer in described first silicon dioxide passivation layer 2 again, and carry out exposing and developing, obtain graphical first photoresist layer 3, as shown in Figure 2.
Then by the Graphic transitions on described graphical first photoresist layer 3 in described first silicon dioxide passivation layer 2, obtain the first etching mask (not giving diagram herein) for the formation of described groove 5.Then remove described graphical first photoresist layer 3 again, and silicon wafer is put into the anisotropic etchant of silicon, corrode and take out to certain depth, thus making obtains described groove 4.Finally remove described first etching mask, the groove structure obtained as shown in Figure 3.
It is pointed out that a pair groove can be symmetrical up and down, namely center is symmetrical and measure-alike, and bottom portion of groove overlaps completely; In addition, the groove in front and the groove center position at the back side can be asymmetric, and size also can be different, and bottom portion of groove only partially overlaps, and wherein, the bottom portion of groove part shared is for the formation of silicon through hole.The present embodiment is depicted as a pair groove situation symmetrical up and down.
Concrete, described first photoresist layer adopts model to be the photoresist of LC100A, its thickness is preferably 1.7 microns, wherein, the front baking technique of first surface photoresist is carried out on hot plate or in baking oven, and the front baking technique of second photoresist can only be carried out in baking oven, if this is because on hot plate front baking, the photoetching offset plate figure of first surface will be destroyed.In photoetching process, during exposure, adopt the first optical mask plate, and is alignd in the <110> crystal orientation of the graphic limit of described first optical mask plate with described (100) crystal face silicon chip.After development, the post bake temperature and time of first surface photoresist is respectively 135 DEG C and 10 minutes, and the post bake temperature and time of second photoresist is respectively 135 DEG C and 30 minutes.Be only example herein, the parameters such as photoresist thickness, post bake temperature and time can adjust as required, and this is the common practise of this area, should too not limit the scope of the invention.
Concrete, Graphic transitions on described graphical first photoresist layer 3 to described first silicon dioxide passivation layer 2 will obtain the method for the first etching mask for the formation of described groove 5, BOE corrosive liquid (HF:NH4F:H2O) can be adopted, also can adopt reactive ion etching (RIE).In actual production process, a kind of wherein method can be selected according to the speed of the requirement of dimension of picture precision, reaction rate and cost requirement.Be described for BOE corrosion in the present embodiment.Before adopting BOE corrosion, silicon wafer need etch one minute in plasma ashing system (being commonly called as bottoming film), to remove the photoresist that photoetching window place remains, and then corrode a period of time and obtain described first etching mask.Corrosion temperature and etching time are determined according to the thickness of described first silicon dioxide passivation layer 2, and the thickness of the first silicon dioxide passivation layer 2 described in the present embodiment is for 2 microns, and at 35 DEG C of temperature, corrosion required time is about 10 minutes.
Concrete, the method removing described graphical first photoresist layer 3 preferably boils 10 minutes in the concentrated sulfuric acid of 120 DEG C, and can certainly adopt other method, this is the common practise of this area.Described anisotropic etchant is preferably KOH corrosive liquid, this solution 50 DEG C, concentration is 40%(wt.) 10-12.5 micro-m/h is about to the corrosion rate of (100) crystal face under condition, and there is good corrosion surface pattern.In the present embodiment, the recess etch degree of depth is preferably 90 microns, and in actual applications, the chip size that can carry out as required interconnecting adjusts depth of groove.Described groove 4 has sloped sidewall, longitudinal section is trapezoidal, (100) crystal face silicon chip is adopted in the present embodiment, and photoetching photomask plate graphic limit is alignd with the <110> crystal orientation of (100) crystal face silicon chip, therefore the sidewall of the final groove 4 formed is { the 111} crystal face of silicon, being 54.7 degree with bottom surface (100) crystal face angle, is namely 54.7 degree with the angle of described bottom portion of groove place plane.
Concrete, remove described first etching mask and preferably adopt BOE solution corrosion.
Then refer to Fig. 4 and Fig. 5, perform step S2: adopt wet etching to form at least one silicon through hole 8 at described bottom portion of groove 5; Described silicon through hole is formed by connecting by laterally zygomorphic upper through hole and lower through-hole; Described upper through hole and lower through-hole have sloped sidewall.
Concrete, first silicon wafer surface is oxidized again, forms the second silicon dioxide passivation layer 6, then in described second silicon dioxide passivation layer 6 at front and the back side, spray photoresist and graphical, form patterned second photoresist layer 7, as shown in Figure 4.Then by the Graphic transitions on described graphical second photoresist layer 7 in described second silicon dioxide passivation layer 6, obtain the second etching mask (not giving diagram herein) for the formation of described silicon through hole 8.Then remove described graphical second photoresist layer 7 again, and silicon wafer is put into the anisotropic etchant of silicon, rear taking-up is worn in silicon wafer corruption, thus making obtains described silicon through hole 8.Finally remove described second etching mask, the through-silicon via structure obtained as shown in Figure 5.
Concrete, the cross section of described silicon through hole 8 is rectangle or square.When photoetching forms described second etching mask, is alignd in the <110> crystal orientation of the graphic limit of the second optical mask plate with described (100) crystal face silicon chip.Adopt described second etching mask to be formed in the process of described silicon through hole 8, silicon wafer front and the back side start corrosion simultaneously, and the silicon through hole 8 obtained is formed by connecting by laterally zygomorphic upper through hole and lower through-hole; Described upper through hole and lower through-hole have sloped sidewall.Wherein, the longitudinal section of described upper through hole is inverted trapezoidal; The longitudinal section of described lower through-hole is trapezoidal, and described silicon through hole 8 presents large, the middle little design feature in two ends.Owing to aliging in the <110> crystal orientation of graphic limit with described (100) crystal face silicon chip, therefore the sidewall of described upper through hole and the angle of described bottom portion of groove place plane are 54.7 degree, and the sidewall of described lower through-hole and the angle of described bottom portion of groove place plane are also 54.7 degree.
Concrete, it is EVG101 spraying colloid system that described second silicon dioxide passivation layer 6 at front and the back side sprays the instrument that photoresist uses, this system can realize the coating technique of three-dimensional structure, and to surface and the sidewall realization covering comprehensively of three-dimensional structure, glue is thick simultaneously reaches ten microns.Implement, in spray-bonding craft and exposure technology subsequently, because of the existence of silicon wafer upper groove structure, disk to be attached on a slide glass, to realize disk fixing on sucker.The concrete steps forming described graphical second photoresist layer 7 are:
1) high temperature gummed tape is used to be attached to by silicon wafer on a slide glass;
2) spray photoresist in silicon wafer one side, photoresist realizes comprehensive uniform fold to described second silicon dioxide passivation layer 6;
3) silicon wafer is separated with slide glass, and described silicon wafer is put into the baking oven front baking 8 minutes of 120 DEG C;
4) high temperature gummed tape is used to be attached to conversely on slide glass by silicon wafer;
5) on silicon wafer another side, photoresist is sprayed;
6) silicon wafer is separated with slide glass, and silicon wafer is put into the baking oven front baking 10 minutes of 120 DEG C;
7) after silicon wafer cooling, reuse high temperature gummed tape and silicon wafer is attached on slide glass, and to one side exposure;
8) used by silicon wafer high temperature gummed tape to paste slide glass conversely, another side is exposed;
9) developed together in silicon wafer front and the back side, then wash by water, dry, obtain patterned second photoresist layer 7.
Concrete, Graphic transitions on described graphical second photoresist layer 7 to described second silicon dioxide passivation layer 6 will obtain the method for the second etching mask for the formation of described silicon through hole 8, BOE corrosive liquid (HF:NH4F:H2O) can be adopted, also can adopt reactive ion etching (RIE).The method removing described graphical second photoresist layer 7 preferably boils 10 minutes in the concentrated sulfuric acid of 120 DEG C.The anisotropic etchant of described silicon is KOH solution, in this enforcement, preferably adopts 40%(wt.) KOH corrosive liquid, the silicon through hole 8 obtained has good surface topography.After forming silicon through hole, remove described second etching mask and preferably adopt BOE solution corrosion.
Then refer to Fig. 6, perform step S3: form through hole dielectric layer 9 in the sidewall surfaces of described silicon through hole 8.
Concrete, form described through hole dielectric layer 9 by thermal oxidation process, when forming described through hole dielectric layer 9, simultaneously at described groove surfaces and around formation groove dielectric layer 10.The thickness range of described through hole dielectric layer 9 and described groove dielectric layer 10 is 1 ~ 2 micron.Described through hole dielectric layer 9 is for the insulation of described silicon through hole 8.
Refer to Fig. 7 again, perform step S4: form via metal layer 11 on described through hole dielectric layer 9 surface.
Concrete, when forming described via metal layer 10, forming metal simultaneously on described groove dielectric layer 9 surface and to reroute layer 12 and metal pad 13.Formation method is: at silicon wafer tow sides splash-proofing sputtering metal layer, carry out glue spraying photoetching simultaneously, and litho pattern is transferred to described metal level, thus form described via metal layer 11, metal reroutes layer 12 and metal pad 13.
Concrete, stating via metal layer 11 is the metal level covering full described silicon through hole four sidewall surfaces, or described via metal layer 11 is for being distributed at least one wires of described one of them sidewall surfaces of silicon through hole, or described via metal layer 11 is be distributed in the discrete metal wire of at least two of described silicon through hole at least two sidewall surfaces.In other words, hole one line structure or a hole multiple line structure can namely be formed.Refer to Fig. 8 to Figure 11, wherein, Fig. 8 is shown as hole one line structure, as shown in Figure 8, via metal layer 11 covers full described silicon through hole four sidewall surfaces, and the layer 12 that reroutes of the metal outside silicon through hole contacts with described via metal layer 11 for wire, forms hole one line structure; In another embodiment, described via metal layer 11 also can for being distributed in a wires of described one of them sidewall surfaces of silicon through hole, and just for hole one line structure, this kind of technique is comparatively complicated, is unfavorable for saving cost.Fig. 9 is shown as hole four line structure, Figure 10 and Figure 11 is shown as hole eight line structure.Be only example herein, can also carry out more evolutions, as hole six line, ten lines etc., and the number that distributes on different lateral can change, and should too not limit the scope of the invention herein.
Concrete, described metal level comprises TiW layer and is formed and Cu layer on it, and wherein, TiW layer is as adhesion layer and diffusion impervious layer, and Cu layer is as conductive functional layers.In the present embodiment, the thickness of TiW layer/Cu layer is preferably 50 nanometer/300 nanometers.The instrument that described metal level sprays photoresist use is EVG101 spraying colloid system, implements, in spray-bonding craft and exposure technology subsequently, to be attached to by silicon wafer on slide glass, to realize silicon wafer fixing on sucker.The concrete steps be transferred to by litho pattern on described metal level are:
1) silicon wafer is put into plasma ashing system etching one minute, to remove the residual photoresist in photoetching window place;
2) silicon wafer is put into two-sided electroplating bath, carry out two-sided Cu electroplating technology;
3), after having electroplated, use acetone soln to be soaked by photoresist layer and remove;
4) use plasma etching (IBE) technique successively to silicon wafer front and back-etching, to remove metal seed layer.
Finally perform step S5: scribing forms independently silicon keyset.
So far, the wafer level completing silicon adapter plate structure makes.
The silicon through hole made based on dry etching of the wafer level manufacture method of silicon adapter plate structure of the present invention and main flow is transferred compared with class, has the advantage of low cost, high reliability; And based on the through-silicon via structure that wet etching makes in the present invention, there is sloped sidewall, be conducive to the insulating barrier of making silicon through hole and form patterned via metal layer, realizing a hole multi-thread, improve interconnection density; And manufacture method technology difficulty of the present invention is low, be applicable to suitability for industrialized production.
The present invention also provides a kind of silicon adapter plate structure, refers to Fig. 7, is shown as the generalized section of described silicon adapter plate structure, comprises:
Silicon wafer 1;
At least one pair of groove 4 distributed up and down, is formed at described silicon wafer 1 front and the back side respectively; A pair groove shares bottom portion of groove 5;
Be formed at least one the silicon through hole 8 in described bottom portion of groove 5;
Be formed at the through hole dielectric layer 9 of described silicon through hole 8 sidewall surfaces;
And be formed at the via metal layer 11 on described through hole dielectric layer 9 surface;
Described silicon through hole 8 is formed by connecting by laterally zygomorphic upper through hole and lower through-hole; Described upper through hole and lower through-hole have sloped sidewall.
Concrete, the cross section of described silicon through hole 8 is square or rectangle, and described silicon through hole 8 presents large, the middle little design feature in two ends, and the longitudinal section of described upper through hole is inverted trapezoidal, and the longitudinal section of described lower through-hole is trapezoidal.The sidewall of described upper through hole and the angle of described bottom portion of groove place plane are 54.7 degree, and the sidewall of described lower through-hole and the angle of described bottom portion of groove place plane are 54.7 degree.
Concrete, stating via metal layer is the metal level covering full described silicon through hole four sidewall surfaces, or described via metal layer is for being distributed at least one wires of described one of them sidewall surfaces of silicon through hole, or described via metal layer is be distributed in the discrete metal wire of at least two of described silicon through hole at least two sidewall surfaces, forms hole one line or a hole multiple line structure.Described groove surfaces and around have groove dielectric layer 10, described groove dielectric layer is formed with metal and reroutes layer 12 and metal pad 13.
In order to show the beneficial effect of silicon adapter plate structure of the present invention, the three-dimensional stacking structure figure of described silicon adapter plate structure and chip is additionally provided in the present embodiment, as shown in figure 12, and described silicon adapter plate structure and chip and pcb board integrated after structure chart, as shown in figure 13.
First Figure 12 is referred to, be shown as the three-dimensional stacked encapsulation (3D StackedPackage) of described silicon adapter plate structure and chip, as shown in the figure, first chip 14 and the second chip 15 are fixed in the groove of described silicon adapter plate structure, wherein, described first chip 14 and described silicon adapter plate structure carry out the connection of electricity by lead-in wire 16, use Wire Bonding Technology (Wire Bonding); Described second chip 15 carries out electricity with described silicon keyset by solder bump 17 and is connected, and uses flip chip bonding (Flip Chip) technology.
In silicon adapter plate structure of the present invention, the existence of described groove 4 makes the degree of depth of the silicon through hole 8 made reduce, and its respective transversal size also reduces thereupon, significantly can improve packaging density; Meanwhile, this configuration reduces the thickness of three-dimensional stacked rear whole package module; And a hole multiple line structure can improve interconnection line density.Whole three-dimensional stacked package module achieve higher density the system integration, reduce system in package volume and improve systematic function; Meanwhile, whole package module technical process is simple, cost is lower.
Refer to Figure 13 again, display be the system in package (System InPackage, SIP) of described silicon keyset and chip and pcb board.Described first chip 14 also can adopt the mode of flip chip bonding and described silicon keyset to interconnect; Meanwhile, described first chip 14 is utilized to be embedded in feature in described groove 4, can also stacking 3rd chip 18 again on it, such that system is compacter, packaging density is higher.Further, whole stack module can be connected with pcb board 20 by ball grid array 19.
In sum, silicon adapter plate structure of the present invention and wafer level manufacture method thereof have the advantage of low cost, high reliability; The silicon through hole that the present invention is based on wet etching making has sloped sidewall, be conducive to forming high-quality through hole insulating barrier on through-silicon via sidewall surface, and be conducive in through hole, form figure via metal layer, thus a hole multiple line structure can be formed, improve interconnection line density; In silicon keyset of the present invention, there is at least one pair of groove structure, the thickness of silicon through hole can be reduced, be conducive to reducing aperture, improve silicon via densities, simultaneously can embedding chip in groove, thus reduce the thickness of three-dimensional stacked rear whole package module, realize the more highdensity system integration; The manufacture method of silicon adapter plate structure of the present invention also has the advantage that technology difficulty is low, be suitable for suitability for industrialized production.So the present invention effectively overcomes various shortcoming of the prior art and tool high industrial utilization.
Above-described embodiment is illustrative principle of the present invention and effect thereof only, but not for limiting the present invention.Any person skilled in the art scholar all without prejudice under spirit of the present invention and category, can modify above-described embodiment or changes.Therefore, such as have in art usually know the knowledgeable do not depart from complete under disclosed spirit and technological thought all equivalence modify or change, must be contained by claim of the present invention.
Claims (10)
1. a wafer level manufacture method for silicon adapter plate structure, is characterized in that, at least comprise the following steps:
S1: provide a silicon wafer, adopts wet etching to form at least one pair of groove distributed up and down in described silicon wafer front and the back side; A pair groove shares bottom portion of groove;
S2: adopt wet etching to form at least one silicon through hole in described bottom portion of groove; Described silicon through hole is formed by connecting by laterally zygomorphic upper through hole and lower through-hole; Described upper through hole and lower through-hole have sloped sidewall;
S3: form through hole dielectric layer in the sidewall surfaces of described silicon through hole;
S4: form via metal layer at described through hole dielectric layer surface; Described via metal layer is for being distributed at least one wires of described one of them sidewall surfaces of silicon through hole, or described via metal layer is be distributed in the discrete metal wire of at least two of described silicon through hole at least two sidewall surfaces;
S5: last scribing forms independently silicon keyset.
2. the wafer level manufacture method of silicon adapter plate structure according to claim 1, is characterized in that: the longitudinal section of described upper through hole is inverted trapezoidal; The longitudinal section of described lower through-hole is trapezoidal.
3. the wafer level manufacture method of silicon adapter plate structure according to claim 2, it is characterized in that: the sidewall of described upper through hole and the angle of described bottom portion of groove place plane are 54.7 degree, the sidewall of described lower through-hole and the angle of described bottom portion of groove place plane are 54.7 degree.
4. the wafer level manufacture method of silicon adapter plate structure according to claim 1, is characterized in that: the cross section of described silicon through hole is rectangle or square.
5. the wafer level manufacture method of silicon adapter plate structure according to claim 1, is characterized in that: described silicon wafer is (100) crystal face silicon chip of twin polishing.
6. the wafer level manufacture method of silicon adapter plate structure according to claim 5, it is characterized in that: adopt the first etching mask to form described groove, when photoetching forms described first etching mask, is alignd in the <110> crystal orientation of the graphic limit of the first optical mask plate with described (100) crystal face silicon chip; Adopt the second etching mask to form described silicon through hole, when photoetching forms described second etching mask, is alignd in the <110> crystal orientation of the graphic limit of the second optical mask plate with described (100) crystal face silicon chip.
7. the wafer level manufacture method of silicon adapter plate structure according to claim 1, is characterized in that: in described step S3, when forming described through hole dielectric layer, forms groove dielectric layer in described groove surfaces simultaneously; In described step S4, when forming via metal layer, simultaneously forming metal at described groove dielectric layer surface and to reroute layer and metal pad.
8. the wafer level manufacture method of silicon adapter plate structure according to claim 1, it is characterized in that: in described step S1 and step S2, described wet etching all adopts the anisotropic etchant of silicon.
9. the wafer level manufacture method of silicon adapter plate structure according to claim 1, is characterized in that: described groove has sloped sidewall.
10. a silicon adapter plate structure, comprising:
Silicon wafer;
At least one pair of groove distributed up and down, is formed at described silicon wafer front and the back side respectively; A pair groove shares bottom portion of groove;
Be formed at least one the silicon through hole in described bottom portion of groove;
Be formed at the through hole dielectric layer on described through-silicon via sidewall surface;
And be formed at the via metal layer of described through hole dielectric layer surface;
It is characterized in that:
Described silicon through hole is formed by connecting by laterally zygomorphic upper through hole and lower through-hole; Described upper through hole and lower through-hole have sloped sidewall; Described via metal layer is for being distributed at least one wires of described one of them sidewall surfaces of silicon through hole, or described via metal layer is be distributed in the discrete metal wire of at least two of described silicon through hole at least two sidewall surfaces.
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| CN112201655B (en) * | 2020-09-10 | 2022-04-29 | 复旦大学 | Three-dimensional integrated structure of nano capacitor and manufacturing method thereof |
| CN112151537B (en) * | 2020-09-10 | 2022-04-29 | 复旦大学 | High-energy-density nano-capacitor three-dimensional integrated structure and preparation method thereof |
| CN112151538B (en) * | 2020-09-10 | 2022-04-29 | 复旦大学 | Three-dimensional integrated structure of nano capacitor and manufacturing method thereof |
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