CN103513207A - Method for channel mapping of matrix switch in integrated circuit testing system calibration device - Google Patents
Method for channel mapping of matrix switch in integrated circuit testing system calibration device Download PDFInfo
- Publication number
- CN103513207A CN103513207A CN201210221101.2A CN201210221101A CN103513207A CN 103513207 A CN103513207 A CN 103513207A CN 201210221101 A CN201210221101 A CN 201210221101A CN 103513207 A CN103513207 A CN 103513207A
- Authority
- CN
- China
- Prior art keywords
- sequence number
- matrix switch
- mapping table
- physics
- logic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Abstract
A method for channel mapping of a matrix switch in an integrated circuit testing system calibration device comprises the following steps: first, a switchover rule of the matrix switch is layered and divided into a logic sequence number layer, a physical sequence number layer and a matrix switch sequence number layer; second, a mapping table from logic sequence numbers to physical sequence numbers is defined, and channel sequence numbers of calibrated resources are mapped to external wiring sequence numbers of the matrix switch one by one; third, a mapping table from the physical sequence numbers to matrix switch sequence numbers is defined; fourth, the switchover rule of the matrix switch is obtained by converting the mapping tables; fifth, the purpose of changing the switchover rule of the matrix switch can be achieved by editing the mapping table from the logic sequence numbers to the physical sequence numbers and the mapping table from the physical sequence numbers to the matrix switch sequence numbers. The method for channel mapping of the matrix switch in the integrated circuit testing system calibration device has the advantages of being clear in structure and significance, thereby enhancing the universality of the integrated circuit testing system calibration device.
Description
Technical field
The present invention relates to microelectronics test and field of measuring techniques, specifically a kind of method for the mapping of integrated circuit test system calibrating installation matrix switch passage.
Background technology
No matter integrated circuit test system belongs to numeral, simulation or mixed type, all comprises some test channel.Traditional calibrating mode cannot complete the automatic calibration to full tunnel, only can calibrate by pure manual mode, due to many defects of manual calibration, in actual alignment work, can not effectively complete the calibration to test macro full tunnel.Newly-built integrated circuit test system calibrating installation, can realize the automatic calibration to test macro full tunnel at present.The hardware device of integrated circuit test system calibrating installation is Cover matrix switches all generally, automatic switchover when hyperchannel is calibrated to realize.
Yet calibrating installation is when to the use of matrix switch, there are the following problems: when (1) carries out adaptation to different integrated circuit test systems, the channel definition that is calibrated resource is inconsistent; (2) some matrix switch passage is because the reasons such as damage need to be skipped; (3) changed the matrix switch of new model, the mode of connection and original matrix switch are inconsistent.There is above-mentioned any situation, all need to utilize matrix switch driver to change its switching law.
Because integrated circuit test system model is many, it is many to be calibrated resource type, matrix switch belongs to again easy loss equipment, causes matrix switch switching law to need frequent change.And integrated circuit test system number of channels many (digital channel can reach 512), the number of channels more (more than being generally 4 * 40 scales) that matrix switch need to use, causes again the workload of each matrix switch switching law change all very large.In addition, the different resource of the even same test macro of different test macros, the definition of its passage is also irregular, and the change of switching law must manually complete in dependence, and this has greatly limited the versatility of calibrating installation to integrated circuit test system.
Summary of the invention
The object of the invention is for the problems referred to above, matrix switch passage mapping method in a kind of integrated circuit test system calibrating installation is proposed: by the switching law layering of matrix switch, and the passage that is calibrated resource is successively mapped to matrix switch passage, and then obtain the matrix switch switching law through passage mapping.
Matrix switch passage mapping method in a kind of integrated circuit test system calibrating installation of the present invention, its step is as follows:
The first step: by the switching law layering of matrix switch, be divided into logic sequence number layer, physics sequence number layer, matrix switch sequence number layer, wherein, logic sequence number layer consists of logic sequence number, correspondence is calibrated the channel position of resource, and physics sequence number layer consists of physics sequence number, the sequence number of homography switch external wiring, matrix switch sequence number layer consists of matrix switch sequence number, the sequence number of homography switch passage;
Second step: definition logic sequence number, to the mapping table of physics sequence number, maps to the channel position that is calibrated resource the sequence number of matrix switch external cabling item by item, this mapping table is with to be calibrated resource corresponding, uncorrelated with the model of matrix switch;
The 3rd step: definition physics sequence number, to the mapping table of matrix switch sequence number, maps to matrix switch channel position item by item by the sequence number of matrix switch external cabling, this mapping table is corresponding with model and the configuration of matrix switch, with to be calibrated resource uncorrelated;
The 4th step: matrix switch switching law is converted to by above-mentioned mapping table, first by logic sequence number, to the mapping table of physics sequence number, be converted to the sequence of physics sequence number, using this sequence as input, by physics sequence number, to the mapping table of matrix switch sequence number, once change, the result of conversion is exactly the switching law of matrix switch again;
The 5th step: the mapping table by editorial logic sequence number to the mapping table of physics sequence number, physics sequence number to matrix switch sequence number, can realize the object of change matrix switch switching law.
In a kind of integrated circuit test system calibrating installation of the present invention, the advantage of matrix switch passage mapping method is that the switching law of matrix switch is divided into 3 layers, and change by 2 mapping tables, every one deck of switching law has clear and definite physical significance, compare with existing matrix switch switching law, clear in structure, meaning are clear and definite.In the time need to changing the switching law of matrix switch, only need to according to circumstances edit the content of a certain layering, strengthen the versatility of calibrating installation, there is the features such as reliable, maintenance cost is low, be particularly suitable for universal integrated circuit test system calibrating installation.Actual measurement shows, apply mapping method of the present invention a kind of switching law that is calibrated resource 50 passage scales is changed and can with interior, be completed at 5 minutes, and the change of using the driver of matrix switch to carry out same scale at least needs 60 minutes.
Accompanying drawing explanation
Fig. 1 is matrix switch passage mapping method fundamental diagram.
Fig. 2 is matrix switch passage mapping usage schematic diagram.
Fig. 3 is the passage mapping relations detailed annotation figure that embodiment is corresponding.
Embodiment
Below in conjunction with embodiment, the present invention is described in further detail, but embodiments of the present invention are not limited to this.
The integrated circuit test system calibrating installation of 50 calibration ports of take describes as example:
According to the example of Fig. 2, integrated circuit test system calibrating installation for 50 calibration ports, select the matrix switch of 4 * 92 scales, 50 calibration ports are drawn by the accurate IDC plug of 50 road sign, between 50 road IDC plugs and matrix switch, by 50 road winding displacements, connect, 50 calibration ports have taken 50 row of matrix switch, and the equipment of calibrating installation is connected with all the other row, column of matrix switch.
With reference to Fig. 1, the mapping of the passage of the present embodiment is divided into following a few step:
The first step is by the switching law layering of matrix switch, the result of switching law layering is with reference to Fig. 3, logic sequence number layer correspondence is calibrated the channel position of resource, the i.e. sequence number of 25 GND and passage 1 ~ passage 25, the sequence number of physics sequence number floor homography switch external 50 road winding displacements, in this example, physics sequence number can represent by the IDC50 port sequence number being connected with winding displacement, the sequence number of the 1st row the ~ the 92 row of matrix switch sequence number layer homography switch.
Second step definition logic sequence number is to the mapping table of physics sequence number, this mapping table consists of 3 column datas of logic sequence number and physics sequence number at Fig. 3, wherein logic sequence number is divided into again channel logic sequence number and GND logic sequence number, the respectively passage of corresponding integrated circuit test system and ground, will be calibrated 25 GND of resource and the numeric order of passage 1 ~ passage 25 and map to the sequence number of 50 road winding displacements according to this mapping table.
The 3rd step definition physics sequence number is to the mapping table of matrix switch sequence number, this mapping table consists of 2 column datas of physics sequence number and matrix switch sequence number at Fig. 3, the sequence number of physics sequence number homography switch external 50 road winding displacements, the sequence number of matrix switch sequence number homography switch 50 row, maps to according to the numeric order of this mapping table Jiang50 road winding displacement the sequence number that matrix switch 50 is listed as.
The 4th step is when needs switch matrix switch, take passage 25 as example, first the logic sequence number that is passage according to the channel position that is calibrated resource is carried out first step conversion, conversion according to being that logic sequence number is to physics sequence number mapping table, according to the logic sequence number of Fig. 3 passage 25, be 25, physics sequence number is 50, using the physics sequence number being converted to as input, according to physics sequence number to matrix switch sequence number mapping table, carry out second step conversion, according to the matrix switch sequence number of this passage of Fig. 3, be 92, the result of this step conversion is exactly the sequence number that needs the matrix switch row of switching, be the row 92 of matrix switch.
The 5th step is when needs are changed matrix switch switching law, suppose that the matrix switch in this example changes, still take passage 25 as example, after changing, IDC50 50 tunnels are connected with the row 50 of matrix switch, in Fig. 3, the matrix switch sequence number of passage 25 need to change 50 into by 92, is about to physics sequence number to the matrix switch sequence number of passage 25 in the mapping table of matrix switch sequence number and changes 50 into from 92.
The present invention is not limited to above embodiment, according to the difference that is calibrated resource, matrix switch external wiring pattern, matrix switch model, can organize a plurality of embodiment.
Claims (1)
1. a matrix switch passage mapping method in integrated circuit test system calibrating installation, is characterized in that: comprise the following steps:
The first step: by the switching law layering of matrix switch, be divided into logic sequence number layer, physics sequence number layer, matrix switch sequence number layer, wherein, logic sequence number layer consists of logic sequence number, correspondence is calibrated the channel position of resource, and physics sequence number layer consists of physics sequence number, the sequence number of homography switch external wiring, matrix switch sequence number layer consists of matrix switch sequence number, the sequence number of homography switch passage;
Second step: definition logic sequence number, to the mapping table of physics sequence number, maps to the channel position that is calibrated resource the sequence number of matrix switch external cabling item by item, this mapping table is with to be calibrated resource corresponding, uncorrelated with the model of matrix switch;
The 3rd step: definition physics sequence number, to the mapping table of matrix switch sequence number, maps to matrix switch channel position item by item by the sequence number of matrix switch external cabling, this mapping table is corresponding with model and the configuration of matrix switch, with to be calibrated resource uncorrelated;
The 4th step: matrix switch switching law is converted to by above-mentioned mapping table, first by logic sequence number, to the mapping table of physics sequence number, be converted to the sequence of physics sequence number, using this sequence as input, by physics sequence number, to the mapping table of matrix switch sequence number, once change, the result of conversion is exactly the switching law of matrix switch again;
The 5th step: the mapping table by editorial logic sequence number to the mapping table of physics sequence number, physics sequence number to matrix switch sequence number, can realize the object of change matrix switch switching law.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210221101.2A CN103513207B (en) | 2012-06-29 | 2012-06-29 | A kind of method mapped for matrix switch passage in integrated circuit test system calibrating installation |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210221101.2A CN103513207B (en) | 2012-06-29 | 2012-06-29 | A kind of method mapped for matrix switch passage in integrated circuit test system calibrating installation |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103513207A true CN103513207A (en) | 2014-01-15 |
| CN103513207B CN103513207B (en) | 2016-02-17 |
Family
ID=49896230
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210221101.2A Active CN103513207B (en) | 2012-06-29 | 2012-06-29 | A kind of method mapped for matrix switch passage in integrated circuit test system calibrating installation |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103513207B (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006060467A (en) * | 2004-08-19 | 2006-03-02 | Nec Corp | Digital modem |
| CN101866154A (en) * | 2010-05-11 | 2010-10-20 | 浙江大学 | I/O port mapping method based on simplifying relay matrix |
| CN101958004A (en) * | 2009-07-14 | 2011-01-26 | 索尼公司 | Image processing apparatus and image processing method |
| US8131975B1 (en) * | 2008-07-07 | 2012-03-06 | Ovics | Matrix processor initialization systems and methods |
-
2012
- 2012-06-29 CN CN201210221101.2A patent/CN103513207B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006060467A (en) * | 2004-08-19 | 2006-03-02 | Nec Corp | Digital modem |
| US8131975B1 (en) * | 2008-07-07 | 2012-03-06 | Ovics | Matrix processor initialization systems and methods |
| CN101958004A (en) * | 2009-07-14 | 2011-01-26 | 索尼公司 | Image processing apparatus and image processing method |
| CN101866154A (en) * | 2010-05-11 | 2010-10-20 | 浙江大学 | I/O port mapping method based on simplifying relay matrix |
Non-Patent Citations (1)
| Title |
|---|
| 郭杰翔等: "自动测试系统测试适配器通用端口的自动设计", 《测试技术学报》 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103513207B (en) | 2016-02-17 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102169157B (en) | Method for constructing multi-channel matrix switch parallel measurement cable network | |
| CN202694136U (en) | Multichannel thermal control system testing equipment | |
| CN201425614Y (en) | Multicore-cable parameter tester | |
| CN104237977B (en) | A kind of automatic weather station fault processing system | |
| CN204480040U (en) | The test macro of fuel-cell vehicle entire car controller | |
| CN104614668A (en) | Circuit board testing system | |
| CN202502407U (en) | Avionics equipment testing device | |
| CN102854877A (en) | Function test system and test method of automobile body control module | |
| CN106546962A (en) | The intrinsic time delay automatic testing equipment of satellite transponder and method of testing | |
| CN103675647A (en) | Calibration device and method based on integrated circuit standard sample | |
| CN105388880A (en) | Method for connecting input/output interface of testing device equipped for testing control unit | |
| CN104991214B (en) | Digital integrated electronic circuit DC parameter standard reproducing method and standard set-up | |
| CN106526397A (en) | Automatic intelligent checking method for intelligent substation | |
| CN203053611U (en) | Transformer temperature check and test device | |
| CN103513207B (en) | A kind of method mapped for matrix switch passage in integrated circuit test system calibrating installation | |
| CN105445818A (en) | Automatic meteorological station data acquisition device checking system and checking method thereof | |
| CN104237642A (en) | Automatic hall resistivity testing method | |
| CN203444053U (en) | Integrated network transformer scan test device | |
| CN102169151A (en) | Cable network parallel test method | |
| CN202854605U (en) | Function test system of automotive body control model | |
| CN203178460U (en) | Traceability device used for electronic mutual inductor output calibration instrument | |
| CN104897965A (en) | Automatic test system for resistor | |
| CN105699832A (en) | Cable checking and grouping method | |
| CN104634574B (en) | Engine test bench characteristic curve preparation method | |
| CN203631891U (en) | Active multifunctional adapter |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |