CN103515292B - The formation method of semiconductor structure - Google Patents
The formation method of semiconductor structure Download PDFInfo
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- CN103515292B CN103515292B CN201210203519.0A CN201210203519A CN103515292B CN 103515292 B CN103515292 B CN 103515292B CN 201210203519 A CN201210203519 A CN 201210203519A CN 103515292 B CN103515292 B CN 103515292B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
Abstract
A formation method for semiconductor structure, comprising: provide substrate; Dielectric layer is formed at described substrate surface; Described dielectric layer forms boron nitride layer; Etching described boron nitride layer and dielectric layer, to exposing substrate, forming opening; Carry out back carving to the boron nitride layer of described opening both sides, increase the width of overthe openings; Full metal level is filled in described opening.The formation method of semiconductor structure of the present invention is passed through back to carve the width that boron nitride layer increases semiconductor structure split shed, is beneficial to the filling of metal level in opening, avoids comprising cavity in formed metal level, improve the electric property of formed semiconductor device.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly relate to a kind of formation method of semiconductor structure.
Background technology
Along with the making of integrated circuit develops to very lagre scale integrated circuit (VLSIC) (ULSI), the current densities of its inside is increasing, contained number of elements constantly increases, and makes the surface of wafer that enough area cannot be provided to make required interconnection line (Interconnect).In order to co-operating member reduces rear increased interconnection line demand, the design of the two-layer above multiple layer metal interconnection line utilizing through hole to realize, becomes the method that very large scale integration technology must adopt.
Traditional metal interconnectedly to be realized by aluminium, but constantly reducing along with device feature size in integrated circuit (IC) chip, the current density in metal connecting line constantly increases, and the response time constantly shortens, and conventional aluminum interconnection line reaches technological limits.After process is less than 130nm, traditional aluminum interconnecting technology gradually replace by copper interconnecting line technology.With aluminum metallic matrix ratio, the resistivity of copper metal is lower, electromigration lifetime is longer, and RC that metal interconnecting wires can reduce interconnection line postpones, improves the integrity problem that electromigration etc. causes to utilize process for copper to make.But adopt process for copper to make interconnection line and also there is two problems: one is that the diffusion velocity of copper is very fast, two is etching difficulties of copper, therefore, its manufacturing process that is suitable for completely different from aluminium technique, mosaic texture usually can be adopted to realize in the mode of filling.
But, along with the continuous reduction of semiconductor technology node, critical size (the CD of the groove in semiconductor device and through hole, critical dimension) also corresponding reduction, easily produce cavity when filling copper metal in groove and through hole, have a strong impact on the electric property of formed semiconductor device.In addition, existing technique groove and through hole are carried out copper metal filled before usually can at groove and through-hole side wall deposited barrier layer and inculating crystal layer, to improve the adhesiveness of copper metal and groove or through-hole side wall and to prevent copper atom from being spread to dielectric layer by sidewall.But when groove and through-hole side wall deposition of adhesion and inculating crystal layer, the adhesion layer deposited and inculating crystal layer easily form projection at groove and via openings place, further reduce the width of formed groove and via openings, have a strong impact on follow-up copper metal filling processes, cause producing cavity in formed copper metal interconnecting wires.
With reference to figure 1, form by existing technique the cross-sectional view of copper semiconductor structure, the technique forming copper semiconductor structure is as follows: first, copper blocking layer 103 and low-k interlayer dielectric layer 105 on the substrate 101; Then, etching low dielectric constant interlayer dielectric layer 105, forms through hole; Again then, barrier layer 107 is formed in via bottoms and sidewall, to improve the adhesiveness between the copper metal of follow-up filling and the low-k interlayer dielectric layer 105 of through-hole side wall, and preventing copper atom from spreading in low-k interlayer dielectric layer 105, this barrier layer 107 is generally Ta, TaN or Ta and TaN composition; Then, barrier layer 107 forms copper seed layer 109, then in through hole, fill copper metal by physical gas-phase deposition, form layers of copper 111.The formation quality of this layers of copper is very large to the performance impact of circuit, directly can have influence on multiple performance parameters of circuit.
In the forming process of above-mentioned layers of copper 111, if the filling quality of copper metal is not good, the cavity 113 shown in Fig. 1 is formed in layers of copper 111 inside, formed semiconductor structure electromigration (EM will be caused, Electronic Migration) lost efficacy, the fabrication having a strong impact on the semiconductor device comprising formed semiconductor structure can test the rate of finished products of (WAT, wafer acceptance test) and wafer sort (CP, circuitprobing).
Be in the Chinese patent application of CN101996924A, to find more formation methods about semiconductor structure at publication number.
Therefore, how in the process forming semiconductor structure, to avoid in copper interconnecting line, produce cavity and just become problem demanding prompt solution.
Summary of the invention
The problem that the present invention solves is to provide a kind of formation method of semiconductor structure, avoids comprising cavity in formed metal level, improve form the electric property of semiconductor device.
For solving the problem, the invention provides a kind of formation method of semiconductor structure, comprising: substrate is provided; Dielectric layer is formed at described substrate surface; Boron nitride layer is formed at described dielectric layer surface; Etching described boron nitride layer and dielectric layer, to exposing substrate, forming opening; Carry out back carving to the boron nitride layer of described opening both sides, increase the width of overthe openings; Full metal level is filled in described opening.
Optionally, described dielectric layer is advanced low-k materials or ultra-low dielectric constant material.
Optionally, before described dielectric layer forms boron nitride layer, also comprise: by acetylene plasma, described dielectric layer surface is bombarded, increase the phosphorus content of described dielectric layer surface.
Optionally, the power forming the radio-frequency power supply of described acetylene plasma is 100 ~ 1000W, and pressure is 1 ~ 7Torr, and acetylene flow is 150 ~ 2000sccm.
Optionally, the method for carrying out back carving to the boron nitride layer of described opening both sides is dry etching method.
Optionally, the etching gas that described dry etching method adopts is chlorine, and the power of radio-frequency power supply is 100 ~ 1000W, and pressure is 1 ~ 7Torr, and chlorine flowrate is 50 ~ 2000sccm.
Optionally, the material of described metal level is copper.
Optionally, fill full metal level in described opening before, also comprise: form barrier layer in the bottom of described opening and sidewall; Inculating crystal layer is formed on described barrier layer.
Optionally, the material on described barrier layer is the composition of tantalum, tantalum nitride or tantalum and tantalum nitride.
Optionally, the material of described inculating crystal layer is copper.
Compared with prior art, technical solution of the present invention has the following advantages:
By forming dielectric layer and boron nitride layer successively from the bottom to top at substrate surface, again etching is carried out to boron nitride layer and dielectric layer and form opening, and pass through back to carve boron nitride layer increase form the width of overthe openings, in the process of filling metal level, avoid the metal layer itself caused because overthe openings seals in advance and produce cavity, effectively prevent the generation of short circuit and leakage phenomenon, improve form the electric property of semiconductor device.
In possibility; before formation boron nitride layer; by acetylene plasma, dielectric layer surface is bombarded; improve the phosphorus content of dielectric layer surface; because chlorine plasma is lower to the dielectric layer etching rate that phosphorus content is high; the high dielectric layer of phosphorus content can the dielectric layer that is positioned at below it of available protecting injury-free, and then improve form the electric property of semiconductor device.
Accompanying drawing explanation
Fig. 1 forms by existing technique the generalized section of copper semiconductor structure;
Fig. 2 is the schematic flow sheet of formation method one execution mode of semiconductor structure of the present invention;
The formation method that Fig. 3 to Fig. 9 is semiconductor structure in one embodiment of the invention form the generalized section in semiconductor structure each stage;
The formation method that Figure 10 to Figure 18 is semiconductor structure in another embodiment of the present invention form the generalized section in semiconductor structure each stage.
Embodiment
For enabling above-mentioned purpose of the present invention, feature and advantage become apparent more, are described in detail the specific embodiment of the present invention below in conjunction with accompanying drawing.
Set forth a lot of detail in the following description so that fully understand the present invention.But the present invention can be much different from alternate manner described here to implement, those skilled in the art can when without prejudice to doing similar popularization when intension of the present invention, therefore the present invention is by the restriction of following public concrete enforcement.
Secondly, the present invention utilizes schematic diagram to be described in detail, and when describing the embodiment of the present invention in detail, for ease of illustrating, described schematic diagram is example, and it should not limit the scope of protection of the invention at this.
Just as described in the background section, along with the continuous reduction of semiconductor technology node, the critical size of semiconductor device also constantly reduces, the depth-to-width ratio of groove or through hole is caused to become large, when the formation method of existing semiconductor structure fills metal material to form metal level in groove or through hole, easily side first closes on trenches or vias, and makes to be formed in metal level cavity, cause formed semiconductor structure generation electromigration invalidation, impact form the electric property of semiconductor device.
For above-mentioned defect, the invention provides a kind of formation method of semiconductor structure, by forming dielectric layer and boron nitride layer successively from the bottom to top at substrate surface, again etching is carried out to boron nitride layer and dielectric layer and form opening, and pass through back to carve boron nitride layer increase form the width of opening, be beneficial to the filling of metal level in opening, avoid comprising cavity in formed metal level, improve form the electric property of semiconductor device.
With reference to figure 2, show the schematic flow sheet of formation method one execution mode of semiconductor structure of the present invention, comprise the following steps:
Step S1, provides substrate;
Step S2, forms dielectric layer at described substrate surface;
Step S3, forms boron nitride layer at described dielectric layer surface;
Step S4, etches described boron nitride layer and dielectric layer, to exposing substrate, forms opening;
Step S5, carries out back carving to the boron nitride layer of described opening both sides, increases the width of overthe openings;
Step S6, fills full metal level in described opening.
Be described in detail below in conjunction with accompanying drawing.
Embodiment one
Present embodiments provide a kind of formation method comprising the semiconductor device of through hole, specifically as shown in Fig. 3 ~ Fig. 9:
With reference to figure 3, provide substrate 301, form stop-layer 303 and dielectric layer 305 successively from the bottom to top on described substrate 301 surface.
In the present embodiment, the material of described substrate 301 is monocrystalline silicon or single-crystal silicon Germanium, or monocrystalline carbon doped silicon; Or can also comprise other material, the present invention does not limit this.
In addition, be formed with device architecture (not shown) in described substrate 301, described device architecture can for the device architecture formed in semiconductor FEOL, such as MOS transistor etc.; Can also comprise in described substrate 301 for realizing the metal interconnecting wires be electrically connected.
Described stop-layer 303 diffuses to Semiconductor substrate 301 for preventing the follow-up metallic atom be formed in through hole, and the method forming stop-layer 303 is chemical vapour deposition (CVD) (CVD, Chemical VaporDeposition) technique.Particularly, when the follow-up metal level formed in through-holes is copper, the material of described stop-layer 303 is silicon nitride.
It should be noted that, according to the difference of metal level material, the material of stop-layer 303 is also not limited to silicon nitride.
In other embodiments, can not also form described stop-layer 303, directly form dielectric layer 305 on substrate 301 surface, the present invention does not limit this.
In the present embodiment, the material of described dielectric layer 305 is advanced low-k materials (low k) or ultra-low dielectric constant material (Ultra low k, ULK), for isolating the metal level of follow-up formation, to reduce the parasitic capacitance between metal level.The method forming described dielectric layer 305 is chemical vapor deposition method.
Continue with reference to figure 3, by acetylene (C
2h
2) plasma bombards described dielectric layer 305 surface.
In the present embodiment, the power forming the radio-frequency power supply of described acetylene plasma is 100 ~ 1000W, and pressure is 1 ~ 7Torr, and acetylene flow is 150 ~ 2000sccm.By acetylene plasma, dielectric layer 305 is bombarded, improve the phosphorus content on dielectric layer 305 surface.Because the etching rate of chlorine plasma to the higher dielectric layer 305 of phosphorus content is less; when the follow-up boron nitride layer to being positioned at above formed through hole carries out back carving, the dielectric layer 305 that the dielectric layer 305 surface energy available protecting that phosphorus content is higher is positioned at below it is injury-free.
In other embodiments, can not also comprise by acetylene (C
2h
2) plasma step that described dielectric layer 305 surface is bombarded.
With reference to figure 4, form boron nitride layer 307 on described dielectric layer 305 surface.
In the present embodiment, the technique forming described boron nitride (BN) layer 307 is chemical vapor deposition method, but the present invention is not limited thereto.
With reference to figure 5, form on described boron nitride layer 307 surface the mask layer 309 comprising through-hole pattern.
In the present embodiment, described in comprise the mask layer 309 of through-hole pattern material be titanium nitride (TiN), form that to comprise the concrete technology of the mask layer 309 of through-hole pattern as follows:
Mask layer and photoresist layer (not shown) is formed successively from the bottom to top on described boron nitride layer 307 surface;
Photoresist layer described in patterning, forms the photoresist layer comprising through-hole pattern;
To comprise the photoresist layer of through-hole pattern for mask, etch described mask layer, form the mask layer 309 comprising through-hole pattern;
The photoresist layer of through-hole pattern is comprised described in removal.
In the present embodiment, the technique forming mask layer 309 on described boron nitride layer 307 surface is chemical vapor deposition method, but the present invention is not limited thereto.
The present invention does not limit the material of photoresist, can be the photoresist of any materials.
With reference to figure 6, with the described mask layer 309 comprising through-hole pattern for mask, etching described boron nitride layer 307 and dielectric layer 305, to exposing stop-layer 303, forming through hole 321.
In the present embodiment, the technique etching described boron nitride layer 307 and dielectric layer 305 is dry etching method, but the present invention is not restricted to this.Follow-up carry out back carving to the boron nitride layer 307 above through hole 321 time, be positioned at stop-layer 303 bottom through hole 321 can available protecting substrate 301 injury-free, improve form the performance of semiconductor structure.
With reference to figure 7, carry out back carving to the boron nitride layer 307 above described through hole 321, increase the A/F of boron nitride layer 307.
In the present embodiment, the method for carrying out back carving to the boron nitride layer 307 above described through hole 321 is dry etching method.Concrete, the etching gas that described dry etching method adopts is chlorine (Cl
2), the power of radio-frequency power supply is 100 ~ 1000W, and pressure is 1 ~ 7Torr, and chlorine flowrate is 50 ~ 2000sccm.Carry out back carving to boron nitride layer 307 by chlorine plasma, to remove the partial nitridation boron layer 307 of through hole 321 both sides, increase the A/F of boron nitride layer 307.
With reference to figure 8, remove the stop-layer 303 be positioned at bottom through hole 321, to exposing substrate 301.
In the present embodiment, the technique removing the stop-layer 303 be positioned at bottom through hole 321 is dry etching method, but the present invention is not limited thereto.
In other embodiments, when substrate 301 surface directly forms dielectric layer 305, accordingly, do not need to remove the stop-layer 303 be positioned at bottom through hole 321 yet, directly in described through hole 321, fill full metal level.
With reference to figure 8 and Fig. 9, in described through hole 321, fill full metal level 315.
In the present embodiment, the material of described metal level 315 is copper, and the method for filling full metal level 315 in described through hole 321 is physical vapour deposition (PVD) (Physical Vapor Deposition, PVD) technique.
In the present embodiment, fill full metal level 315 in described through hole 321 before, also comprise: remove the mask layer 309 comprising through-hole pattern, to reduce the depth-to-width ratio of through hole 321, be beneficial to the filling of through hole 321 inner metal layer 315, avoid comprising cavity in formed metal level 315.
In the present embodiment, fill full metal level 315 in described through hole 321 before, also comprise further: form barrier layer 311 in the bottom of described through hole 321 and sidewall; Inculating crystal layer 313 is formed on described barrier layer 311.
Concrete, the material on described barrier layer 311 is the composition of tantalum (Ta), tantalum nitride (TaN) or tantalum and tantalum nitride; The material of described inculating crystal layer 313 is copper.As described in barrier layer 311 be the composition of tantalum and tantalum nitride, when forming described barrier layer 311, first can carry out tantalum nitride membrane deposition, carry out metal tantalum deposition again, to stop the metal level 315 of subsequent deposition and direct contact of dielectric layer 305 dielectric layer material, improve the adhesiveness between metal level 315 and dielectric layer 305 simultaneously.Described barrier layer 311 is formed by physical gas-phase deposition, and also can be undertaken by other method, the present invention does not limit this.Described inculating crystal layer 313 is that the deposition of subsequent metal layer 315 provides conductive layer.The concrete formation process of described barrier layer 311 and inculating crystal layer 313, as the known technology of those skilled in the art, does not repeat at this.
In the present embodiment, in described through hole 321, fill full metal level 315 comprise the following steps:
In described through hole 321, fill metal material (not shown), described metal material fills up through hole 321 and covers the boron nitride layer 307 of through hole 321 opening both sides;
Metal material described in planarization, to exposing boron nitride layer 307, forms metal level 315.
Concrete, by metal material described in cmp (CMP, Chemical Mechanical Polishing) technique planarization.
It should be noted that, in the process of metal material described in planarization, also eliminate and be positioned at barrier layer 311 on boron nitride layer 307 and inculating crystal layer 313.
Second embodiment
Present embodiments provide a kind of formation method comprising the semiconductor structure of double damask structure, specifically as shown in Figure 10 ~ Figure 18:
With reference to Figure 10, provide substrate 201, form stop-layer 203 and dielectric layer 205 successively from the bottom to top on described substrate 201 surface.
In the present embodiment, the material of described substrate 201 is monocrystalline silicon or single-crystal silicon Germanium, or monocrystalline carbon doped silicon; Or can also comprise other material, the present invention does not limit this.
In addition, be formed with device architecture (not shown) in described substrate 201, described device architecture can for the device architecture formed in semiconductor FEOL, such as MOS transistor etc.; Can also comprise in described substrate 201 for realizing the plain conductor be electrically connected.
Described stop-layer 203 diffuses to Semiconductor substrate 201 for preventing the follow-up metallic atom be formed in the second through hole, and the method forming stop-layer 203 is chemical vapor deposition method.Particularly, when the follow-up metal level deposited in the second through hole is copper, the material of described stop-layer 203 is silicon nitride.
It should be noted that, according to the difference of metal level material, the material of stop-layer 203 is also not limited to silicon nitride.
In other embodiments, described substrate 201 surface can not also form stop-layer 203, and directly forms dielectric layer 205, and the present invention does not limit this.
In the present embodiment, the material of described dielectric layer 205 is advanced low-k materials or ultra-low dielectric constant material, for isolating the metal level of follow-up formation, to reduce the parasitic capacitance between metal level.The method forming described dielectric layer 205 is chemical vapor deposition method.
Continue, with reference to Figure 10, to be bombarded described dielectric layer 205 surface by acetylene plasma.
In the present embodiment, the power forming the radio-frequency power supply of described acetylene plasma is 100 ~ 1000W, and pressure is 1 ~ 7Torr, and acetylene flow is 150 ~ 2000sccm.By acetylene plasma, dielectric layer 205 is bombarded, improve the phosphorus content on dielectric layer 205 surface.
Because the etching rate of chlorine plasma to the higher dielectric layer 205 of phosphorus content is less; when the follow-up boron nitride layer to being positioned at above formed groove carries out back carving, the dielectric layer 205 that the dielectric layer 205 surface energy available protecting that phosphorus content is higher is positioned at below it is injury-free.
In other embodiments, can not also comprise by acetylene (C
2h
2) plasma step that described dielectric layer 205 surface is bombarded.
With reference to Figure 11, described dielectric layer 205 forms boron nitride layer 207.
In the present embodiment, the technique forming described boron nitride layer 207 is chemical vapor deposition method, but the present invention is not limited thereto.
With reference to Figure 12, form on described boron nitride layer 207 surface the mask layer 209 comprising through-hole pattern.
In the present embodiment, described in comprise the mask layer 209 of through-hole pattern material be titanium nitride, form that to comprise the concrete technology of the mask layer 209 of through-hole pattern as follows:
Mask layer and photoresist layer (not shown) is formed successively from the bottom to top on described boron nitride layer 207 surface;
Photoresist layer described in patterning, forms the photoresist layer comprising through-hole pattern;
To comprise the photoresist layer of through-hole pattern for mask, etch described mask layer, form the mask layer 209 comprising through-hole pattern;
The photoresist layer of through-hole pattern is comprised described in removal.
With reference to Figure 13, with the described mask layer 209 comprising through-hole pattern for mask, etching described boron nitride layer 207 and dielectric layer 205, to exposing stop-layer 203, forming the first through hole 221.
In the present embodiment, the method etching described boron nitride layer 207 and dielectric layer 205 is dry etching method, but the present invention is not restricted to this.
With reference to Figure 14, described in patterning, comprise the mask layer 209 of through-hole pattern, form the mask layer 210 comprising channel patterns.
In the present embodiment, form the mask layer 210 comprising channel patterns and comprise the following steps:
In described stop-layer 203 and the mask layer 209 surface formation photoresist layer (not shown) comprising through-hole pattern;
Photoresist layer described in patterning, forms the photoresist layer comprising channel patterns;
With the described photoresist layer of channel patterns that comprises for mask, described in etching, comprise the mask layer 209 of through-hole pattern, form the mask layer 210 comprising channel patterns;
Remove described photoresist layer.
With reference to Figure 15, to comprise the mask layer 210 of channel patterns for mask, etch nitride boron layer 207 and certain media layer 205, to remainder dielectric layer 205, form groove 223.
With reference to Figure 16, carry out back carving, to increase the A/F of boron nitride layer 207 to the boron nitride layer 207 of described groove 223 both sides.
In the present embodiment, the method for carrying out back carving to the boron nitride layer 207 of described groove 223 both sides is dry etching method.Concrete, the etching gas that described dry etching method adopts is chlorine, and the power of radio-frequency power supply is 100 ~ 1000W, and pressure is 1 ~ 7Torr, and chlorine flowrate is 50 ~ 2000sccm.Carry out back carving to boron nitride layer 207 by chlorine plasma, remove the partial nitridation boron layer 207 above groove 223, increase the A/F of boron nitride layer 207, be beneficial to the filling of subsequent metal layer.
With reference to Figure 17, removing the stop-layer 203 be positioned at bottom the first through hole 221, to exposing substrate 201, forming the second through hole 225.Described groove 223 and the second through hole 225 form the double damask structure in semiconductor structure.
In the present embodiment, the method removing the stop-layer 203 be positioned at bottom through hole 221 is dry etching method, but the present invention is not limited thereto.
It should be noted that, for embodiment substrate 201 not being formed stop-layer 203, do not comprise the step that above-mentioned removal is positioned at the stop-layer 203 bottom through hole 221.
With reference to Figure 17 and Figure 18, in described groove 223 and the second through hole 225, fill full metal level 219.
In the present embodiment, the material of described metal level 219 is copper, and the method for filling full metal level 219 in described groove 223 and the second through hole 225 is physical gas-phase deposition.
In the present embodiment, fill full metal level 219 in described groove 223 and the second through hole 225 before, also comprise: remove the mask layer 210 comprising channel patterns, be beneficial to the filling of groove 223 and the second through hole 225 inner metal layer 219, avoid comprising cavity in formed metal level 219.
In the present embodiment, fill full metal level 219 in described groove 223 and the second through hole 225 before, also comprise further: form barrier layer 215 in the bottom of the sidewall of described groove 223 and described second through hole 225 and sidewall; Inculating crystal layer 217 is formed on described barrier layer 215.
In the present embodiment the material of barrier layer 215 and inculating crystal layer 217 and formation process identical with inculating crystal layer 313 with barrier layer 311 in embodiment one respectively, do not repeat at this.
In the present embodiment, form groove (i.e. via-first technique) technique again form double damask structure in semiconductor structure by first forming through hole, in other embodiments, also form through hole (i.e. trench-first technique) or self-registered technology (i.e. self-aligned technique) again form double damask structure in semiconductor structure by first forming groove, its forming step does not repeat at this.
In above-described embodiment, by forming dielectric layer and boron nitride layer successively from the bottom to top at substrate surface, carry out etching the double damask structure forming through hole or comprise through hole and groove again to boron nitride layer and dielectric layer, and pass through back to carve boron nitride layer increase form the A/F of groove in through hole or double damask structure, be beneficial to through hole or comprise the filling of metal level in through hole and groove double damask structure, avoid comprising cavity in formed metal level, improve form the electric property of semiconductor device.
The method that the present invention forms semiconductor structure is also suitable for forming interconnecting construction.
Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; the Method and Technology content of above-mentioned announcement can be utilized to make possible variation and amendment to technical solution of the present invention; therefore; every content not departing from technical solution of the present invention; the any simple modification done above embodiment according to technical spirit of the present invention, equivalent variations and modification, all belong to the protection range of technical solution of the present invention.
Claims (10)
1. a formation method for semiconductor structure, is characterized in that, comprising:
Substrate is provided;
Dielectric layer is formed at described substrate surface;
Boron nitride layer is formed at described dielectric layer surface;
The titanium nitride layer comprising through-hole pattern is formed on described boron nitride layer surface;
With described titanium nitride layer for mask, etching described boron nitride layer and dielectric layer, to exposing stop-layer, forming opening;
With described titanium nitride layer for mask, carry out back carving to the boron nitride layer of described opening both sides, increase the width of overthe openings;
Remove described titanium nitride layer;
Full metal level is filled in described opening.
2. the formation method of semiconductor structure as claimed in claim 1, it is characterized in that, described dielectric layer is advanced low-k materials or ultra-low dielectric constant material.
3. the formation method of semiconductor structure as claimed in claim 1, be is characterized in that, before described dielectric layer forms boron nitride layer, also comprise: bombarded described dielectric layer surface by acetylene plasma, increase the phosphorus content of described dielectric layer surface.
4. the formation method of semiconductor structure as claimed in claim 3, it is characterized in that, the power forming the radio-frequency power supply of described acetylene plasma is 100 ~ 1000W, and pressure is 1 ~ 7Torr, and acetylene flow is 150 ~ 2000sccm.
5. the formation method of semiconductor structure as claimed in claim 1, is characterized in that, the method for carrying out back carving to the boron nitride layer of described opening both sides is dry etching method.
6. the formation method of semiconductor structure as claimed in claim 5, is characterized in that, the etching gas that described dry etching method adopts is chlorine, and the power of radio-frequency power supply is 100 ~ 1000W, and pressure is 1 ~ 7Torr, and chlorine flowrate is 50 ~ 2000sccm.
7. the formation method of semiconductor structure as claimed in claim 1, it is characterized in that, the material of described metal level is copper.
8. the formation method of semiconductor structure as claimed in claim 1, is characterized in that, before filling full metal level, also comprises in described opening: form barrier layer in the bottom of described opening and sidewall; Inculating crystal layer is formed on described barrier layer.
9. the formation method of semiconductor structure as claimed in claim 8, it is characterized in that, the material on described barrier layer is the composition of tantalum, tantalum nitride or tantalum and tantalum nitride.
10. the formation method of semiconductor structure as claimed in claim 8, it is characterized in that, the material of described inculating crystal layer is copper.
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| CN105633135B (en) * | 2014-11-06 | 2019-03-12 | 中芯国际集成电路制造(上海)有限公司 | Transistor and forming method thereof |
| CN109087886B (en) * | 2018-11-05 | 2019-10-25 | 武汉新芯集成电路制造有限公司 | Metal interconnection structure and preparation method thereof |
| CN113380648A (en) * | 2021-05-13 | 2021-09-10 | 中国科学院微电子研究所 | Bonded semiconductor device and method for manufacturing the same |
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| US5374591A (en) * | 1991-03-22 | 1994-12-20 | Sony Corporation | Method of making a metal plug |
| US6027982A (en) * | 1999-02-05 | 2000-02-22 | Chartered Semiconductor Manufacturing Ltd. | Method to form shallow trench isolation structures with improved isolation fill and surface planarity |
| US6962869B1 (en) * | 2002-10-15 | 2005-11-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | SiOCH low k surface protection layer formation by CxHy gas plasma treatment |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US8043973B2 (en) * | 2008-05-22 | 2011-10-25 | Texas Instruments Incorporated | Mask overhang reduction or elimination after substrate etch |
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| US5374591A (en) * | 1991-03-22 | 1994-12-20 | Sony Corporation | Method of making a metal plug |
| US6027982A (en) * | 1999-02-05 | 2000-02-22 | Chartered Semiconductor Manufacturing Ltd. | Method to form shallow trench isolation structures with improved isolation fill and surface planarity |
| US6962869B1 (en) * | 2002-10-15 | 2005-11-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | SiOCH low k surface protection layer formation by CxHy gas plasma treatment |
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