CN103560150B - 具有外延源区和漏区的金属栅晶体管 - Google Patents

具有外延源区和漏区的金属栅晶体管 Download PDF

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CN103560150B
CN103560150B CN201310419494.2A CN201310419494A CN103560150B CN 103560150 B CN103560150 B CN 103560150B CN 201310419494 A CN201310419494 A CN 201310419494A CN 103560150 B CN103560150 B CN 103560150B
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region
drain region
lightly doped
monocrystalline substrate
source region
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CN103560150A (zh
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N·林德特
J·布拉斯克
A·韦斯特梅耶
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Intel Corp
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Abstract

公开一种具有外延源区和漏区的金属栅晶体管。描述了形成于重掺杂的衬底上的MOS晶体管。在低温处理中使用金属栅以防止衬底的掺杂扩散到晶体管的沟道区。

Description

具有外延源区和漏区的金属栅晶体管
本申请是国际申请日为2005年9月29日、中国国家阶段申请号为200580032453.1、题为“具有外延源区和漏区的金属栅晶体管”的发明专利申请的分案申请。
发明领域
本发明涉及MOS晶体管的领域，尤其涉及以外延源区和漏区制造的MOS晶体管。
现有技术和相关技术
在Noda等人的“0.1μm Delta-Doped MOSFET Using Post Low EnergyImplanting Selective Epitaxy”，VLSI Technology1994,技术论文的摘要中描述了δ掺杂晶体管。δ掺杂晶体管的动机是用未掺杂或轻掺杂的沟道来实现较高的迁移率(较低的杂质分散)。在2003年10月24日提交的题为“Epitaxially DepositedSource/Drain”的专利申请序列号10/692,696中也描述了这种器件，该专利转让给本申请的受让人。
这些晶体管的制造大部分依靠重掺杂衬底和衬底的轻掺杂或未掺杂外延形成的表面之间的掺杂水平的差别。由于这一掺杂水平的差别，蚀刻剂能够在衬底的表面区和主体之间进行区分。然而，出现了一个问题，即在形成栅结构时，需要相对较高温度的处理以便例如激活多晶硅栅中的掺杂。这导致掺杂剂从衬底扩散到沟道区中，由此使晶体管的性能劣化。
附图简述
图1是硅衬底的上部区域的横截面正视图，用于示出在衬底的上部区域中的掺杂曲线。
图2示出当在衬底上生长未掺杂或轻掺杂半导体层后图1的衬底。
图3是除用于形成栅的其它层以外的图2的衬底和半导体层的横截面俯视图。
图4示出在形成栅后图3的衬底。
图5示出在栅上形成侧壁隔片后图4的衬底。
图6示出在用于蚀刻半导体层的蚀刻步骤后图5的衬底。该图示出栅的底切。
图7示出在源区和漏区的外延生长后图6的衬底。
图8示出在形成另外的隔片和掺杂了源区和漏区的暴露部分后图7的结构。
图9示出在形成硅化物层后图8的结构。
图10示出其中两个晶体管并排示出的图9的结构，尤其描述了n沟道晶体管和p沟道晶体管。
图11示出在层间电介质(ILD)的化学机械抛光(CMP)后图10的结构。
图12示出当在p沟道晶体管区上形成光刻胶层并将多晶硅栅和其下面的绝缘层从n沟道栅中去除之后图11的结构。
图13示出在形成n金属层后图12的结构。
图14示出在CMP处理后图13的结构。
图15示出在从p沟道栅中去除多晶硅栅和其下面的绝缘层后图14的结构。
图16示出在沉积p金属后图15的结构。
图17示出CMP处理后图16的结构。
详细描述
描述了互补金属氧化物半导体（MOS）场效应晶体管的制造工艺和所得的晶体管。在以下描述中，陈述了诸如特定的掺杂剂浓度水平、特定的化学药品等的众多特定的细节，以提供对本发明的全面理解。本领域的技术人员将明白，不需要这些特定细节也能实施本发明。在其他情况下，没有详细描述诸如清洗步骤之类的公知的处理步骤，以免不必要地使以下的公开内容晦涩。
在图1中，示出了单晶硅衬底10的约200纳米(nm)的上部。如图所示，用诸如硼之类的掺杂剂重掺杂该衬底的上部区域。掺杂曲线示出掺杂水平在超过1019原子/立方厘米或更高的表面下具有峰值。该掺杂曲线可利用离子注入来获得。
在衬底的掺杂后，在衬底10的上表面上形成示为单晶硅层12的外延层。例如，外延硅层12的沉积利用基于二氯硅烷的化学品在诸如ASM E3000反应器之类的单晶片CVD反应器中实现。该膜以气体流量为140-250sccm的二氯硅烷（SiH2Cl2）、100-150sccm的HCl、20slm的H2在825℃和20Torr的处理压力下来沉积。在这些处理条件下，对于暴露的衬底上的硅实现了10-15nm/min的沉积速度，同时实现了对于隔片和氧化物区的极好的选择性。层12可具有约85nm的厚度，且其掺杂浓度将例如小于衬底的埋置峰值掺杂浓度的1/100。
在形成层12后，在层10上形成绝缘层13。层13可以是薄的、热生长氧化物层或沉积的二氧化硅层。接着，在绝缘层13上沉积多晶硅层14。正如将要看到的，由层14形成的栅是牺牲的。它们随后将被去除，并由金属代替由这些多晶硅栅占据的区域。在多晶硅层14上形成硬掩模。
接着，如图4所示，通过首先利用普通的光刻处理掩模并蚀刻硬掩模15以限定用于栅的掩模构件来制造牺牲栅结构。现在，利用普通的蚀刻剂与硬掩模15对准地蚀刻多晶硅层14和绝缘层13。在图4中描述了所得的结构。
如图5所示，然后在图4的栅上形成侧壁16。可利用普通的侧壁处理来形成相对薄的氮化硅侧壁构件16。这些侧壁隔片的目的是在随后的处理期间保护多晶硅。因此，多晶硅栅14的所有侧面都被覆盖。因为侧壁隔片用于保护多晶硅，所以它们可相对薄。
现在，蚀刻层12以形成沟道体12a。该蚀刻底切栅结构，如由图6中的底切20所示。
层12可用各种基于氢氧化物的溶液来蚀刻。然而，为了对重掺杂结构的高选择性，采用相对温和的处理条件和湿法蚀刻。一种方法是用2-10%范围的体积浓度的氢氧化铵水溶液，在25摄氏度下用以0.5到5W/cm2的功率耗散超声能或兆声能的超声波传感器来处理。
然后生长源区和漏区，以建立在栅边缘下横向延伸一定的距离到沟道体12a的浅、高掺杂的源/漏尖端(延伸)。对p沟道和n沟道晶体管使用分离处理，且源区和漏区中的每一个都在不同的处理步骤中生长，两者都利用了原位掺杂。这得到了高掺杂的源区和漏区，在一种情况下用p型掺杂剂，而在另一种情况下用n型掺杂剂。
在形成PMOS晶体管时，源/漏延伸(尖端)是通过选择性地沉积外延硼(B)掺杂的硅或具有高达30%的锗浓度的SiGe来形成的凸起的源/漏区。在100sccm的二氯甲硅烷(DCS)、20slm的H2、750-800℃、20Torr、150-200sccm的HCl、150-200sccm流量的乙硼烷(B2H6)以及150-200sccm流量的CeH4的处理条件下，获得了具有20nm/min的沉积速率、1E20cm-3的B浓度以及20%的锗浓度的高掺杂SiGe膜。由膜中的高B浓度得到的0.7-0.9mOhm-cm的低电阻率提供在尖端源/漏区中的高电导率以及由此减小的R外部的优点。在源/漏区中的SiGe在沟道上施加压缩应力，这进而得到增强的迁移率和提高的晶体管性能。
对于NMOS晶体管，在100sccm的DCS、25-50sccm的HCl、具有20slm的载体H2气体流量的200-300sccm的1%Ph3在750℃和20Torr的处理条件下利用选择性沉积的原位磷掺杂硅来形成源/漏区。在沉积膜中获得了具有0.4-0.6mOhm-cm的电阻率的2E20cm-3的磷浓度。
在如图7所示形成源/漏区后，利用普通的处理来形成另外的隔片24。作为一个示例，隔片可以是氮化硅或二氧化硅隔片。隔片24与如图8所示的隔片16的厚度相比相对较厚。
现在进行离子注入以在衬底10中形成源/漏区26。此外，对p型掺杂剂和n型掺杂剂使用分隔离子注入工艺。可将区域26注入成1020原子/立方厘米的水平。
如图9所示，可使用普通的硅化物工艺或自对准多晶硅化物（salicide）处理来形成自对准多晶硅化物层28，从而使源/漏区的上表面更导电。
在图10中，连同p沟道晶体管一起描述了n沟道晶体管。对于n沟道晶体管沟道区示为12b，而对于p沟道晶体管为12c。以下使用字母“b”来表示用于n沟道晶体管的层和区域，类似地，用字母“c”来表示用于p沟道晶体管的层和区域。图10中所示的结构除在晶片上形成ILD30外与图9所示的一样。诸如二氧化硅、碳掺杂二氧化硅或其他低k电介质等多种电介质中的任何一种可用于ILD。
现在，使用CMP来提供平坦化表面并从栅14b和14c的顶部去除自对准多晶硅化物。所得的结构在图11中示出。
接着，在p沟道晶体管上形成光刻胶层32，并利用湿法蚀刻剂来从n沟道晶体管去除多晶硅。同样去除下面的绝缘层，从而形成图12中所描述的开口。
现在，如图13所示，连同称为“n金属”的金属层38一起形成绝缘层37b，金属层38被称为“n金属”是因为它是具有用于n沟道晶体管的适当功函数的金属。栅电介质理想地具有高介电常数，诸如如HfO2、ZrO2等的金属氧化物电介质或如PZT或BST等的其它高k电介质。高k介电膜可通过诸如化学气相沉积(CVD)之类的任何公知的技术来形成。栅电极层38可通过适当的栅电极材料的毯式沉积（blanket deposition）来形成。在一个实施例中，栅电极材料包括诸如钨、钽和/或其氮化物和合金等金属膜。对于n沟道晶体管，可采用4.0到4.6eV范围的功函数。
接着使用CMP来使表面平坦化，从而去除除以前由多晶硅栅占据的区域内以外的金属层38。所得的栅38b和下面的绝缘层37b在图14中示出。
使用湿法蚀刻剂来去除与p沟道晶体管相关联的多晶硅栅。此外，同样去除下面的绝缘层，以形成更适当的绝缘层。在去除多晶硅栅和下面的绝缘层后得到图15的开口42。在暴露的硅上形成栅电介质37c。该电介质可与电介质37b相同。
在图15的结构和栅电介质37b上形成金属层44。这示为图16中的“p金属”，因为该金属的功函数适合于p沟道晶体管。p金属除功函数较佳地在4.6到5.2eV之间外可与n金属的成分相同。
在沉积p金属后，利用CMP来使结构平坦化，且所得的结构在图17中示出。得到了具有栅37b和沟道区12b的n沟道晶体管，且类似地，得到了具有栅44c和沟道区12c的p沟道晶体管。
图17的晶体管及其制造在与现有技术晶体管相比时有几个优点。首先，浅的尖端(延伸)结深度对于帮助支持较小的晶体管尺寸是理想的。当利用传统的注入尖端技术时，最小的尖端结深度受到必要的栅重叠的限制。采用图17的结构和所述的处理，可更好地控制栅重叠尺寸和结深度。例如，可定时湿法蚀刻以确定栅结构下的底切的程度。
浅的尖端结深度允许制造较短的栅长度，而不增大截止状态的漏电流。需要在栅边缘下进行尖端掺杂以保证栅下的反型层和高掺杂的源/漏尖端区之间的低电阻路径。低电阻允许较高的驱动电流，这对于电路切换速度是关键的。
金属栅的一个优点是处理可在较低的温度下进行。这在与多晶硅栅相比时增加了以金属栅获得的较好的性能。在以上所述的处理中，较低温度的选择用于减小总的热暴露。正如先前所提及的，这防止掺杂剂从衬底扩散到沟道区。
因此，描述了具有金属栅的δ掺杂晶体管以及制造方法。

Claims (8)

1.一种PMOS晶体管，包括：
单晶硅衬底，包括重掺杂的上区域；
未掺杂或轻掺杂的单晶硅沟道区，直接设置在所述单晶硅衬底的最上表面上并具有顶表面；
源区和漏区对，每个源区和漏区包括直接设置在所述单晶硅衬底的最上表面上、与所述未掺杂或轻掺杂的单晶硅沟道区直接相邻且从所述单晶硅衬底的最上表面直接向上延伸超出所述未掺杂或轻掺杂的单晶硅沟道区的顶表面的外延硅锗第一部分，并且每个源区和漏区还包括仅部分地延伸到所述单晶硅衬底中的第二部分，所述第二部分直接在所述第一部分下方；以及
金属栅，与所述未掺杂或轻掺杂的单晶硅沟道区绝缘、被设置超过所述未掺杂或轻掺杂的单晶硅沟道区并位于其上方、且被设置超过所述源区和漏区中每一个的所述第一部分的至少部分并位于其上方，其中所述源区和漏区中每一个的所述第一部分包括在所述金属栅之下的所述外延硅锗和所述未掺杂或轻掺杂的单晶硅沟道区之间的成角度面轮廓，并且其中所述源区和漏区中每一个的所述第二部分仅包括一个圆化扩散角轮廓，所述一个圆化扩散角轮廓低于所述金属栅但并不在所述金属栅下方。
2.如权利要求1所述的晶体管，其特征在于，还包括设置在所述金属栅附近的第一侧壁隔片。
3.如权利要求2所述的晶体管，其特征在于，还包括在所述源区和漏区中每一个的所述第一部分的至少部分上的硅化物层。
4.如权利要求1所述的晶体管，其特征在于，所述单晶硅衬底的重掺杂的上区域具有1019原子/立方厘米或更高的峰值掺杂浓度。
5.一种PMOS晶体管，包括：
单晶硅衬底，包括重掺杂的上区域；
未掺杂或轻掺杂的单晶硅沟道区，直接设置在所述单晶硅衬底的最上表面上并具有顶表面；
源区和漏区对，每个源区和漏区包括直接设置在单晶硅衬底的最上表面上、与所述未掺杂或轻掺杂的单晶硅沟道区直接相邻且从所述单晶硅衬底的最上表面直接向上延伸超出所述未掺杂或轻掺杂的单晶硅沟道区的顶表面的外延硅锗第一部分，并且每个源区和漏区还包括仅部分地延伸到所述单晶硅衬底中的第二部分，所述第二部分直接在所述第一部分下方；以及
非硅金属栅，与所述未掺杂或轻掺杂的单晶硅沟道区绝缘、被设置在所述未掺杂或轻掺杂的单晶硅沟道区上方、且被设置在所述源区和漏区中每一个的所述第一部分的至少部分的上方，其中所述源区和漏区中每一个的所述第一部分包括在所述非硅金属栅之下的所述外延硅锗和所述未掺杂或轻掺杂的单晶硅沟道区之间的成角度面轮廓，并且其中所述源区和漏区中每一个的所述第二部分仅包括一个圆化扩散角轮廓，所述一个圆化扩散角轮廓低于所述非硅金属栅但并不在所述非硅金属栅下方。
6.如权利要求5所述的晶体管，其特征在于，还包括设置在所述金属栅附近的第一侧壁隔片。
7.如权利要求6所述的晶体管，其特征在于，还包括在所述源区和漏区中每一个的所述第一部分的至少部分上的硅化物层。
8.如权利要求5所述的晶体管，其特征在于，所述单晶硅衬底的重掺杂的上区域具有1019原子/立方厘米或更高的峰值掺杂浓度。
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