CN103579313A - Structure for improving breakdown voltages of high-voltage LDMOS device - Google Patents
Structure for improving breakdown voltages of high-voltage LDMOS device Download PDFInfo
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- CN103579313A CN103579313A CN201210283176.3A CN201210283176A CN103579313A CN 103579313 A CN103579313 A CN 103579313A CN 201210283176 A CN201210283176 A CN 201210283176A CN 103579313 A CN103579313 A CN 103579313A
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Abstract
The invention discloses a structure for improving breakdown voltages of a high-voltage LDMOS device. The method includes the steps that a drift region which is composed of a deep trap is formed on a silicon substrate of the LDMOS device; a field oxide layer is formed in the deep trap, a buried layer is formed below the field oxide layer, a drain region polycrystal filed plate is formed on one side, close to a drain region, of the field oxide layer, and a grid electrode polycrystal filed plate is formed on the other side of the field oxide layer; a trap region is formed in the silicon substrate, a source region which is composed of a first doping region is formed in the trap region, and a drain region which is composed of a second doping region is formed in the deep trap; a source electrode is led out from the first doping region through a source region metal filed plate, and the drain region is connected with the drain region polycrystal filed plate through a drain region metal filed plate; a grid electrode metal filed plate is formed between the source region metal filed plate and the drain region metal filed plate; at least one field plate is further formed above the drift region. By the adoption of the structure, electric field distribution can be changed, the electric field intensity of the drift region is improved, meanwhile, the influence on the electric field intensity at the two ends of the source electrode and a drain electrode is small, the entire electric field integral area of the device is increased, and therefore the withstand voltage level of the high-voltage LDMOS device is effectively improved.
Description
Technical field
The present invention relates to semiconductor device structure, specifically belong to the structure and the method that improve superhigh pressure LDMOS device electric breakdown strength.
Background technology
LDMOS device, as shown in Figure 1, comprises P type silicon substrate 1, forms N-type deep trap 2 on silicon substrate 1, and this N-type deep trap 2 forms drift region; In deep trap 2, be formed with field oxide 4, field oxide 4 belows are formed with P+ buried regions 5, and this buried regions 5 does not longitudinally contact with field oxide 4.Near on a side field oxide 4 in drain region, be formed with drain region polycrystalline field plate 7, on opposite side field oxide 4, be formed with grid polycrystalline field plate 6.In silicon substrate 1, be formed with P type well region 3, well region 3 is drawn by the 3rd doped region 13 of P+, source is formed by the first doped region 8 of N+, and the first doped region 8 and the 3rd doped region 13 are laterally connected to form source region, forms the drain region being comprised of N+ the second doped region 9 in N-type deep trap 2.Source electrode is drawn by source region Metal field plate 11 in the first doped region 8 and the 3rd doped region 13, and the second doped region 9 is connected with drain region polycrystalline field plate 7 by drain region Metal field plate 10; Between source region Metal field plate 11 and drain region Metal field plate 10, be formed with gate metal field plate 12.
In the LDMOS device of high pressure (drain terminal voltage is greater than 20V) or even superhigh pressure (drain terminal voltage is greater than 400V), in order to improve the puncture voltage of device, conventionally in channel region part, form a longer drift region, when drain terminal making alive, drift region will exhaust completely, become ，Gai region, a space charge region and will present high-impedance state, thereby play a withstand voltage effect.Yet the concentration of drift region can not be too high, if too high, exhausting expansion can be too not wide, and space charge region is less, cause longitudinally when drain terminal adds high voltage, easily puncturing, thus certain withstand voltage in order to ensure, need lighter drift region concentration.But when the concentration of drift region is too low, the conducting resistance of drift region part will become greatly, the conducting resistance of whole device also will increase, and the power consumption of device itself can become greatly, and energy conversion efficiency reduces.In order to solve this contradiction, particularly for high-voltage LDMOS device, often in drift region, form a buried regions contrary with drift region concentration, this buried regions can exhaust with drift region, the concentration of drift region is improved, can not reduce puncture voltage again simultaneously, this technology can balance contradiction between withstand voltage and conducting resistance, be commonly referred to and reduce surface field technology (Reduced Surface Field is called for short RESURF).
In addition, field plate techniques is also a kind of technology that is usually used in improving device withstand voltage, conventionally in drain electrode, add a polycrystalline field plate 7 and Metal field plate 10, polycrystalline field plate 7 is directly connected with drain voltage by Metal field plate 10, can adopt polycrystalline field plate 6 and Metal field plate 12 near grid simultaneously.This field plate effect makes LDMOS device have similar mos capacitance structure, can carry out dividing potential drop, thereby reduces the peak value electric field of device, and the puncture voltage of device can be improved.Yet, in the marginal portion of field plate, because power line is more concentrated, have a peak electric field, in contrast to this, the most of region above drift region is without any field plate, electric field strength is just lower, causes the peak value electric field of resulting devices high in drain electrode and source electrode, middle low.As everyone knows, what the area integral below electric field was device is withstand voltage, so device is withstand voltage still limited.The high pressure NLDMOS device of take is example, and as shown in Figure 1, the simulation result of electric field as shown in Figure 2 for device architecture.In Fig. 2, in emulation, drain terminal has been made to the structure claiming with respect to source both sides, middle is source, both sides are drain terminal, from simulation result, the leakage two ends, electric field ratio source, drift region between drain-source two ends are low, and the area integral region below its electric field is that compressive resistance is limited.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of structure and method that improves high-voltage LDMOS device puncture voltage, can change the Electric Field Distribution of device, improves the electric field strength of device drift region and the withstand voltage level of device.
For solving the problems of the technologies described above, the structure of raising high-voltage LDMOS device puncture voltage of the present invention, described LDMOS device comprises the silicon substrate with the first conduction type, on silicon substrate, form a deep trap having with the second conduction type of the first conductivity type opposite, described deep trap forms drift region; In deep trap, be formed with field oxide, field oxide below is formed with the buried regions with the first conduction type, near on a side field oxide in drain region, is formed with drain region polycrystalline field plate, is formed with grid polycrystalline field plate on opposite side field oxide; In described silicon substrate, form the well region with the first conduction type, in well region, form the source region that the first doped region by the second conduction type forms, the drain region that in deep trap, formation is comprised of the second doped region of the second conduction type; Source electrode is drawn by source region Metal field plate in described the first doped region, and the second doped region is connected with drain region polycrystalline field plate by drain region Metal field plate; Between source region Metal field plate and drain region Metal field plate, be formed with gate metal field plate; Top, drift region is also formed with at least one field plate.
A kind of form preferably, the field oxide top of described drift region is formed with at least one polycrystalline field plate, described polycrystalline field plate is between grid polycrystalline field plate and drain region polycrystalline field plate, between gate metal field plate and drain region Metal field plate, be formed with a Metal field plate, described polycrystalline field plate can be connected with Metal field plate, and the current potential of polycrystalline field plate is identical with source current potential, or identical with grid potential, or current potential in addition separately, or do not add current potential and be floating dummy status.
The second form preferably, the field oxide top of described drift region is formed with at least one polycrystalline field plate, between described polycrystalline field plate and field oxide, form an oxide layer, polycrystalline field plate and oxide layer are between grid polycrystalline field plate and drain region polysilicon field plate, and described polycrystalline field plate is connected with drain region Metal field plate.
The third form preferably, on field oxide between described grid polycrystalline field plate and drain region polycrystalline field plate, be formed with the field plate of at least one highly resistant material, described high resistant field plate can be independent with one metal wire be connected, the current potential of this field plate is identical with source current potential, or identical with drain terminal current potential, or identical with grid potential, or give separately current potential, or do not connect current potential and be floating dummy status.
The 4th kind of form preferably, top, described drift region is formed with at least one Metal field plate, described Metal field plate is between gate metal field plate and drain region Metal field plate, the current potential of described Metal field plate is identical with source current potential, or identical with drain terminal current potential, or identical with grid potential, or give separately current potential, or do not connect current potential and be floating dummy status.
Wherein, described buried regions is positioned at the below of field oxide and does not longitudinally contact.Described the first conduction type is P type, and the second conduction type is N-type, or the first conduction type is N-type, and the second conduction type is P type.
The spacious region of the present invention on drift region adds suitable field plate, because the power line of field plate marginal portion is more concentrated, can form a peak electric field, therefore can change by these field plates the distribution of electric field, and then the electric field strength of raising drift region, these field plates are less on the electric field strength impact at leakage two ends, source simultaneously, and the whole field integral area of device is increased, and effectively improved the withstand voltage level of high-voltage LDMOS device.
Accompanying drawing explanation
Fig. 1 is the schematic cross-section of existing NLDMOS device;
Fig. 2 is the simulation result figure of the NLDMOS device peak value electric field of symmetrical structure;
Fig. 3 is the schematic cross-section of first embodiment of the invention;
Fig. 3 a to 3i is the device schematic cross-section that first embodiment of the invention forms technique;
Fig. 4 is the schematic cross-section of second embodiment of the invention;
Fig. 5 is the schematic cross-section of third embodiment of the invention;
Fig. 6 is the schematic cross-section of fourth embodiment of the invention.
Embodiment
Below in conjunction with accompanying drawing and embodiment, the present invention is further detailed explanation.
The structure of raising high-voltage LDMOS device puncture voltage provided by the invention, take NLDMOS device as example, and this NLDMOS device comprises P type silicon substrate, forms N-type deep trap on silicon substrate, and this N-type deep trap forms drift region; In deep trap, be formed with field oxide, field oxide below is formed with P+ buried regions, and this buried regions does not longitudinally contact with field oxide.Near on a side field oxide in drain region, be formed with drain region polycrystalline field plate, on opposite side field oxide, be formed with grid polycrystalline field plate, the field plate of at least one polycrystalline field plate or high resistant type on the zone line of field oxide.In silicon substrate, be formed with P type well region, well region is drawn by the 3rd doped region of P+, and source is formed by the first doped region of N+, and the first doped region and the 3rd doped region are laterally connected to form source region, forms the drain region being comprised of N+ the second doped region in N-type deep trap.Source electrode is drawn by source region Metal field plate in the first doped region and the 3rd doped region, and the second doped region is connected with drain region polycrystalline field plate by drain region Metal field plate; Between source region Metal field plate and drain region Metal field plate, be formed with gate metal field plate.
In the first embodiment, as shown in Figure 3, field oxide 104 tops of drift region are formed with at least one polycrystalline field plate 114, this polycrystalline field plate 114 is between grid polycrystalline field plate 106 and drain region polycrystalline field plate 107, between gate metal field plate 112 and drain region Metal field plate 110, be formed with a Metal field plate 115 simultaneously, this Metal field plate 115 is connected with polycrystalline field plate 114, polycrystalline field plate 114 can be identical with source current potential, can be identical with grid potential, also can be separately current potential or do not add current potential and be floating dummy status in addition.The production process of this structure comprises: 1) on P type silicon substrate 101, form N-type deep trap 102, N-type deep trap 102 forms drift region, as shown in Figure 3 a, 2) on P type silicon substrate 101, form P type well region 103, described P type well region 103 transversely has a segment distance with N-type deep trap 102, as shown in Figure 3 b, 3) above N-type deep trap 102, generate field oxide 104, as shown in Figure 3 c, 4) in N-type deep trap 102, by Implantation, form P+ buried regions 105, described P+ buried regions 105 is positioned at the below of field oxide 104, and longitudinally upper and field oxide 104 has a segment distance, as shown in Figure 3 d, 5) side field oxide 104 tops near P type well region 103 form grid polycrystalline field plate 106, and one end of grid polycrystalline field plate 106 is positioned on N-type deep trap 102, and the other end is positioned on P type well region 103, side field oxide 104 tops away from P type well region 103 form the drain region polycrystalline field plate 107 that highly resistant material is made, and are formed with polycrystalline field plate 114, as shown in Figure 3 e on the field oxide 104 between grid polycrystalline field plate 106 and drain region polycrystalline field plate 107, 6) carry out N-type Implantation, in the first doped region 108 of the interior formation of P type well region 103 N+, at N-type deep trap 102, near one end of drain region polycrystalline field plate 107, form the 109 formation drain regions, 109, the second doped regions, the second doped region of N+, as shown in Fig. 3 f simultaneously, 7) carry out P type Implantation, in 113, the first doped regions 108, the 3rd doped region of the interior formation of P type well region 103 P+, be laterally connected and form source region with the 3rd doped region 113, as shown in Fig. 3 g, 8) deposition of dielectric layer, adopt CMP(cmp) or Etch Back (anti-carving technology) formation contact hole, described contact hole communicates with the 3rd doped region 113, the first doped region 108, the second 109He drain region, doped region polycrystalline field plate 107 respectively, in contact hole, fill metal, as shown in Fig. 3 h, 9) dielectric layer surface forms source region Metal field plate 111 and the drain region Metal field plate 110 that is positioned at contact hole top, the second doped region 109 is connected with drain region polycrystalline field plate 107 by drain region Metal field plate 110, between source region Metal field plate 111 and drain region Metal field plate 110, be formed with gate metal field plate 112, between gate metal field plate 112 and drain region Metal field plate 110, be formed with a Metal field plate 115, this Metal field plate 115 is connected with polycrystalline field plate 114, polycrystalline field plate 114 can be identical with source current potential, can be identical with grid potential, also can be separately current potential or do not add current potential and be floating dummy status in addition, as shown in Fig. 3 i, 11) carry out device surface passivation technique, final device architecture as shown in Figure 3.
In the second embodiment, field oxide 204 tops of drift region are formed with at least one polycrystalline field plate 214, between described polycrystalline field plate 214 and field oxide 204, form an oxide layer 215, polycrystalline field plate 214 and oxide layer 215 are between grid polycrystalline field plate 206 and drain region polysilicon field plate 207, described polycrystalline field plate 214 is drain region with drain region polycrystalline field plate 207 with the second doped region 209(by drain region Metal field plate 210) be connected, wherein the thickness of the oxide layer 215 between polycrystalline field plate 214 and field oxide 204 and dielectric constant can regulate, to control the impact of drain terminal high voltage on electric field under the oxygen of field.The production process of this structure comprises: 1) on P type silicon substrate 201, form N-type deep trap 202, N-type deep trap 202 forms drift region; 2) on P type silicon substrate 201, form P type well region 203, described P type well region 203 transversely has a segment distance with N-type deep trap 202; 3) above N-type deep trap 202, generate field oxide 204; 4) in N-type deep trap 202, by Implantation, form P+ buried regions 205, described P+ buried regions 205 is positioned at the below of field oxide 204, and longitudinally upper and field oxide 204 has a segment distance; 5) side field oxide 204 tops near P type well region 203 form grid polycrystalline field plate 206, and one end of grid polycrystalline field plate 206 is positioned on N-type deep trap 202, and the other end is positioned on P type well region 203; Side field oxide 204 tops away from P type well region 203 form the drain region polycrystalline field plate 207 that highly resistant material is made; 6) on the field oxide 204 between grid polycrystalline field plate 206 and drain region polycrystalline field plate 207, form an oxide layer 215(as silicon dioxide layer), on it, form polycrystalline field plate 214; 7) carry out N-type Implantation, in the first doped region 208 of the interior formation of P type well region 203 N+, at N-type deep trap 202, near one end of drain region polycrystalline field plate 207, form the 209 formation drain regions, 209, the second doped regions, the second doped region of N+ simultaneously; 8) carry out P type Implantation, in 213, the first doped regions 208, the 3rd doped region of the interior formation of P type well region 203 P+, be laterally connected and form source region with the 3rd doped region 213; 9) deposition of dielectric layer, adopt CMP(cmp) or Etch Back (anti-carving technology) formation contact hole, described contact hole communicates with the 3rd doped region 213, the first doped region 208, the second doped region 209 and drain region polycrystalline field plate 207 and polycrystalline field plate 214 respectively, fills metal in contact hole; 10) dielectric layer surface forms source region Metal field plate 211 and the drain region Metal field plate 210 that is positioned at contact hole top, the second doped region 209 is connected with polycrystalline field plate 214 with drain region polycrystalline field plate 207 by drain region Metal field plate 210, between source region Metal field plate 211 and drain region Metal field plate 210, is formed with gate metal field plate 212; 11) carry out device surface passivation technique, final device architecture as shown in Figure 4.
In the 3rd embodiment, as shown in Figure 5, on field oxide 304 between grid polycrystalline field plate 306 and drain region polycrystalline field plate 307, be formed with the polycrystalline field plate 314 that at least one highly resistant material is made, described high resistant polycrystalline field plate 314 longitudinally directly contacts with field oxide 304, and the metal wire that described high resistant field plate 314 can be independent with is connected, and the current potential of this field plate can be identical with source current potential, or identical with drain terminal current potential, or identical with grid potential, or give separately current potential, or do not connect current potential and be floating dummy status.The production process of this structure comprises: 1) on P type silicon substrate 301, form N-type deep trap 302, N-type deep trap 302 forms drift region; 2) on P type silicon substrate 301, form P type well region 303, described P type well region 303 transversely has a segment distance (P type well region 303 also can be completed in N-type deep trap 302, and drift region surrounds the source region of follow-up formation and drain region wherein) with N-type deep trap 302; 3) above N-type deep trap 302, generate field oxide 304; 4) in N-type deep trap 302, by Implantation, form P+ buried regions 305, described P+ buried regions 305 is positioned at the below of field oxide 304, and longitudinally upper and field oxide 304 has a segment distance; 5) side field oxide 304 tops near P type well region 303 form grid polycrystalline field plate 306, and one end of grid polycrystalline field plate 306 is positioned on N-type deep trap 302, and the other end is positioned on P type well region 303; Side field oxide 304 tops away from P type well region 303 form the drain region polycrystalline field plate 307 that highly resistant material is made; Above the field oxide 304 between grid polycrystalline field plate 306 and drain region polycrystalline field plate 307, form the polycrystalline field plate 314 that highly resistant material is made simultaneously; 6) carry out N-type Implantation, in the interior formation of P type well region 303 the first doped region 308, simultaneously at N-type deep trap 302, near the one end in drain region, form the second doped region 309; 7) carry out P type Implantation, in 313, the first doped regions 308, P type well region 303 interior formation the 3rd doped region, be laterally connected and form source region with the 3rd doped region 313; 8) deposition of dielectric layer, adopt CMP(cmp) or Etch Back (anti-carving technology) formation contact hole, described contact hole communicates with the 3rd doped region 313, the first doped region 308, the second 309He drain region, doped region polycrystalline field plate 307 respectively, fills metal in contact hole; 9) dielectric layer surface forms source region Metal field plate 311 and the drain region Metal field plate 310 that is positioned at contact hole top, the second doped region 309 is connected with drain region polycrystalline field plate 307 by drain region Metal field plate 310, between source region Metal field plate 311 and drain region Metal field plate 310, be formed with gate metal field plate 312, high resistant polycrystalline field plate 314 is connected with gate metal field plate 312; 10) carry out device surface passivation technique, final device architecture as shown in Figure 5.
In the 4th embodiment, as shown in Figure 6, between gate metal field plate 412 and drain region Metal field plate 410, be formed with at least one Metal field plate 415, the current potential of this Metal field plate 415 is identical with source current potential, or identical with drain terminal current potential, or identical with grid potential, or give separately current potential, or do not connect current potential and be floating dummy status.The production process of this structure comprises: 1) on P type silicon substrate 401, form N-type deep trap 402, N-type deep trap 402 forms drift region; 2) on P type silicon substrate 401, form P type well region 403, described P type well region 403 transversely has a segment distance (P type well region 403 also can be completed in N-type deep trap 402, and drift region surrounds the source region of follow-up formation and drain region wherein) with N-type deep trap 402; 3) above N-type deep trap 402, generate field oxide 404; 4) in N-type deep trap 402, by Implantation, form P+ buried regions 405, described P+ buried regions 405 is positioned at the below of field oxide 404, and longitudinally upper and field oxide 404 has a segment distance; 5) side field oxide 404 tops near P type well region 403 form grid polycrystalline field plate 406, and one end of grid polycrystalline field plate 406 is positioned on N-type deep trap 402, and the other end is positioned on P type well region 403; Side field oxide 404 tops away from P type well region 403 form the drain region polycrystalline field plate 407 that highly resistant material is made; 6) carry out N-type Implantation, in the interior formation of P type well region 403 the first doped region 408, simultaneously at N-type deep trap 402, near the one end in drain region, form the second doped region 409; 7) carry out P type Implantation, in 413, the first doped regions 408, P type well region 403 interior formation the 3rd doped region, be laterally connected and form source region with the 3rd doped region 413; 8) deposition of dielectric layer, adopt CMP(cmp) or Etch Back (anti-carving technology) formation contact hole, described contact hole communicates with the 3rd doped region 413, the first doped region 408, the second 409He drain region, doped region polycrystalline field plate 407 respectively, fills metal in contact hole; 9) dielectric layer surface forms source region Metal field plate 411 and the drain region Metal field plate 410 that is positioned at contact hole top, the second doped region 409 is connected with drain region polycrystalline field plate 407 by drain region Metal field plate 410, between source region Metal field plate 411 and drain region Metal field plate 410, be formed with gate metal field plate 412, between gate metal field plate 412 and drain region Metal field plate 410, be formed with a Metal field plate 415; 10) carry out device surface passivation technique, final device architecture as shown in Figure 6.
In above-mentioned NLDMOS device, convert each injection region ionic type, can form PLDMOS device.
The spacious region of the present invention on drift region increases field plate, by quantity, position and the size of field plate, can change the Electric Field Distribution of drift region, improve the electric field strength of drift region part, thereby the area integral below the whole electric field of device is increased, thereby improve the withstand voltage level of device.The field plate that drift region increases has various ways, and it can be connected with source metal according to actual needs, also can be connected with grid end metal, even can be connected with drain terminal metal, and under different connected modes, the structure &processes of field plate techniques is not identical yet.Field plate in the present invention can be one, also can be many, if many, its width dimensions and mutual interval can be set to identical or different according to actual needs.
By specific embodiment, the present invention is had been described in detail above, but these are not construed as limiting the invention.Without departing from the principles of the present invention, those skilled in the art can make many distortion and improvement to conductive resistance coefficient, quantity, position and the annexation of field plate, and these also should be considered as protection scope of the present invention.
Claims (8)
1. a structure that improves high-voltage LDMOS device puncture voltage, is characterized in that:
Described LDMOS device comprises the silicon substrate with the first conduction type, forms a deep trap having with the second conduction type of the first conductivity type opposite on silicon substrate, and described deep trap forms drift region; In deep trap, be formed with field oxide, field oxide below is formed with the buried regions with the first conduction type, near on a side field oxide in drain region, is formed with drain region polycrystalline field plate, is formed with grid polycrystalline field plate on opposite side field oxide;
In described silicon substrate, form the well region with the first conduction type, in well region, form the source region that the first doped region by the second conduction type forms, the drain region that in deep trap, formation is comprised of the second doped region of the second conduction type; Source electrode is drawn by source region Metal field plate in described the first doped region, and the second doped region is connected with drain region polycrystalline field plate by drain region Metal field plate; Between source region Metal field plate and drain region Metal field plate, be formed with gate metal field plate;
Top, drift region is also formed with at least one field plate.
2. the structure of raising high-voltage LDMOS device puncture voltage according to claim 1, it is characterized in that: the field oxide top of described drift region is formed with at least one polycrystalline field plate, described polycrystalline field plate is between grid polycrystalline field plate and drain region polycrystalline field plate, between gate metal field plate and drain region Metal field plate, be formed with a Metal field plate, described polycrystalline field plate can be connected with Metal field plate, the current potential of polycrystalline field plate is identical with source current potential, or identical with grid potential, or current potential in addition separately, or do not add current potential and be floating dummy status.
3. the structure of raising high-voltage LDMOS device puncture voltage according to claim 1, it is characterized in that: the field oxide top of described drift region is formed with at least one polycrystalline field plate, between described polycrystalline field plate and field oxide, form an oxide layer, polycrystalline field plate and oxide layer are between grid polycrystalline field plate and drain region polysilicon field plate, and described polycrystalline field plate is connected with drain region Metal field plate.
4. the structure of raising high-voltage LDMOS device puncture voltage according to claim 1, it is characterized in that: the field plate that is formed with at least one highly resistant material on the field oxide between described grid polycrystalline field plate and drain region polycrystalline field plate, described high resistant field plate can be independent with one metal wire be connected, the current potential of this field plate is identical with source current potential, or identical with drain terminal current potential, or identical with grid potential, or give separately current potential, or do not connect current potential and be floating dummy status.
5. the structure of raising high-voltage LDMOS device puncture voltage according to claim 1, it is characterized in that: top, described drift region is formed with at least one Metal field plate, described Metal field plate is between gate metal field plate and drain region Metal field plate, the current potential of described Metal field plate is identical with source current potential, or identical with drain terminal current potential, or identical with grid potential, or give separately current potential, or do not connect current potential and be floating dummy status.
6. according to the structure of the raising high-voltage LDMOS device puncture voltage described in any one in claim 1 to 5, it is characterized in that: described buried regions is positioned at the below of field oxide and does not longitudinally contact.
7. according to the structure of the raising high-voltage LDMOS device puncture voltage described in any one in claim 1 to 5, it is characterized in that: described the first conduction type is P type, the second conduction type is N-type.
8. according to the structure of the raising high-voltage LDMOS device puncture voltage described in any one in claim 1 to 5, it is characterized in that: described the first conduction type is N-type, the second conduction type is P type.
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| CN104064602A (en) * | 2014-07-08 | 2014-09-24 | 苏州卓能微电子技术有限公司 | LDMOS structure applicable to LED driving circuit |
| CN104617148A (en) * | 2015-01-30 | 2015-05-13 | 上海华虹宏力半导体制造有限公司 | Isolation N-type laterally diffused metal oxide semiconductor (NLDMOS) device and manufacturing method thereof |
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| CN110634834A (en) * | 2018-06-25 | 2019-12-31 | 世界先进积体电路股份有限公司 | Semiconductor structure |
| CN110634834B (en) * | 2018-06-25 | 2021-10-08 | 世界先进积体电路股份有限公司 | Semiconductor structure |
| CN109411527A (en) * | 2018-09-22 | 2019-03-01 | 天津大学 | A kind of N-type LDMOS using reduction surface field technology |
| CN111162124A (en) * | 2018-11-08 | 2020-05-15 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN111162124B (en) * | 2018-11-08 | 2023-10-17 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN112750911A (en) * | 2021-02-03 | 2021-05-04 | 南京邮电大学 | LDMOS with controllable three-dimensional electric field and preparation method thereof |
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