CN103631161A

CN103631161A - Filtering method based on state machine

Info

Publication number: CN103631161A
Application number: CN201310424881.5A
Authority: CN
Inventors: 王建群; 吴清扬; 曹宁; 薛晓卿; 柴瑞
Original assignee: Beijing Institute of Technology BIT
Current assignee: Beijing Institute of Technology BIT
Priority date: 2013-09-17
Filing date: 2013-09-17
Publication date: 2014-03-12

Abstract

A digital filtering technology applying and detecting transient pulses in signals uses a CPLD as hardware to detect the width of transient pulses in signals, filter small-width pulses and output wide pulses through a state-machine-based method under the drive of a high-frequency clock. According to the method, an appropriate filter width n is selected first, and the number of states of the state machine is S0-Sn. When the width after signal mutation is within a filter width range and if an output signal is not consistent with an input signal, the state machine is switched from the state S(k-1) to Sk, namely, the accumulated width after signal mutation is added with 1, or the state machine returns to the state S0, and at the moment, output is consistent with historical output. When the width after signal mutation is not within the filter width range and if the output signal is not consistent with the input signal, the state machine is switched from the state Sn to the state S0, and at the moment, the output signal is consistent with the input signal. The filtering method based on the state machine has been applied to speed detection of a military vehicle and has achieved the expected effect.

Description

A kind of filtering method based on state machine

Technical field:

The invention belongs to a kind of digital filtering technique, in software, the data that collect are eliminated to the processing of disturbing.

Background technology

When test macro obtains data from the external world, severe due to working site environment, usually has adding of some random disturbance, noise signal.Some undesired signal is often irregular, so just to test macro, has brought error.In order to overcome these errors, except hardware filtering, also have digital filtering, by certain calculation procedure, the data that gather are carried out to certain processing, thereby eliminate or weaken the impact of interference noise.Digital filtering is realized by software algorithm, compares with hardware filtering, does not need to increase hardware device, only need before program enters control algolithm, add the program of a piece of digital filtering.At present, SCM Based digital filtering method has a variety of, and classical has: arithmetic mean law is the different time sampling in one-period, then asks its mean value, and this method can effectively be eliminated the interference of preiodic type; Median filtering method, is that the variate-value in several cycles that collect is sorted, and then gets the intermediate value of the value that sequences order, and this method can effectively prevent that the data that are subject to bursty interference from entering.But these methods all could not effectively solve the filtering of square-wave signal in speed of a motor vehicle detection at present.

Summary of the invention

The invention provides a kind of digital filtering technique can be used in industrial controlling software.This technology is under high frequency clock drives, and by transient pulse width in the method detection signal of state machine, the pulse that filtering width is short, exports broad pulse.The present invention has applied to the speed of a motor vehicle of certain military vehicle and has processed, and obtains better effects.

In the speed of a motor vehicle detects, for obtaining the accurate speed of a motor vehicle, need to process the signal period collecting.The measurement in cycle does not need to obtain the accurate numerical value of external signal, only needs to export 1 when the signal collecting is high level, during for low level, exports 0.But in actual acquisition process, due to the deficiency of collecting device self and the interference of environment, inevitably can produce various burrs, the measuring accuracy in cycle is affected.In order to address this problem, the present invention proposes the filtering method based on state machine.The thought of the method is, supposes that the width of burr is less than filter width n, when input signal, do not undergo mutation, and thinks that input signal is actual signal; When input signal is undergone mutation, adopt counter, the deration of signal after sudden change is counted.If counting width is less than filter width, think that this sudden change is caused by burr, to its filtering, if counting width is greater than filter width, think that this sports real sign mutation.The technical scheme of the method is: introduce sign mutation width variable St afterwards, suppose that the state conversion of this sequential circuit occurs in the rising edge of CP.According to filter width n, St is divided into S ₀to S _nindividual state.When input signal is not undergone mutation, St keeps S always ₀state.When signal is undergone mutation, suppose to be currently output as low level CLKA_filt=0, and CLKA=1 while being input as high level, St is by state S ₀become state S ₁, physical significance, for the signal accumulative total width after sudden change is 1, is less than filter width, and now output still keeps low level CLKA_filt=0.When second rising edge clock arrives, CLKA=1 when input is still high level, St is by state S ₁become state S ₂, physical significance, for signal accumulative total width after sudden change is 2, is less than filter width, output low level CLKA_filt=0; If at this moment be input as low level CLKA=0, St is by state S ₁become state S ₀, the deration of signal that physical significance is this sudden change is less than filter width, is judged as burr signal, carries out filtering, output low level CLKA_filt=0.By that analogy, at the k(1～n) individual rising edge clock is when arrive, and is input as high level if current, and St is by state S _k-1become state S _k, output low level; If current, be input as low level, St is by state S _kbecome state S ₀, output low level.When St has been S _nstate, if when next rising edge clock arrives, input is still high level, St is by state S _nbecome state S ₀, output high level, physical significance is that the accumulative total width after sign mutation is greater than filter width, is judged as true sudden change, otherwise gets back to S ₀state, output low level.The state transition table of this state machine is in Table (one).

Table one: state-transition table (CLKA_filt is output, and CLKA is input)

Accompanying drawing explanation

Fig. 1 is the St state transition diagram of state machine.Be wherein state in circle, arrow is state conversion direction, and xx/x represents respectively the output of previous moment, current input, current output.

embodiment

The present invention adopts verilog language to realize this function, and its filter mainly realizes by nested if statement.Concrete methods of realizing is as follows: when rising edge arrives, first judge the level of current output, if current output state is low level, whether judgement input is low level, if so, keep output low level state zero clearing, continue to wait for subsequently the arrival on clock edge; If not, see whether high level state arrives, and whether counter reaches filter width: if be less than filter width, keep output low level, counter adds 1, otherwise output high level and counter O reset.Wait for the arrival of next rising edge.If current output state is high level, whether judgement input is high level, if so, keeps output high level state zero clearing, continues to wait for subsequently the arrival on clock edge; If not, see whether low level state arrives, and whether counter reaches filter width: if be less than filter width, keep output high level, counter adds 1, otherwise output low level and counter O reset.Continue to wait for the arrival of next rising edge.

Specific procedure following (7 is filter width):

Claims

1. a digital filtering technique for the transient pulse in application and detection signal, is characterized in that usining that CPLD is as hardware, under high frequency clock drives, and by transient pulse width in the method detection signal of state machine, the pulse that filtering width is short, output broad pulse.This state machine has memory function, i.e. the output in its arbitrary moment is not only relevant with current input, also relevant with the state in a upper moment.Use this state machine first to choose suitable filter width, the width after sign mutation is less than filter width, thinks burr, carries out filtering, if the width after sign mutation is greater than filter width, thinks actual signal, and output.

2. as claimed in claim 1, it is characterized in that being applied to the transient signal in detection signal, filter the short pulse of width, output broad pulse.

3. as claimed in claim 1, it is characterized in that it is a digital filtering technique of being realized by programmed algorithm, this program is driven by high frequency clock, according to actual needs, can, at rising edge or the falling edge working procedure of clock, realize filter function.

4. as claimed in claim 1, it is characterized in that this state machine memory function, the output in its arbitrary moment, not only relevant with current input, also relevant with the output in a upper moment.

5. as claimed in claim 1, the status number of this state machine determines by filter width n, and state is S ₀～S _n.State S _k(k=0,1 ... n) be defined as, the accumulative total width after input signal sudden change is k.

6. as described in claim 4,5, the state transformation rule of state machine is:

When rising edge clock/negative edge arrives

Step 1: judged whether reset signal, if having, state returns S ₀state, output zero clearing, waits for next clock edge, otherwise enters step 2;

Step 2: judge whether current output is high level (low level);

Step 3: if output is high level (low level), whether judgement input is high level (low level);

Step 4: if input is high level (low level), current state S _kbeing converted to next state is S ₀, output high level (low level);

Step 5: if the low level of being input as (high level) judges whether current state is S _n, if so, S _nbe converted to next state S ₀, output low level, (high level), otherwise current state S _kbeing converted to next state is S _k+1, output high level (low level).