CN103675376A

CN103675376A - Semiconductor device with microprobe and its manufacturing method

Info

Publication number: CN103675376A
Application number: CN201210394101.2A
Authority: CN
Inventors: 程吕义; 邱启新; 邱世冠
Original assignee: Siliconware Precision Industries Co Ltd
Current assignee: Siliconware Precision Industries Co Ltd
Priority date: 2012-09-19
Filing date: 2012-10-16
Publication date: 2014-03-26
Anticipated expiration: 2032-10-16
Also published as: CN103675376B; TW201413250A; TWI447399B

Abstract

A semiconductor device having a microprobe and a method of fabricating the same, the semiconductor device comprising: a substrate having a first surface and a second surface opposite to each other; a first circuit layer formed on the first surface of the substrate; a first dielectric layer formed on the first surface of the substrate and the first circuit layer and having a first opening exposing the first circuit layer; a second circuit layer formed on the first dielectric layer and in the first opening; an insulating buffer layer formed on the first dielectric layer and the second circuit layer and having at least one opening exposing the second circuit layer; a third wiring layer formed on the insulating buffer layer and in the insulating buffer layer opening; a second dielectric layer formed on the insulating buffer layer and the third circuit layer and having at least one second opening exposing the third circuit layer; and a microprobe disposed in the second opening of the second dielectric layer. The invention can effectively buffer the external force applied to the microprobe and avoid elastic fatigue.

Description

Semiconductor device and the method for making thereof with microprobe

Technical field

The present invention is about a kind of semiconductor device and method for making thereof, and in more detail, the present invention is a kind of semiconductor device and method for making thereof with the microprobe of resistance to elastic fatigue.

Background technology

Now, along with the progress of development in science and technology, the dealer of electronic product develop one after another various different kenels in order to test the test probe card of electronic product.The method for making of conventional probe card because of probe size enjoy restriction and cost of manufacture higher, so need to overcome many bottlenecks in making the process of probe.And the size trend of current semi-conductor chip is tending towards microminiaturization and this semi-conductor chip output contact is more and more many, test probe structure is all formed by tiny probe wiring one by one again, therefore, must constantly improve and the technology that overcomes probe structure, to coordinate with the semi-conductor chip of microminiaturization, and overcome the conventional probe structure problem that easily generation is tired and probe size is limited when operation, to meet the trend of modern science and technology product.

8001685B2 United States Patent (USP) discloses a kind of method for making of probe, refers to 1A to 1K and schemes, and is the diagrammatic cross-section of the method for making of existing probe.

As shown in Figure 1A to Fig. 1 C, one stack of ceramic plates 10 is provided, and form the first conductive layer 12 in the end face of this stack of ceramic plates 10, and on this first conductive layer 12, form the first resistance layer 14, and prior to removing this first resistance layer 14 of part on this first conductive layer 12, and this first conductive layer 12 of exposed parts, then this first conductive layer 12 of the part exposing is removed, then remove this first resistance layer 14, above-mentioned technique is defined as step 1 again.

If Figure 1A ' is to as shown in Fig. 1 C ', semiconductor chip 10 ' is provided, and the end face in this semi-conductor chip 10 ' forms photoresist layer 12 ', this photoresist layer 12 ' of patterning forms a plurality of openings 121 ' with the end face in this semi-conductor chip 10 ' again, then, utilize macromolecular elastomer 14 ' to incite somebody to action respectively this opening 121 ' and fill up, above-mentioned technique is defined as step 2.

As shown in Fig. 1 D, in the structure of Fig. 1 C that this macromolecular elastomer 14 ' of the structure of Fig. 1 C ' of step 2 is posted in step 1, make this macromolecular elastomer 14 ' be located at the end face of this stack of ceramic plates 10, and this macromolecular elastomer 14 ' have the first perforate 122 of the first conductive layer 12 of the end face that exposes this stack of ceramic plates 10.

As shown in Fig. 1 E, on this first conductive layer 12, form the first metal layer 15, and the bottom of this first metal layer 15 is nickel dam 151, and top layer is gold layer 152.

As shown in Fig. 1 F, on this macromolecular elastomer 14 ' and this gold layer 152, form the second conductive layer 16, and be provided with the second resistance layer 141 in this second conductive layer 16.

As shown in Figure 1 G, this second resistance layer 141 of patterning to be to form the perforate of this second conductive layer 16 of exposed parts, then on this second conductive layer 16, forms the second metal level 18.

As shown in Fig. 1 H, in this second resistance layer 141, be provided with the 3rd resistance layer 142 with this second metal level 18, and patterning the 3rd resistance layer 142 is to form the opening that exposes this second metal level 18, then, forms the 3rd metal level 181 on this second metal level 18.

As shown in Figure 1 I, in the 3rd resistance layer 142, be provided with the 4th resistance layer 143 with the 3rd metal level 181, and patterning the 4th resistance layer 143 is to form the opening that exposes the 3rd metal level 181, then, forms the 4th metal level 182 on the 3rd metal level 181.

As shown in Fig. 1 J, in the 4th resistance layer 143, be provided with the 5th resistance layer 144 with the 4th metal level 182, and patterning the 4th resistance layer 143 is to form the opening that exposes the 4th metal level 182, then, on the 4th metal level 182, forms probe projection 183.

As shown in Fig. 1 K, this second resistance layer 141, the 3rd resistance layer 142, the 4th resistance layer 143 and the 5th resistance layer 144 are removed, and complete probe.

But; the method for making of aforementioned existing probe needs the structure of step 1 to be posted the structure to step 2; use semiconductor core blade technolgy and stack of ceramic plates technique simultaneously; cause that integrated artistic is more complicated, yield is poor and Production Time is elongated; cause the problems such as cost raising; moreover existing probe is because structure is tiny and probe base partial suspended does not have cushion protection, therefore easily produce the disappearances such as elastic fatigue or damage when operation is mobile.

Therefore, how overcoming the variety of problems of prior art, is an important topic in fact.

Summary of the invention

For solving the variety of problems of above-mentioned prior art, fundamental purpose of the present invention is to disclose a kind of semiconductor device and method for making thereof with microprobe, can effectively cushion the suffered external force of microprobe and avoid elastic fatigue.

The semiconductor device with microprobe of the present invention comprises: substrate, has relative first surface and second surface; The first line layer, is formed on the first surface of this substrate; The first dielectric layer, is formed on the first surface and this first line layer of this substrate, and has the first perforate that exposes this first line layer; The second line layer, be formed on this first dielectric layer with this first perforate in; Buffer insulation layer, is formed on this first dielectric layer and this second line layer, and has at least one buffer insulation layer perforate that exposes this second line layer; Tertiary circuit layer, be formed on this buffer insulation layer with this buffer insulation layer perforate in; The second dielectric layer, is formed on this buffer insulation layer and this tertiary circuit layer, and has at least one the second perforate that exposes this tertiary circuit layer; And microprobe, be located in the second perforate of this second dielectric layer, and protrude from this second dielectric layer.

The present invention provides again a kind of method for making with the semiconductor device of microprobe, comprising: in one, have on the first surface of substrate of relative first surface and second surface and form the first line layer; On the first surface of this substrate and this first line layer, form the first dielectric layer, this first dielectric layer also has the first perforate that exposes this first line layer; Form the second line layer on this first dielectric layer with this first perforate in; On this first dielectric layer and this second line layer, form a buffer insulation layer, this buffer insulation layer also has at least one buffer insulation layer perforate that exposes this second line layer; Form tertiary circuit layer on this buffer insulation layer with this buffer insulation layer perforate in; On this buffer insulation layer and this tertiary circuit layer, form the second dielectric layer, this second dielectric layer also has at least one the second perforate that exposes this tertiary circuit layer; And form microprobe in the second perforate of this second dielectric layer, and this microprobe protrudes from this second dielectric layer.

In the method for making of the aforesaid semiconductor device with microprobe, this first line layer, this second line layer and this tertiary circuit layer and this microprobe are to form by plating mode.

In the method for making of the aforesaid semiconductor device with microprobe, the position of this buffer insulation layer perforate is not to position that should the first perforate, and the position of this second perforate is to should the perforate of buffer insulation layer, the position of this first perforate is to position that should the second perforate again.

In the method for making of the aforesaid semiconductor device with microprobe, this buffer insulation layer has two these buffer insulation layer perforates, and two these buffer insulation layer perforates are to connect by this tertiary circuit layer, and this microprobe is electrically connected this tertiary circuit layer.

In the method for making of the aforesaid semiconductor device with microprobe, be also included in and in this second perforate, be formed with the 4th line layer, and this microprobe is electrically connected the 4th line layer.

In the method for making of the aforesaid semiconductor device with microprobe, the material of this buffer insulation layer is BCB(benzocyclobutene, Benzocyclo-buthene), polyimide (PI) or polybenzoxazoles (polybenzoxazole, PBO).

In the method for making of the aforesaid semiconductor device with microprobe, the material of this microprobe is tungsten (W), rhenium (Re), beryllium (Be), palladium (Pd), titanium-tungsten (TiW), tungsten-rhenium alloy (ReW) or beallon (BeCu).

According to the above, bow type underlying structure and buffer insulation layer that the semiconductor device that utilization of the present invention has a microprobe has syllogic are subject to the problem of elastic fatigue or damage to reduce microprobe structure when operation is mobile, the present invention more can produce the microprobe structure of high density (for example the spacing of each microprobe is less than 40 microns) and microminiaturization, to expand test area, increase test contacts pin number (being greater than 10000 microprobe numbers).

Accompanying drawing explanation

Figure 1A to Fig. 1 K is for showing the diagrammatic cross-section of the method for making of existing microprobe card, and Figure 1A to Fig. 1 C is for showing the diagrammatic cross-section of step 1 method for making of existing microprobe card, Figure 1A ' to Fig. 1 C ' for showing the diagrammatic cross-section of step 2 method for making of existing microprobe card.

Fig. 2 A to Fig. 2 U is the diagrammatic cross-section with the semiconductor device of microprobe and the first embodiment of method for making thereof of the present invention.

Fig. 3 is the diagrammatic cross-section with the semiconductor device of microprobe and the second embodiment of method for making thereof of the present invention.

Fig. 4 is the diagrammatic cross-section with the semiconductor device of microprobe and the 3rd embodiment of method for making thereof of the present invention.

Fig. 5 is the diagrammatic cross-section with the semiconductor device of microprobe and the 4th embodiment of method for making thereof of the present invention.

Primary clustering symbol description

10 stack of ceramic plates

10 ' semi-conductor chip

12,214 first conductive layers

122,212 first perforates

12 ' photoresist layer

121 ' opening

14,202 first resistance layers

141,23 second resistance layers

142,26 the 3rd resistance layers

143,29 the 4th resistance layers

144,31 the 5th resistance layers

14 ' macromolecular elastomer

15 the first metal layers

151 nickel dams

152 gold medal layers

16,244 second conductive layers

18 second metal levels

181 the 3rd metal levels

182 the 4th metal levels

183 probe projections

20 base materials

20a first surface

20b second surface

201 the first metal layers

The 201 ' first line layer

2020 first resistance layer perforates

203 conductive through holes

204 polymer material layers

205 the 3rd perforates

206 soldering projections

21 first dielectric layers

22 second metal levels

The 22 ' second line layer

24 buffer insulation layers

242 buffer insulation layer perforate

25 the 3rd metal levels

25 ' tertiary circuit layer

27 second dielectric layers

272 second perforates

274 the 3rd conductive layers

28 the 4th metal levels

The 28 ' the 4th line layer

30 microprobes

32 bonding wires.

Embodiment

By particular specific embodiment explanation embodiments of the present invention, those skilled in the art can understand other advantage of the present invention and effect easily by content disclosed in the present specification below.

Notice, appended graphic the illustrated structure of this instructions, ratio, size etc., equal contents in order to coordinate instructions to disclose only, understanding and reading for those skilled in the art, not in order to limit the enforceable qualifications of the present invention, therefore the technical essential meaning of tool not, the adjustment of the modification of any structure, the change of proportionate relationship or size, not affecting under the effect that the present invention can produce and the object that can reach, all should still drop on disclosed technology contents and obtain in the scope that can contain.Simultaneously, in this instructions, quote as " on ", " top ", " end ", " one's " and " two " etc. term, also only for ease of understanding of narrating, but not in order to limit the enforceable scope of the present invention, the change of its relativeness or adjustment, under without essence change technology contents, when being also considered as the enforceable category of the present invention.

The first embodiment

To coordinate Fig. 2 A to Fig. 2 U to describe the diagrammatic cross-section with the semiconductor device of microprobe and the first embodiment of method for making thereof of the present invention in detail below.

As shown in Figure 2 A, provide one to there is relative first surface 20a and the substrate 20 of second surface 20b, in the upper the first metal layer 201 that forms of this first surface 20a.

Also refer to Fig. 2 B, it continues from Fig. 2 A, forms the first resistance layer 202 on this first metal layer 201, and this first resistance layer 202 has the first resistance layer perforate 2020 of this first metal layer 201 of exposed parts.

As shown in Figure 2 C, it continues from the technique of Fig. 2 B, removes the first metal layer 201 in this first resistance layer perforate 2020, to form the first line layer 201 ', and removes this first resistance layer 202.

As shown in Figure 2 D, it continues from the technique of Fig. 2 C, in the first surface 20a of this substrate 20 and this first line layer 201 ' is upper forms the first dielectric layer 21, and this first dielectric layer 21 there is the first perforate 212 that exposes this first line layer 201 '.

As shown in Figure 2 E, it continues from the technique of Fig. 2 D, on this first dielectric layer 21, above in for example mode of sputter copper/nickel/gold, forms the first conductive layer 214 with this first line layer 201 '.

As shown in Figure 2 F, it continues from the technique of Fig. 2 E, on this first conductive layer 214, in for example mode of copper plating or electroplated aluminum, forms the second metal level 22.

As shown in Figure 2 G, it continues from the technique of Fig. 2 F, forms the second resistance layer 23 of this second metal level 22 of exposed parts on this second metal level 22.

As shown in Fig. 2 H, it continues from the technique of Fig. 2 G, removes this second metal level 22 and the first conductive layer 214 that by this second resistance layer 23, are not covered, to form the second line layer 22 ' that is electrically connected this first line layer 201 ', then removes this second resistance layer 23.

As shown in Fig. 2 I, it continues from the technique of Fig. 2 H, in this first dielectric layer 21 and the upper buffer insulation layer 24 that forms of this second line layer 22 ', this buffer insulation layer 24 also has at least one buffer insulation layer perforate 242 exposing on this second line layer 22 ', wherein, the position of this buffer insulation layer perforate 242 is not to position that should the first perforate 212, and the material of this buffer insulation layer 24 is BCB(benzocyclobutene, Benzocyclo-buthene), polyimide (PI) or polybenzoxazoles (polybenzoxazole, PBO).

As shown in Fig. 2 J, it continues from the technique of Fig. 2 I, in this buffer insulation layer 24 and this second line layer 22 ', above in for example mode of sputter copper/nickel/gold, forms the second conductive layer 244.

As shown in Fig. 2 K, it continues from the technique of Fig. 2 J, on this second conductive layer 244, with plating mode, forms the 3rd metal level 25.

As shown in Fig. 2 L, it continues from the technique of Fig. 2 K, forms the 3rd resistance layer 26 of exposed parts the 3rd metal level 25 on the 3rd metal level 25.

As shown in Fig. 2 M, it continues from the technique of Fig. 2 L, remove part the 3rd metal level 25 and the second conductive layer 244 that by the 3rd resistance layer 26, are not covered, to form the tertiary circuit layer 25 ' that is electrically connected this second line layer 22 ', and this buffer insulation layer 24 of exposed parts, then remove the 3rd resistance layer 26.

As shown in Fig. 2 N, it continues from the technique of Fig. 2 M, in this buffer insulation layer 24 and upper second dielectric layer 27 that forms of this tertiary circuit layer 25 ', this second dielectric layer 27 also has at least one the second perforate 272 that exposes this tertiary circuit layer 25 ', wherein, the position of this second perforate 272 is to position that should the first perforate 212, and the position of this second perforate 272 is not to should buffer insulation layer perforate 242.

As shown in Figure 2 O, it continues from the technique of Fig. 2 N, on this second dielectric layer 27, above in for example mode of sputter copper/nickel/gold, forms the 3rd conductive layer 274 with this tertiary circuit layer 25 '.

As shown in Fig. 2 P, it continues from the technique of Fig. 2 O, on the 3rd conductive layer 274, with plating mode, forms the 4th metal level 28.

As shown in Fig. 2 Q, it continues from the technique of Fig. 2 P, forms the 4th resistance layer 29 on the 4th metal level 28, and exposes the 4th metal level 28 in this second perforate 272.

As shown in Fig. 2 R, it continues from the technique of Fig. 2 Q, on the 4th metal level 28, with plating mode, form microprobe 30, and the material of this microprobe 30 is tungsten (W), rhenium (Re), beryllium (Be), palladium (Pd), titanium-tungsten (TiW), tungsten-rhenium alloy (ReW) or beallon (BeCu).

As shown in Fig. 2 S, it continues from the technique of Fig. 2 R, removes the 4th resistance layer 29.

As shown in Fig. 2 T, it continues from the technique of Fig. 2 S, forms the 5th resistance layer 31 on this microprobe 30.

As shown in Fig. 2 U, it continues from the technique of Fig. 2 T, removes the 4th metal level 28 and the 3rd conductive layer 274 that by the 5th resistance layer 31, are not covered, to form the 4th line layer 28 ', and removes the 5th resistance layer 31, and this microprobe 30 is exposed; Again, the 4th line layer 28 ' is formed in this second perforate 272, and this microprobe 30 is electrically connected the 4th line layer 28 '.

The second embodiment

Refer to Fig. 3, it is the diagrammatic cross-section of the second embodiment of the semiconductor device with microprobe of the present invention.The difference of the present embodiment and above-described embodiment is: this first line layer 201 ' of part stretches out along the semiconductor device sidepiece (not icon) of this microprobe, can be in the upper bonding wire 32 that is electrically connected of this first line layer 201 ' that exposes to atmosphere, for external electric connection.All similar as for other related process, therefore repeat no more.

The 3rd embodiment

Refer to Fig. 4, it is the diagrammatic cross-section of the 3rd embodiment of the semiconductor device with microprobe of the present invention.The difference of the present embodiment and the first embodiment is: this substrate 20 also has the conductive through hole 203 that runs through this first surface 20a and second surface 20b and be electrically connected this first line layer 201 ', and upper with polyimide (PI) material formation polymer material layer 204 in the second surface 20b of this substrate 20, and the correspondence that has this polymer material layer 204 exposes the 3rd perforate 205 of this conductive through hole 203, and soldering projection 206 is set on this conductive through hole 203 to be electrically connected with the external world.All similar as for other related process, therefore repeat no more.

The 4th embodiment

Refer to Fig. 5, it is the diagrammatic cross-section of the 4th embodiment of the semiconductor device with microprobe of the present invention.The difference of the present embodiment and the first embodiment is: in this buffer insulation layer 24, have two these buffer insulation layer perforates 242, this tertiary circuit layer 25 ' connects two these buffer insulation layer perforates 242, and this microprobe 30 is electrically connected this tertiary circuit layer 25 ', at least one this second perforate 262 is between two these buffer insulation layer perforates 242 again, in addition, two these buffer insulation layer perforates 242 are with respect to these the second perforate 272 asymmetric settings in ground, or, two these buffer insulation layer perforates 242 are to be symmetrical arranged and (to be symmetrical in microprobe 30 with respect to these the second perforate 262 ground, this situation of icon not).All similar as for other related process, therefore repeat no more.

The present invention also provides a kind of semiconductor device with microprobe, comprising: substrate 20, the first line layer 201 ', the first dielectric layer 21, the second line layer 22 ', buffer insulation layer 24, tertiary circuit layer 25 ', the second dielectric layer 27 and microprobe 30.

This substrate 20 has relative first surface 20a and second surface 20b, on the first surface 20a of this substrate 20, be formed with this first line layer 201 ', and on the first surface 20a of this substrate 20 and this first line layer 201 ', being formed with the first dielectric layer 21, this first dielectric layer 21 also has the first perforate 212 that exposes this first line layer 201 '.

This second line layer 22 ' be formed on this first dielectric layer 21 with this first perforate 212 in, upper with BCB(benzocyclobutene with this second line layer 22 ' in this first dielectric layer 21 again, Benzocyclo-buthene), polyimide (PI) or polybenzoxazoles (polybenzoxazole, PBO) material is formed with this buffer insulation layer 24, and this buffer insulation layer 24 has at least one buffer insulation layer perforate 242 that exposes this second line layer 22 '.

This tertiary circuit layer 25 ' be formed on this buffer insulation layer 24 with this buffer insulation layer perforate 242 in, and be formed with this second dielectric layer 27 on this buffer insulation layer 24 and this tertiary circuit layer 25 ', and this second dielectric layer 27 has at least one the second perforate 272 that exposes this tertiary circuit layer 25 ', and the position of this second perforate 272 is not to should buffer insulation layer perforate 242, and in the second perforate 272 of this second dielectric layer 27, form material for example for tungsten (W), rhenium (Re), beryllium (Be), palladium (Pd), titanium-tungsten (TiW), this microprobe 30 of tungsten-rhenium alloy (ReW) or beallon (BeCu), and this microprobe 30 protrudes from this second dielectric layer 27.

According to the aforesaid semiconductor device with microprobe, the position of this buffer insulation layer perforate 242 is not to position that should the first perforate 212, the position of this second perforate 272 is to should buffer insulation layer perforate 242 again, but the position of this first perforate 212 is to position that should the second perforate 272.

In the semiconductor device with microprobe of the present invention, this first line layer 201 ' of part exposes to atmosphere, for external electric connection, this substrate 20 also has the conductive through hole 203 that runs through this first surface 20a and second surface 20b and be electrically connected this first line layer 201 '.

According to front described semiconductor device, this buffer insulation layer perforate 242 has two these buffer insulation layer perforates 242, and two these buffer insulation layer perforates 242 are to connect by this tertiary circuit layer 25 ', and this microprobe 30 is electrically connected this tertiary circuit layer 25 ', and at least one this second perforate 272 is between two these buffer insulation layer perforates 242, two these buffer insulation layer perforates 242 are asymmetric with respect to these the second perforate 272 ground or are symmetrical arranged.Above-described embodiment, the material of this first metal layer 201, the second metal level 22, the 3rd metal level 25 and the 4th metal level 28 is copper or aluminium, the material of this first dielectric layer 21 and this second dielectric layer 27 is BCB(benzocyclobutene, BenzocycloBu-thene), polyimide (PI) or polyphenyl are disliked (Polybenzoxazole, PBO), the material of this base material 20 is silicon (silicon), insulation course silicon (silicon on insulator, SOI), gallium arsenide (GaAs), glass (glass), germanium (Ge), SiGe (SiGe) or silit (SiC).

In sum, the semiconductor device with microprobe of the present invention has the bow type underlying structure of syllogic, and to take material be for example BCB(benzocyclobutene, Benzocyclo-buthene), polyimide (PI) or polybenzoxazoles (polybenzoxazole, PBO) buffer insulation layer as buffering and the substrate of coated bow type so that better elastic force to be provided, therefore the problem of subject to damage and elastic fatigue in the time of can reducing microprobe operation movement, and microprobe of the present invention has again fine pitch (being less than 40 microns) and huge quantity (being greater than 10000 microprobe numbers); In addition, as the syllogic diapsida buffer structure of Fig. 5 further provides preferably elastic force; The material on this microprobe surface can be wear-resisting titanium-tungsten (TiW), tungsten-rhenium alloy (ReW) or beallon (BeCu) again, to increase the serviceable life of microprobe; In addition, the simple structure with the semiconductor device of microprobe of the present invention, and be easy to make, the shortcoming that there is no existing probe manufacturing: Calipering needs to use semiconductor core blade technolgy and stack of ceramic plates technique simultaneously, cause that integrated artistic is more complicated, yield is poor and Production Time is elongated, cause the problems such as cost raising.

Above-mentioned those embodiment are illustrative effect of the present invention only, but not for limiting the present invention, any those skilled in the art all can, under spirit of the present invention and category, modify and change above-mentioned those embodiment.In addition, the quantity of the assembly in above-mentioned those embodiment is only illustrative, also non-for limiting the present invention.Therefore the scope of the present invention should be as listed in claims.

Claims

1. a method for making with the semiconductor device of microprobe, comprising:

In one, have on the first surface of substrate of relative first surface and second surface and form the first line layer;

On the first surface of this substrate and this first line layer, form the first dielectric layer, this first dielectric layer also has the first perforate that exposes this first line layer;

Form the second line layer on this first dielectric layer with this first perforate in;

On this first dielectric layer and this second line layer, form a buffer insulation layer, this buffer insulation layer also has at least one buffer insulation layer perforate that exposes this second line layer;

Form tertiary circuit layer on this buffer insulation layer with this buffer insulation layer perforate in;

On this buffer insulation layer and this tertiary circuit layer, form the second dielectric layer, this second dielectric layer also has at least one the second perforate that exposes this tertiary circuit layer; And

In the second perforate of this second dielectric layer, form microprobe, and this microprobe protrudes from this second dielectric layer.

2. the method for making with the semiconductor device of microprobe according to claim 1, is characterized in that, this first line layer, this second line layer or this tertiary circuit layer are to form by plating mode.

3. the method for making with the semiconductor device of microprobe according to claim 1, is characterized in that, this microprobe is to form by plating mode.

4. the method for making with the semiconductor device of microprobe according to claim 1, is characterized in that, the position of this buffer insulation layer perforate is not to position that should the first perforate.

5. the method for making with the semiconductor device of microprobe according to claim 1, is characterized in that, the position of this second perforate is not to should the perforate of buffer insulation layer.

6. the method for making with the semiconductor device of microprobe according to claim 1, is characterized in that, the position of this first perforate is to position that should the second perforate.

7. the method for making with the semiconductor device of microprobe according to claim 1, is characterized in that, this first line layer of part stretches out along the semiconductor device sidepiece of this microprobe, for external electric connection.

8. the method for making with the semiconductor device of microprobe according to claim 1, is characterized in that, this substrate also has the conductive through hole that runs through this first surface and second surface and be electrically connected this first line layer.

9. the method for making with the semiconductor device of microprobe according to claim 1, is characterized in that, the material of this buffer insulation layer is BCB, polyimide or polybenzoxazoles.

10. the method for making with the semiconductor device of microprobe according to claim 1, is characterized in that, the material of this microprobe is titanium-tungsten, tungsten-rhenium alloy or beallon.

11. method for makings with the semiconductor device of microprobe according to claim 1, is characterized in that, the material of this microprobe is tungsten, rhenium, beryllium or palladium.

12. method for makings with the semiconductor device of microprobe according to claim 1, is characterized in that, this method for making is also included in and in this second perforate, is formed with the 4th line layer, and this microprobe is electrically connected the 4th line layer.

13. method for makings with the semiconductor device of microprobe according to claim 1, it is characterized in that, this buffer insulation layer has two these buffer insulation layer perforates, and two these buffer insulation layer perforates are to connect by this tertiary circuit layer, and this microprobe is electrically connected this tertiary circuit layer.

14. 1 kinds of semiconductor devices with microprobe, comprising:

Substrate, has relative first surface and second surface;

The first line layer, is formed on the first surface of this substrate;

The first dielectric layer, is formed on the first surface and this first line layer of this substrate, and has the first perforate that exposes this first line layer;

The second line layer, be formed on this first dielectric layer with this first perforate in;

Buffer insulation layer, is formed on this first dielectric layer and this second line layer, and has at least one buffer insulation layer perforate that exposes this second line layer;

Tertiary circuit layer, be formed on this buffer insulation layer with this buffer insulation layer perforate in;

The second dielectric layer, is formed on this buffer insulation layer and this tertiary circuit layer, and has at least one the second perforate that exposes this tertiary circuit layer; And

Microprobe, is located in the second perforate of this second dielectric layer, and protrudes from this second dielectric layer.

15. semiconductor devices with microprobe according to claim 14, is characterized in that, the position of this buffer insulation layer perforate is not to position that should the first perforate.

16. semiconductor devices with microprobe according to claim 14, is characterized in that, the position of this second perforate is not to should the perforate of buffer insulation layer.

17. semiconductor devices with microprobe according to claim 14, is characterized in that, the position of this first perforate is to position that should the second perforate.

18. semiconductor devices with microprobe according to claim 14, is characterized in that, this first line layer of part exposes to atmosphere, for external electric connection.

19. semiconductor devices with microprobe according to claim 14, is characterized in that, this substrate also has the conductive through hole that runs through this first surface and second surface and be electrically connected this first line layer.

20. semiconductor devices with microprobe according to claim 14, is characterized in that, the material of this buffer insulation layer is BCB, polyimide or polybenzoxazoles.

21. semiconductor devices with microprobe according to claim 14, is characterized in that, the material of this microprobe is titanium-tungsten, tungsten-rhenium alloy or beallon.

22. semiconductor devices with microprobe according to claim 14, is characterized in that, the material of this microprobe is tungsten, rhenium, beryllium or palladium.

23. semiconductor devices with microprobe according to claim 14, it is characterized in that, this buffer insulation layer has two these buffer insulation layer perforates, and two these buffer insulation layer perforates are to connect by this tertiary circuit layer, and this microprobe is electrically connected this tertiary circuit layer.

24. semiconductor devices with microprobe according to claim 14, is characterized in that, this semiconductor device is also included in and in this second perforate, is formed with the 4th line layer, and this microprobe is electrically connected the 4th line layer.