CN103681390A - TSV (Through Silicon Via) technology based preparation method for wafer level silicon substrate - Google Patents
TSV (Through Silicon Via) technology based preparation method for wafer level silicon substrate Download PDFInfo
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- CN103681390A CN103681390A CN201310713210.0A CN201310713210A CN103681390A CN 103681390 A CN103681390 A CN 103681390A CN 201310713210 A CN201310713210 A CN 201310713210A CN 103681390 A CN103681390 A CN 103681390A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
Abstract
The invention discloses a TSV (Through Silicon Via) technology based preparation method for a wafer level silicon substrate. The TSV technology based preparation method comprises the following steps of preparing a first blind hole in a substrate wafer by using a DRIE (Deep Reactive Ion Etching) technology; depositing an insulating layer, an adhesion/diffusion barrier layer and a seed layer metal on the inner wall of the first blind hole; electrically plating copper in the first blind hole and flattening the electrically plated copper by using a CMP (Chemical Mechanical Polishing) technology; preparing a bonding pad and a passivation layer on the backside of the substrate; preparing a second blind hole in the front side of the substrate wafer by using the DRIE technology; depositing an insulating layer on the inner wall of the second blind hole and removing an insulating layer at the bottom; depositing an adhesion/diffusion barrier layer and a seed layer in the second blind hole; electrically plating copper in the second blind hole and flattening; preparing a wiring metal, a passivation layer and a bonding pad on the front side of the substrate wafer. The TSV technology based preparation method for the wafer level silicon substrate can realize machining of the silicon substrate with the high aspect ratio of 20: 1-30: 1, reduces difficulties of deposition of the insulating layer, the adhesion/diffusion barrier layer and the seed layer metal on the sidewall of the through hole and electric plating technology of the through hole, and can be used for machining ultra-thick TSV packaging substrates for high-density and small-size system level packaging.
Description
Technical field
The wafer scale silicon substrate preparation method who the present invention relates to a kind of high-aspect-ratio TSV, belongs to module and system in package technical field.
Background technology
Electronic product miniaturization day by day, lighting, multi-functional, low-power consumption and low-cost development trend, two dimension, 3 D semiconductor encapsulation technology cannot meet the demands.
TSV(Through Silicon Via, silicon through hole) technology can be carried out chip and chip, chip and substrate perpendicular interconnection, has effectively shortened information transmission path, and with package area can realize greater functionality, more high power, more cross exit.TSV technology is the effective way of semiconductor system level encapsulation.At present, one of main application of silicon through hole technology (TSV) is preparation interposer substrate, for chip-scale encapsulation and system in package.
Tradition TSV interposer substrate manufacture craft is: 1) at substrate, prepare blind hole; 2) substrate one side PECVD deposit through-hole side wall passivation layer; 3) at stick/diffusion impervious layer of substrate one side magnetron sputtering deposit through-hole side wall, Seed Layer metal; 4) electroplating technology completes via metal filling; 5) via metal planarization; 6) attenuate exposes substrate back via metal; 7) make metal line, pad and protective layer thereof.Tradition TSV interposer substrate preparation method possesses following defect or deficiency:
(1) PECVD deposit deep hole sidewall passivation layer lack of homogeneity, deep hole bottom thickness of insulating layer approximately only has 1/5 of top, and bottom insulation layer coverage rate is poor, easily produces discontinuous defect and has a strong impact on insulation effect and reliability.This has also limited passivation layer depositing technics depth-to-width ratio deposit ability.
(2) magnetron sputtering deposit deep hole sidewall adhesion/diffusion impervious layer, Seed Layer lack of homogeneity, deep hole bottom thickness approximately only has 1/5 of top, deep hole bottom coverage rate is poor, easily produces discontinuous defect and occurs while causing electroplating having a strong impact on through hole reliability in cavity.At present, the deep hole depth-to-width ratio deposit ability of state-of-the-art magnetron sputtering apparatus is less than 15:1, this restricted T SV depth-to-width ratio deposit ability.
(3) depth-to-width ratio is 20:1～30:1 deep hole, realizes without hole plating fill process difficulty larger.
(4) be limited to above-mentioned traditional TSV interposer substrate manufacture craft, interposer substrate thickness is less than 200 μ m conventionally, only can be used as interposer substrate, cannot directly assemble with complete machine plate.
Summary of the invention
The object of the invention is to solve traditional TSV substrate processing technology deep hole sidewall passivation layer, stick/diffusion impervious layer, seed layer deposition thickness offset, via bottoms coverage rate is not enough technical problem, a kind of high-aspect-ratio TSV wafer scale silicon substrate preparation method is provided, reduce Deep hole electroplating fill process difficulty, have 10:1～15:1 to bring up to 20:1～30:1 deep hole depth-to-width ratio ability.
The described wafer scale silicon substrate preparation method based on TSV technique, comprises following processing step:
Step 1: adopt deep reaction ion etching technique to prepare the first blind hole at the substrate disk back side;
Step 2: stick at the first blind hole inwall and substrate disk back side deposit the first insulating barrier, first, diffusion impervious layer and Seed Layer metal;
Step 3: electro-coppering in the first blind hole, and adopt CMP technique to carry out electro-coppering planarization;
Step 4: prepare the first pad and the first passivation layer at the substrate disk back side;
Step 5: adopt deep reaction ion etching technique in the positive preparation of substrate disk the second blind hole;
Step 6: at second blind hole inwall deposit the second insulating barrier, and remove the second insulating barrier of the second blind hole bottom, expose that first in the first blind hole sticked, diffusion impervious layer and Seed Layer metal;
Step 7: stick in the second blind hole inwall deposit second, diffusion impervious layer and Seed Layer metal;
Step 8: electro-coppering in the second blind hole, and adopt CMP technique to carry out electro-coppering planarization;
Step 9: wiring metal, the second passivation layer and the second pad are prepared in substrate disk front.
Described the first blind hole depth-to-width ratio is 10:1～15:1, and the second blind hole depth-to-width ratio is 10:1～15:1.
Beneficial effect of the present invention: the present invention has improved TSV deep hole sidewall passivation layer, sticks/diffusion impervious layer, seed layer deposition thickness evenness, via bottoms coverage rate, reduced TSV the electroplates in hole fill process difficulty, traditional TSV technique depth-to-width ratio thin film deposition ability 10:1～12:1 has been brought up to 20:1～30:1.Can be used for the thicker base plate for packaging of preparation.
Accompanying drawing explanation
Fig. 1～Fig. 9 is a kind of wafer scale silicon substrate preparation method's based on TSV technique of the present invention process flow chart and Typical Process Case flow chart; Wherein,
Etching the first blind hole schematic diagram on Fig. 1 silicon substrate disk.
Fig. 2 the first blind hole inwall deposition insulating layer, stick/diffusion impervious layer and Seed Layer schematic diagram.
Electro-coppering and cmp planarization schematic diagram in Fig. 3 the first blind hole.
Fig. 4 makes back side pad and passivation layer schematic diagram.
Etching the second blind hole schematic diagram on Fig. 5 substrate.
Fig. 6 the second blind hole inwall deposition insulating layer and removal bottom insulation layer, expose the schematic diagram of filling metal.
Stick/diffusion impervious layer of deposit and Seed Layer schematic diagram in Fig. 7 the second blind hole.
Electro-coppering and cmp planarization schematic diagram in Fig. 8 the second blind hole.
The wiring of Fig. 9 substrate and passivation layer thereof are prepared schematic diagram.
Description of reference numerals in figure: the electro-coppering 9 in the electro-coppering 4 in substrate disk 1, through-hole side wall the first insulating barrier 2, through-hole side wall the first stick/diffusion impervious layer and Seed Layer 3, the first blind hole, the back side the first pad 5, the back side the first passivation layer 6, through-hole side wall the second insulating barrier 7, through-hole side wall the second stick/diffusion impervious layer and Seed Layer 8, the second blind hole, substrate front side wiring metal 10, substrate front side the second passivation layer 11, substrate front side the second pad 12.
Embodiment
Wafer scale silicon substrate preparation method based on TSV technique of the present invention comprises the following steps:
Step 1: adopt deep reaction ion etching (DRIE) technique to prepare the first blind hole at the substrate disk back side.
Step 2: in the first blind hole inwall and substrate disk back side deposition insulating layer, stick/diffusion impervious layer and Seed Layer.
Step 3: electro-coppering in the first blind hole, and adopt CMP technique to carry out electro-coppering planarization.
Step 4: prepare pad and passivation layer at the substrate disk back side.
Step 5: adopt DRIE technique in the positive preparation of substrate disk the second blind hole.
Step 6: the second blind hole inwall deposition insulating layer, and remove the second blind hole bottom insulation layer, expose in the first blind hole stick/diffusion impervious layer and Seed Layer metal.
Step 7: stick/diffusion impervious layer of deposit and Seed Layer metal in the second blind hole.
Step 8: electro-coppering in the second blind hole, and adopt CMP technique to carry out electro-coppering planarization.
Step 9: wiring metal, passivation layer and pad are prepared in substrate disk front.
Fig. 1～Fig. 9 is a kind of wafer scale silicon substrate preparation method's based on TSV technique of the present invention Typical Process Case flow chart.Described preparation method comprises following processing step:
Step 1: 1. choose 8 inches of silicon chips and make baseplate material, substrate thickness 500 μ m; 2. at substrate disk 1 back side spin coating photoresist, by photoetching process, form figure opening; 3. adopt deep reaction ion etching (DRIE, Deep Reactive Ion Etch) the technique etching first blind hole I on substrate disk 1 based on " BOSCH " technology, its diameter 20～35 μ m, the degree of depth 300 μ m; 4. stripping photoresist.As Fig. 1.
Step 2: 1. adopt PECVD(plasma-reinforced chemical vapor deposition) technique is at substrate disk 1 back side and the first blind hole I inwall deposit 1～2 μ m thickness SiO
2insulating layer material (the first insulating barrier 2); 2. adopt magnetron sputtering technique substrate disk 1 back side and the first blind hole I inwall respectively deposit 1000～2000 (dust) Ti and 5000～8000 Cu as stick/diffusion impervious layer and Seed Layer metal 3.Referring to Fig. 2.
Step 3: 1., at substrate disk 1 back side spin coating photoresist, form figure opening by photoetching process, expose the first blind hole I; 2. electro-coppering 4 in the first blind hole I; 3. stripping group disc 1 photomask surface glue; 4. adopt wet-etching technology to remove aforesaid substrate disk 1 surperficial unnecessary Ti and Cu; 5. adopt CMP technique to carry out planarization to electro-coppering 4.Referring to Fig. 3.
Step 4: 1. adopt magnetron sputtering technique at substrate disk 1 back side deposit 6000～8000 aluminium of completing steps three; 2. at deposit aluminium surface spin coating photoresist, by photoetching process, form figure opening, adopt wet-etching technology to remove substrate disk 1 surperficial unnecessary aluminium, form the first pad 5; 3. remove photoresist; 4. adopt pecvd process at substrate disk 1 back side deposit 6000～8000 SiO successively
2with 2000～4000 Si
3n
4as the first pad 5 passivation layer 6 above; 5. at Si
3n
4upper spin coating photoresist, forms figure opening by photoetching process, and by dry etch process etching SiO
2and Si
3n
4expose the first pad 5; 6. remove photoresist.Referring to Fig. 4.
Step 5: 1., at the positive spin coating photoresist of substrate disk 1, form figure opening by photoetching process, and make the second blind hole II by deep reaction ion etching technique, its diameter 15～25 μ m, the degree of depth 200 μ m; 2. stripping photoresist.Referring to Fig. 5.
Step 6: 1. adopt PECVD(plasma-reinforced chemical vapor deposition) technique is at substrate disk 1 front and the second blind hole II inwall deposit 1～2 μ m thickness SiO
2insulating layer material (the second insulating barrier 7); 2. adopt laser ablation technology to remove the second blind hole II bottom insulation layer 7 materials, expose stick/diffusion impervious layer and the Seed Layer metal 3 of lower floor.Referring to Fig. 6.
Step 7: adopt magnetron sputtering technique at the substrate disk 1 of completing steps six positive and the second blind hole II inwall successively deposit 1000～2000 Ti and 5000～8000 Cu as Seed Layer 8.Referring to Fig. 7.
Step 8: 1., by the positive spin coating photoresist of the substrate disk 1 of completing steps seven, form figure opening by photoetching process, expose the second blind hole II; 2. electro-coppering 9 in the second blind hole II; 3. stripping group disc 1 photomask surface glue; 4. adopt wet-etching technology to remove aforesaid substrate disk 1 unnecessary Ti and the Cu in surface; 5. adopt CMP technique to carry out planarization to electro-coppering 9.Referring to Fig. 8.
Step 9: 1. adopt magnetron sputtering technique at substrate disk 1 surface deposition 6000～8000 aluminium of completing steps three, at deposit aluminium surface spin coating photoresist, by photoetching process, form figure opening, adopt wet-etching technology to remove substrate disk 1 surperficial unnecessary aluminium, form wiring metal 10, finally remove photoresist; 2. adopt pecvd process at positive deposit 6000～8000 SiO of substrate disk 1 that form wiring metal 10
2with 2000～3000 Si
3n
4as passivation material 11; At the surperficial spin coating photoresist of passivation material 11, by photoetching process, form litho pattern opening, then adopt dry etch process to remove unnecessary SiO in photoresist opening
2and Si
3n
4, expose wiring metal 10, finally remove photoresist; 3. on passivation layer 10 surfaces that form opening successively magnetron sputtering 800～2000 Ti, 2000～5000 Ni, 100～600 Au; At sputter Au surface spin coating photoresist, by photoetching process, form litho pattern opening, then adopt wet-etching technology to remove substrate disk 1 unnecessary Ti, Ni, the Au in surface, form the second pad 12; 4. finally remove photoresist.Referring to Fig. 9.
The present invention is by TSV(silicon through hole) through hole making, through-hole side wall insulation, stick/diffusion impervious layer of deposit, Seed Layer and through hole copper electroplates to fill and carries out in two steps, the method has improved through-hole side wall insulating barrier, stick/diffusion impervious layer and Seed Layer metal uniformity, by deep hole side wall insulating layer, stick/diffusion impervious layer, seed layer deposition ability improved 2 times; Reduce deep hole copper electroplating technology difficulty, can guarantee to obtain in deep hole and electroplate without hole copper, improved reliability.The method can, by TSV technique depth-to-width ratio working ability by 10:1～15:1, be brought up to 20:1～30:1.
Claims (3)
1. the wafer scale silicon substrate preparation method based on TSV technique, is characterized in that, comprises following processing step:
Step 1: adopt deep reaction ion etching technique to prepare the first blind hole at substrate disk (1) back side;
Step 2: stick at the first blind hole inwall and substrate disk (1) back side deposit the first insulating barrier (2), first, diffusion impervious layer and Seed Layer metal (3);
Step 3: electro-coppering in the first blind hole, and adopt CMP technique to carry out electro-coppering planarization;
Step 4: prepare the first pad (5) and the first passivation layer (6) at substrate disk (1) back side;
Step 5: adopt deep reaction ion etching technique in the positive preparation of substrate disk (1) the second blind hole;
Step 6: at second blind hole inwall deposit the second insulating barrier (7), and remove the second insulating barrier of the second blind hole bottom, expose that first in the first blind hole sticked, diffusion impervious layer and Seed Layer metal (3);
Step 7: stick in the second blind hole inwall deposit second, diffusion impervious layer and Seed Layer metal (8);
Step 8: electro-coppering in the second blind hole, and adopt CMP technique to carry out electro-coppering planarization;
Step 9: wiring metal (10), the second passivation layer (11) and the second pad (12) are prepared in substrate disk (1) front.
2. a kind of wafer scale silicon substrate preparation method based on TSV technique as claimed in claim 1, is characterized in that, described the first blind hole depth-to-width ratio is 10:1～15:1.
3. as claim 1, a kind of wafer scale silicon substrate preparation method based on TSV technique described in 2, is characterized in that, described the second blind hole depth-to-width ratio is 10:1～15:1.
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| WO2017177388A1 (en) * | 2016-04-13 | 2017-10-19 | 深圳线易科技有限责任公司 | Interposer having embedded metal wires with high depth-to-width ratio and method for manufacturing same |
| CN108448217A (en) * | 2018-03-01 | 2018-08-24 | 西南科技大学 | The radio frequency microstrip structure of Ti/Ni/Ag material systems |
| CN109622968A (en) * | 2019-02-19 | 2019-04-16 | 南通理工学院 | A kind of TSV encapsulation 3D printer and Method of printing |
| CN110791746A (en) * | 2019-11-08 | 2020-02-14 | 北京工业大学 | Method and device for rapidly filling vertical silicon through hole with liquid alloy |
| CN111968953A (en) * | 2020-08-26 | 2020-11-20 | 中国电子科技集团公司第十三研究所 | Through silicon via structure and preparation method thereof |
| CN113161289A (en) * | 2021-04-22 | 2021-07-23 | 浙江集迈科微电子有限公司 | Electroplating process of TSV (through silicon via) metal column with high depth-to-width ratio |
| CN113174620A (en) * | 2021-04-22 | 2021-07-27 | 浙江集迈科微电子有限公司 | Electroplating method of plating solution flow velocity reinforced TSV metal column |
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| CN114959606A (en) * | 2022-05-13 | 2022-08-30 | 赛莱克斯微系统科技（北京）有限公司 | Preparation method of silicon through hole seed layer and preparation method of chip |
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| CN108448217A (en) * | 2018-03-01 | 2018-08-24 | 西南科技大学 | The radio frequency microstrip structure of Ti/Ni/Ag material systems |
| CN109622968A (en) * | 2019-02-19 | 2019-04-16 | 南通理工学院 | A kind of TSV encapsulation 3D printer and Method of printing |
| CN110791746B (en) * | 2019-11-08 | 2021-10-15 | 北京工业大学 | Method and device for rapidly filling vertical silicon through hole with liquid alloy |
| CN110791746A (en) * | 2019-11-08 | 2020-02-14 | 北京工业大学 | Method and device for rapidly filling vertical silicon through hole with liquid alloy |
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| CN113174620B (en) * | 2021-04-22 | 2022-05-03 | 浙江集迈科微电子有限公司 | Electroplating method of plating solution flow velocity reinforced TSV metal column |
| CN113174620A (en) * | 2021-04-22 | 2021-07-27 | 浙江集迈科微电子有限公司 | Electroplating method of plating solution flow velocity reinforced TSV metal column |
| CN113161289A (en) * | 2021-04-22 | 2021-07-23 | 浙江集迈科微电子有限公司 | Electroplating process of TSV (through silicon via) metal column with high depth-to-width ratio |
| CN113410175A (en) * | 2021-06-15 | 2021-09-17 | 西安微电子技术研究所 | Preparation method of TSV (through silicon Via) conductive through hole structure |
| CN113410175B (en) * | 2021-06-15 | 2023-06-02 | 西安微电子技术研究所 | TSV conductive through hole structure preparation method |
| CN113506767A (en) * | 2021-06-16 | 2021-10-15 | 天津津航计算技术研究所 | TSV adapter plate manufacturing method |
| CN113782489A (en) * | 2021-08-27 | 2021-12-10 | 上海华虹宏力半导体制造有限公司 | Through silicon via and forming method thereof |
| CN114959606A (en) * | 2022-05-13 | 2022-08-30 | 赛莱克斯微系统科技（北京）有限公司 | Preparation method of silicon through hole seed layer and preparation method of chip |
| WO2024021356A1 (en) * | 2022-07-29 | 2024-02-01 | 武汉新芯集成电路制造有限公司 | Tsv electrical connection structure having high aspect ratio and manufacturing method therefor |
| CN117253872A (en) * | 2023-11-15 | 2023-12-19 | 深圳市新凯来技术有限公司 | Interconnect structure and method for manufacturing interconnect structure |
| CN117253872B (en) * | 2023-11-15 | 2024-02-27 | 深圳市新凯来技术有限公司 | Interconnect structure and method for manufacturing interconnect structure |
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