CN103681450A - Method for forming semiconductor device - Google Patents
Method for forming semiconductor device Download PDFInfo
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- CN103681450A CN103681450A CN201210348133.9A CN201210348133A CN103681450A CN 103681450 A CN103681450 A CN 103681450A CN 201210348133 A CN201210348133 A CN 201210348133A CN 103681450 A CN103681450 A CN 103681450A
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- semiconductor device
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- oxide layer
- formation method
- pad oxide
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02299—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment
- H01L21/02304—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment formation of intermediate layers, e.g. buffer layers, layers to improve adhesion, lattice match or diffusion barriers
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Abstract
The invention provides a method for forming a semiconductor device. The method comprises the following steps: providing a substrate; etching the substrate to form a plurality of isolation trenches on the substrate; cleaning the substrate on which the isolation trenches are formed; forming a lining oxide layer covering the substrate and the bottoms and side walls of the isolation trenches in the substrate; performing oxidation treatment on the surface of the lining oxide layer, and performing annealing process. The method for forming a semiconductor device, provided in the invention, performs oxidation treatment on the surface of the lining oxide layer before the substrate provided with the lining oxide layer is annealed, so that unstable silicon-oxygen bonds on the surface of the lining oxide layer form silicon oxide with stable property, which avoids the loss of silicon atoms on the surface of the lining oxide layer and thus prevents the formation of drain current on the surface of the lining oxide layer, as a result, the stability and yield of the semiconductor device formed are improved.
Description
Technical field
The present invention relates to field of semiconductor manufacture, relate in particular to a kind of formation method of semiconductor device.
Background technology
Develop rapidly along with semiconductor fabrication, semiconductor device is in order to reach arithmetic speed faster, larger information storage and more function, semiconductor chip is to high integration future development more, be the characteristic size (CD of semiconductor device, Critical Dimension) less, and the integrated level of semiconductor chip is higher.
Along with uprising of semiconductor chip integrated level, in unit are, need the semiconductor device quantity and the type that form also more and more, how the position of each semiconductor device of reasonable arrangement and utilize the common ground in each semiconductor device forming process to save the focus that semiconductor technology step becomes present research.
Existing technique is when forming semiconductor device, the active area of semiconductor device mainly defines by form isolation structure on substrate, referring to figs. 1 to Fig. 4, on substrate, forming isolated groove first mainly comprises the steps:, with reference to figure 1, substrate 101 is provided, and forms the mask layer 103 that comprises channel patterns on substrate 101; Then, with reference to figure 2, the described mask layer 103 of take is mask, along substrate 101 described in channel patterns etching, forms isolated groove 105; With reference to figure 3, remove described mask layer 103, and described substrate 101 is cleaned, to remove the impurity being attached on substrate 101 and to form residual polymer in isolated groove 105 processes; Then, with reference to figure 4, on the surface of substrate 101 and isolated groove 105, form pad oxide layer 107; Finally, to being formed with the substrate 101 of pad oxide layer 107 in Fig. 4, carry out annealing process, damage substrate 101 being caused to repair etching technics.Wherein, the substrate 101 between isolated groove 105, as the active area of semiconductor device, defines the position of semiconductor device in substrate 101, and each active area can be by isolating at the interior fill oxide of isolated groove 105 mutually.
Yet, after annealing process, during being detected, surfaces of active regions finds: the surfaces of active regions forming by existing technique exists damage, causes formed semiconductor device easily produce leakage current and puncture, and the rate of finished products of the semiconductor device that forms is lower.
More in multiple semiconductor devices, the formation method of active area please refer to the Chinese patent application that publication number is CN102087960A.
Summary of the invention
The problem that the present invention solves is to provide a kind of formation method of semiconductor device, avoids surfaces of active regions in semiconductor device to form silicon damage, improves stability and the rate of finished products of the semiconductor device that forms.
For addressing the above problem, the invention provides a kind of formation method of semiconductor device, comprising: substrate is provided; Substrate described in etching forms some isolated grooves on substrate; To being formed with the substrate of isolated groove, clean; The pad oxide layer of isolated groove bottom and sidewall in formation covering substrate and substrate; Oxidation processes is carried out in described pad oxide layer surface; Carry out annealing process.
The method of optionally, oxidation processes being carried out in described pad oxide layer surface is wet treatment or dry process.
Optionally, the solution of described wet treatment is sulfuric acid solution, and the time is 1min ~ 10min; Or the solution of described wet treatment is hydrogen peroxide, the time is 5min ~ 30min.
Optionally, the gas that described dry process adopts is oxygen, and the flow of oxygen is 10000sccm ~ 20000sccm, and the temperature of described dry process is 200 ℃ ~ 300 ℃, and the time is 10min ~ 30min.
Compared with prior art, technical solution of the present invention has the following advantages:
To being formed with before the substrate of pad oxide layer carries out annealing process, oxidation processes is carried out in pad oxide layer surface, making to be positioned at the unsettled silicon oxygen bond in pad oxide layer surface is oxidized, form silica, avoid unsettled silicon oxygen bond and the impurity that is attached to pad oxide layer surface to react, form sulfurous acid, and then avoid the silicon atom on pad oxide layer surface to run off, prevent from producing leakage current on pad oxide layer surface, improved stability and the rate of finished products of the semiconductor device that forms.
Accompanying drawing explanation
Fig. 1 ~ Fig. 4 is the cross-sectional view of semiconductor device that existing technique forms;
Fig. 5 is the schematic flow sheet of an execution mode of formation method of semiconductor device of the present invention;
In embodiment of formation method that Fig. 6 ~ Fig. 8 is semiconductor device of the present invention the cross-sectional view of formation semiconductor device.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.
Set forth in the following description a lot of details so that fully understand the present invention, but the present invention can also adopt other to be different from alternate manner described here, implement, so the present invention has not been subject to the restriction of following public specific embodiment.
Just as described in the background section, existing technique forms surfaces of active regions in semiconductor device and has damage, causes formed semiconductor device easily produce leakage current and puncture, and the rate of finished products of the semiconductor device that forms is low.
Research through inventor is found, in semiconductor device, the damage of surfaces of active regions is due to when substrate being carried out to etching formation isolated groove, silicon atom in substrate easily loses an electronics, form the silicon ion of positive monovalence, the silicon ion of this positive monovalence easily in pad oxide layer silica be combined, form unsettled silicon oxygen bond, when carrying out thermal anneal process, unsettled silicon oxygen bond easily reacts with the hydroxyl and the water that are attached to pad oxide layer surface under hot environment, form sulfurous acid, cause the silicon atom of surfaces of active regions to run off, in surfaces of active regions, form damage.In the use procedure of semiconductor device, surfaces of active regions easily produces leakage current, and semiconductor device easily punctures, and the stability of the semiconductor device that forms is not high, rate of finished products is low.
For above-mentioned defect, in technical solution of the present invention, first on substrate, form isolated groove, then to being formed with the substrate of isolated groove, clean, and on substrate and on the bottom of isolated groove and sidewall, form pad oxide layer, then pad oxide layer is carried out to oxidation processes, finally carry out annealing process, thereby before annealing process, unsettled silicon oxygen bond is converted into stable silica, avoid unsettled silicon oxygen bond in annealing process to react with the hydroxyl and the water that residue in pad oxide layer surface, and then can avoid silicon atom on active area to run off, rate of finished products and the stability of the semiconductor device that forms have been improved.
Below in conjunction with accompanying drawing, be elaborated.
With reference to figure 5, the schematic flow sheet for the execution mode of formation method of semiconductor device of the present invention, comprising:
Step S1, provides substrate, is formed with some isolated grooves on described substrate;
Step S2, cleans being formed with the substrate of isolated groove;
Step S3, the pad oxide layer of isolated groove bottom and sidewall in formation covering substrate surface and substrate;
Step S4, carries out oxidation processes to described pad oxide layer surface;
Step S5, carries out annealing process;
Step S6 forms isolation structure in described isolated groove.
In embodiment of formation method that Fig. 6 ~ Fig. 8 is semiconductor device of the present invention the cross-sectional view of formation semiconductor device.In conjunction with Fig. 6 ~ Fig. 8, the formation method of semiconductor device of the present invention is described further.
With reference to figure 6, first, provide substrate 201, on described substrate 201, be formed with some isolated grooves 205.
Described substrate 201 can be silicon substrate, germanium silicon substrate or silicon-on-insulator (SOI).In the present embodiment, described substrate 201 is silicon substrate.
On substrate 201, forming some isolated grooves 205 comprises the steps:
Graphical described mask layer forms groove figure on described mask layer;
Take described mask layer as mask, along substrate 201 described in groove figure etching, form some isolated grooves 205 on substrate 201, the substrate 201 between adjacent isolated groove 205 is as the active area of semiconductor device;
Remove described mask layer.
The material of described mask layer can be organic polymer material, but the invention is not restricted to this, and it can utilize known other mask material of those skilled in the art to substitute.In the present embodiment, the material of described mask layer is photoresist, by described mask layer is exposed, developed, forms groove figure.
Take described mask layer as mask, is dry etching along the method for substrate 201 described in groove figure etching.Concrete, the etching gas of described dry etching is CF
4, CHF
3, HBr and SF
6in one or more, temperature is 50 ℃ ~ 100 ℃, the time is 1min ~ 10min, pressure is 10mTorr ~ 30mTorr, supply frequency is 800W ~ 1200W.
In the present embodiment, the method for removing described mask layer is cineration technics.In other embodiments, the method for removing mask layer can be selected according to the material of the mask layer that will remove.
Then, to being formed with the substrate 201 of isolated groove 205 in Fig. 6, clean.
In the present embodiment, the solution that substrate 201 is cleaned is sulfuric acid (H
2sO
4) solution, hydrogen peroxide (H
2o), ammoniacal liquor (NH
3h
2o) one or several and in hydrofluoric acid (HF) solution, by described substrate 201 is cleaned, can remove and form residual polymer beads in isolated groove 205 processes; Meanwhile, substrate 201 is cleaned and can also remove the impurity being attached on substrate 201, be beneficial to the formation of follow-up pad oxide layer.
It should be noted that, existing technique, after substrate 201 being carried out to etching formation isolated groove 205, is and then cleaned formed isolated groove 205, removes the residual polymer of etching technics; And also there is certain time interval in the pad oxide layer of this cleaning and follow-up formation covering substrate 201 and isolated groove 205 bottoms and sidewall, in this time interval, the bottom of substrate 201 and isolated groove 205 and sidewall easily react by contaminating impurity or with airborne gas, affect the formation of follow-up pad oxide layer.
Therefore, after substrate 201 being carried out to etching formation isolated groove 205, first, by sulfuric acid solution, one or several in hydrogen peroxide, ammoniacal liquor or hydrofluoric acid solution once clean substrate 201, remove and form residual polymer in isolated groove 205 processes; Before forming pad oxide layer, pass through sulfuric acid solution, one or several in hydrogen peroxide or hydrofluoric acid solution clean again to substrate 201, removal is attached to the impurity on substrate 201 surfaces and isolated groove 205 bottoms and sidewall, ensure while forming pad oxide layer, cleaning of substrate 201 surfaces and isolated groove 205 bottoms and sidewall, and then ensure the form of the pad oxide layer that forms in subsequent technique.
With reference to figure 7, then, the pad oxide layer 207 of isolated groove 205 bottoms and sidewall in formation covering substrate 201 surfaces and substrate 201.
The material of described pad oxide layer 207 is silica, and the method that forms described pad oxide layer 207 is thermal oxidation technology or chemical vapor deposition method.
In the present embodiment, form the method thermal oxidation technology of described pad oxide layer 207, as adopted oxidation furnace to carry out, in oxidation furnace, reacting gas is oxygen, and the temperature of gas is 1000 ℃ ~ 1200 ℃, and flow is 10slm ~ 30slm, and the reaction time is 1min ~ 5min.By forming pad oxide layer 207 on substrate 201 surfaces, make the surfacing of substrate 201, avoid electric charge partly accumulate and substrate 201 is caused to damage at substrate 201 rats, and then improve the stability of the semiconductor device that forms.
Then, oxidation processes is carried out in described pad oxide layer 207 surfaces.
In the present embodiment, described oxidation processes is dry process, and the gas of described dry process is oxygen, and the flow of described oxygen is 10000sccm ~ 20000sccm, and described dry process temperature is 200 ℃ ~ 300 ℃, and the time is 10min ~ 30min.
In other embodiments, described oxidation processes can also be wet treatment; The solution of described wet treatment is sulfuric acid solution or hydrogen peroxide; When the solution of wet treatment is sulfuric acid solution, the time of wet treatment is 1min ~ 10min; When the solution of wet treatment is hydrogen peroxide, the time of wet treatment is 5min ~ 30min.
By oxidation processes is carried out in pad oxide layer 207 surfaces, can make the surperficial unsettled silicon oxygen bond of pad oxide layer 207 be transformed into the silicon dioxide of stable in properties.
Follow, the substrate 201 that effects on surface is formed with pad oxide layer 207 carries out annealing process again, forms in Fig. 6 in isolated groove 205 processes the damage that etching technics causes substrate 201 to repair.
In the present embodiment, described annealing process is high-temperature thermal annealing (High Temperature Anneal, referred to as HTA), and the temperature of described high-temperature thermal annealing is 800 ℃ ~ 1200 ℃, and the time of high-temperature thermal annealing is 60min ~ 180min.
In carrying out annealing process procedure, because pad oxide layer 207 surfaces do not exist unsettled silicon oxygen bond, therefore, even if pad oxide layer 207 surface attachment have hydroxyl and water, also can not cause the silicon atom of surfaces of active regions to run off, and then can avoid forming damage in surfaces of active regions.
With reference to figure 8, last, at the interior formation isolation structure 209 of isolated groove described in Fig. 7 205.
In the present embodiment, the material of described isolation structure 209 is silica, and the method that forms isolation structure 209 is thermal oxidation technology or chemical vapor deposition method, and it specifically forms technique as those skilled in the art's known technology, at this, does not repeat.
In above-described embodiment, the formation method of semiconductor device is to being formed with before the substrate of pad oxide layer anneals, oxidation processes is carried out in pad oxide layer surface, making to be positioned at the unsettled silicon oxygen bond in pad oxide layer surface is oxidized, form the silica of stable chemical nature, avoid the unsettled silicon oxygen bond in pad oxide layer surface to react with hydroxyl and water and form liquid sulfurous acid, and then can avoid the silicon atom of substrate surface to run off, finally improved stability and the rate of finished products of the semiconductor device that forms.
Although the present invention discloses as above with preferred embodiment, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, so protection scope of the present invention should be as the criterion with claim limited range.
Claims (14)
1. a formation method for semiconductor device, is characterized in that, comprising:
Substrate is provided;
Substrate described in etching forms some isolated grooves on substrate;
To being formed with the substrate of isolated groove, clean;
The pad oxide layer of isolated groove bottom and sidewall in formation covering substrate and substrate;
Oxidation processes is carried out in described pad oxide layer surface;
Carry out annealing process.
2. the formation method of semiconductor device as claimed in claim 1, is characterized in that, the method for described pad oxide layer surface being carried out to oxidation processes is wet treatment or dry process.
3. the formation method of semiconductor device as claimed in claim 2, is characterized in that, the solution of described wet treatment is sulfuric acid solution, and the time is 1min ~ 10min.
4. the formation method of semiconductor device as claimed in claim 2, is characterized in that, the solution of described wet treatment is hydrogen peroxide, and the time is 5min ~ 30min.
5. the formation method of semiconductor device as claimed in claim 2, it is characterized in that, the gas that described dry process adopts is oxygen, and the flow of oxygen is 10000sccm ~ 20000sccm, the temperature of described dry process is 200 ℃ ~ 300 ℃, and the time is 10min ~ 30min.
6. the formation method of semiconductor device as claimed in claim 1, is characterized in that, to being formed with solution that the substrate of isolated groove cleans, is one or several in hydrofluoric acid solution, hydrogen peroxide, ammoniacal liquor and sulfuric acid solution.
7. the formation method of semiconductor device as claimed in claim 1, is characterized in that, the material of described pad oxide layer is silica.
8. the formation method of semiconductor device as claimed in claim 7, is characterized in that, the method that forms described pad oxide layer is thermal oxidation technology or chemical vapor deposition method.
9. the formation method of semiconductor device as claimed in claim 1, is characterized in that, described annealing process is high-temperature thermal annealing.
10. the formation method of semiconductor device as claimed in claim 9, is characterized in that, the temperature of described high-temperature thermal annealing is 800 ℃ ~ 1200 ℃, and the time of high-temperature thermal annealing is 60min ~ 180min.
The formation method of 11. semiconductor device as claimed in claim 1, is characterized in that, the method for substrate is dry etching described in etching.
The formation method of 12. semiconductor device as claimed in claim 11, is characterized in that, the etching gas of described dry etching is CF
4, CHF
3, HBr and SF
6in one or more, temperature is 50 ℃ ~ 100 ℃, the time is 1min ~ 10min, pressure is 10mTorr ~ 30mTorr, supply frequency is 800W ~ 1200W.
The formation method of 13. semiconductor device as claimed in claim 1, is characterized in that, after carrying out annealing process, also comprises: in described isolated groove, form isolation structure.
The formation method of 14. semiconductor device as claimed in claim 13, is characterized in that, the material of described isolation structure is silica.
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|---|---|---|---|
| CN201210348133.9A CN103681450B (en) | 2012-09-18 | 2012-09-18 | The forming method of semiconductor device |
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|---|---|---|---|
| CN201210348133.9A CN103681450B (en) | 2012-09-18 | 2012-09-18 | The forming method of semiconductor device |
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| CN103681450B CN103681450B (en) | 2016-10-05 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111106057A (en) * | 2019-11-18 | 2020-05-05 | 华虹半导体(无锡)有限公司 | Method for manufacturing STI (shallow trench isolation) structure of flash memory device and flash memory device |
Citations (3)
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|---|---|---|---|---|
| US6110793A (en) * | 1998-06-24 | 2000-08-29 | Taiwan Semiconductor Manufacturing Company | Method for making a trench isolation having a conformal liner oxide and top and bottom rounded corners for integrated circuits |
| CN101312147A (en) * | 2007-05-23 | 2008-11-26 | 中芯国际集成电路制造(上海)有限公司 | Process for preparing isolation of shallow channel |
| CN101459116A (en) * | 2007-12-13 | 2009-06-17 | 中芯国际集成电路制造(上海)有限公司 | Shallow groove isolation construction manufacturing method |
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2012
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6110793A (en) * | 1998-06-24 | 2000-08-29 | Taiwan Semiconductor Manufacturing Company | Method for making a trench isolation having a conformal liner oxide and top and bottom rounded corners for integrated circuits |
| CN101312147A (en) * | 2007-05-23 | 2008-11-26 | 中芯国际集成电路制造(上海)有限公司 | Process for preparing isolation of shallow channel |
| CN101459116A (en) * | 2007-12-13 | 2009-06-17 | 中芯国际集成电路制造(上海)有限公司 | Shallow groove isolation construction manufacturing method |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111106057A (en) * | 2019-11-18 | 2020-05-05 | 华虹半导体(无锡)有限公司 | Method for manufacturing STI (shallow trench isolation) structure of flash memory device and flash memory device |
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| CN103681450B (en) | 2016-10-05 |
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