CN103681450B - The forming method of semiconductor device - Google Patents
The forming method of semiconductor device Download PDFInfo
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- CN103681450B CN103681450B CN201210348133.9A CN201210348133A CN103681450B CN 103681450 B CN103681450 B CN 103681450B CN 201210348133 A CN201210348133 A CN 201210348133A CN 103681450 B CN103681450 B CN 103681450B
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- substrate
- semiconductor device
- forming method
- oxide layer
- pad oxide
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02299—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment
- H01L21/02304—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment formation of intermediate layers, e.g. buffer layers, layers to improve adhesion, lattice match or diffusion barriers
Abstract
A kind of forming method of semiconductor device, including: substrate is provided；Etch described substrate, substrate is formed some isolated grooves；The substrate being formed with isolated groove is carried out；Formed and cover in substrate and substrate bottom isolated groove and the pad oxide layer of sidewall；Described pad oxide layer surface is carried out oxidation processes；Carry out annealing process.The forming method of semiconductor device of the present invention is before annealing to the substrate being formed with pad oxide layer, pad oxide layer surface is carried out oxidation processes, the siliconoxygen bond being positioned at pad oxide layer surface unstable is made to aoxidize, the silicon oxide that forming properties is stable, the silicon atom avoiding pad oxide layer surface runs off, and then avoid pad oxide layer surface to produce leakage current, improve stability and the yield rate of formed semiconductor device.
Description
Technical field
The present invention relates to field of semiconductor manufacture, particularly relate to the forming method of a kind of semiconductor device.
Background technology
Along with developing rapidly of semiconductor fabrication, semiconductor device in order to reach faster arithmetic speed,
Bigger information storage and more function, semiconductor chip develops to more high integration direction, i.e.
The characteristic size (CD, Critical Dimension) of semiconductor device is the least, and the collection of semiconductor chip
One-tenth degree is the highest.
Along with uprising of semiconductor chip integrated level, unit are needs the semiconductor device number of packages formed
Amount and type also get more and more, how the position of each semiconductor device of reasonable arrangement and utilize half and half to lead
Common ground in body device forming process saves semiconductor process step becomes the focus of research now.
Existing technique is when forming semiconductor device, and the active area of semiconductor device is mainly by substrate
Form isolation structure to define, referring to figs. 1 to Fig. 4, substrate is formed isolated groove and mainly includes as follows
Step: first, with reference to Fig. 1, it is provided that substrate 101, and formation comprises covering of channel patterns on the substrate 101
Film layer 103；Then, with reference to Fig. 2, with described mask layer 103 as mask, described lining is etched along channel patterns
The end 101, form isolated groove 105；With reference to Fig. 3, remove described mask layer 103, and to described substrate 101
It is carried out, to remain during removing the impurity being attached on substrate 101 and forming isolated groove 105
Polymer；Then, with reference to Fig. 4, form pad oxidation on the surface of substrate 101 and isolated groove 105
Layer 107；Finally, the substrate 101 being formed with pad oxide layer 107 in Fig. 4 is carried out annealing process, to repair
The damage that substrate 101 is caused by multiple etching technics.Wherein, the substrate 101 between isolated groove 105 is made
For the active area of semiconductor device, defining the position of semiconductor device in substrate 101, each active area can
Mutually isolated by fill oxide in isolated groove 105.
But, after an anneal process, find during surfaces of active regions is detected: by existing technique
There is damage in the surfaces of active regions formed, causes formed semiconductor device to be easily generated leakage current and generation
Puncturing, the yield rate of formed semiconductor device is relatively low.
In more multiple semiconductor devices, the forming method of active area refer to Publication No. CN102087960A
Chinese patent application.
Summary of the invention
The problem that the present invention solves is to provide the forming method of a kind of semiconductor device, it is to avoid at semiconductor device
In part, surfaces of active regions forms silicon damage, improves stability and the yield rate of formed semiconductor device.
For solving the problems referred to above, the invention provides the forming method of a kind of semiconductor device, including: carry
For substrate；Etch described substrate, substrate is formed some isolated grooves；To being formed with isolated groove
Substrate is carried out；Formed and cover in substrate and substrate bottom isolated groove and the pad oxide layer of sidewall；
Described pad oxide layer surface is carried out oxidation processes；Carry out annealing process.
Optionally, the method described pad oxide layer surface being carried out oxidation processes is wet treatment or does
Method processes.
Optionally, the solution of described wet treatment is sulfuric acid solution, and the time is 1min ~ 10min；Or institute
The solution stating wet treatment is hydrogen peroxide, and the time is 5min ~ 30min.
Optionally, the gas that described dry process uses is oxygen, and the flow of oxygen is
10000sccm ~ 20000sccm, the temperature of described dry process is 200 DEG C ~ 300 DEG C, and the time is
10min~30min。
Compared with prior art, technical solution of the present invention has the advantage that
Before the substrate being formed with pad oxide layer is carried out annealing process, pad oxide layer surface is entered
Row oxidation processes, makes the siliconoxygen bond being positioned at pad oxide layer surface unstable aoxidize, forms silicon oxide,
The siliconoxygen bond avoiding instability reacts with the impurity being attached to pad oxide layer surface, forms sulfurous acid,
And then avoid the silicon atom on pad oxide layer surface to run off, prevent from producing leakage current on pad oxide layer surface,
Improve stability and the yield rate of formed semiconductor device.
Accompanying drawing explanation
Fig. 1 ~ Fig. 4 is the cross-sectional view of the formed semiconductor device of existing technique；
Fig. 5 is the schematic flow sheet of one embodiment of forming method of semiconductor device of the present invention；
Fig. 6 ~ Fig. 8 be semiconductor device of the present invention one embodiment of forming method formed in semiconductor device
The cross-sectional view of part.
Detailed description of the invention
Understandable, below in conjunction with the accompanying drawings for enabling the above-mentioned purpose of the present invention, feature and advantage to become apparent from
The detailed description of the invention of the present invention is described in detail.
Elaborate a lot of detail in the following description so that fully understanding the present invention, but this
Bright other can also be used to be different from alternate manner described here implement, therefore the present invention is not by following
The restriction of disclosed specific embodiment.
The most as described in the background section, in the formed semiconductor device of existing technique there is damage in surfaces of active regions,
Formed semiconductor device is caused to be easily generated leakage current and puncture, the finished product of formed semiconductor device
Rate is low.
Through the research discovery of inventor, in semiconductor device, the damage of surfaces of active regions is due to substrate
When performing etching formation isolated groove, the silicon atom in substrate easily loses an electronics, forms positive monovalence
Silicon ion, the silicon ion of this positive monovalence easily with pad oxide layer in silicon oxide is combined, the silicon of formation instability
Oxygen key, when carrying out thermal anneal process, unstable siliconoxygen bond is easy in high temperature environments and is attached to pad
Hydroxyl and the water on oxide layer surface react, and form sulfurous acid, cause the silicon atom of surfaces of active regions
Run off, form damage in surfaces of active regions.During the use of semiconductor device, surfaces of active regions is easy
Producing leakage current, semiconductor device easily punctures, and the stability of formed semiconductor device is the highest, one-tenth
Product rate is low.
For drawbacks described above, technical solution of the present invention first forms on substrate isolated groove, then to shape
Become to have the substrate of isolated groove to be carried out, and shape on substrate and on the bottom of isolated groove and sidewall
Become pad oxide layer, then pad oxide layer is carried out oxidation processes, finally carries out annealing process, thus
Before annealing process, unstable siliconoxygen bond is converted into stable silicon oxide, it is to avoid in annealing process not
Stable siliconoxygen bond reacts with the hydroxyl and water that residue in pad oxide layer surface, and then can keep away
Exempt from silicon atom on active area to run off, improve yield rate and the stability of formed semiconductor device.
It is described in detail below in conjunction with the accompanying drawings.
With reference to Fig. 5, for the schematic flow sheet of one embodiment of forming method of semiconductor device of the present invention,
Including:
Step S1, it is provided that substrate, described substrate is formed some isolated grooves；
Step S2, is carried out the substrate being formed with isolated groove；
Step S3, is formed and covers in substrate surface and substrate bottom isolated groove and the pad oxidation of sidewall
Layer；
Step S4, carries out oxidation processes to described pad oxide layer surface；
Step S5, carries out annealing process；
Step S6, forms isolation structure in described isolated groove.
Fig. 6 ~ Fig. 8 be semiconductor device of the present invention one embodiment of forming method formed in semiconductor device
The cross-sectional view of part.In conjunction with Fig. 6 ~ Fig. 8, the forming method of semiconductor device of the present invention is done into
One step explanation.
With reference to Fig. 6, first, it is provided that substrate 201, described substrate 201 is formed with some isolated grooves 205.
Described substrate 201 can be silicon substrate, germanium silicon substrate or silicon-on-insulator (SOI).This enforcement
In example, described substrate 201 is silicon substrate.
Form some isolated grooves 205 on the substrate 201 to comprise the steps:
Substrate 201 is provided, and on described substrate 201, forms mask layer (not shown)；
Graphical described mask layer, forms groove figure on described mask layer；
With described mask layer as mask, etch described substrate 201 along groove figure, formed on the substrate 201
Some isolated grooves 205, active as semiconductor device of the substrate 201 between adjacent isolation trenches 205
District；
Remove described mask layer.
The material of described mask layer can be organic polymer material, but the invention is not restricted to this, and it may utilize
Those skilled in the art's other mask material known substitute.In the present embodiment, the material of described mask layer is
Photoresist, by described mask layer is exposed, is developed, forms groove figure.
With described mask layer as mask, the method etching described substrate 201 along groove figure is dry etching.
Concrete, the etching gas of described dry etching is CF4、CHF3, HBr and SF6In one or more,
Temperature is 50 DEG C ~ 100 DEG C, and the time is 1min ~ 10min, and pressure is 10mTorr ~ 30mTorr, power supply frequency
Rate is 800W ~ 1200W.
In the present embodiment, the method removing described mask layer is cineration technics.In other embodiments, go
Except the method for mask layer can select according to the material of mask layer to be removed.
Then, the substrate 201 being formed with isolated groove 205 in Fig. 6 is carried out.
In the present embodiment, the solution being carried out substrate 201 is sulphuric acid (H2SO4) solution, hydrogen peroxide
(H2O), ammonia (NH3·H2O) one or several and in Fluohydric acid. (HF) solution, by right
Described substrate 201 is carried out, it is possible to remove the polymer particles remained during forming isolated groove 205
Grain；Meanwhile, it is carried out substrate 201 removing the impurity being attached on substrate 201, is beneficial to
The formation of follow-up pad oxide layer.
It should be noted that existing technique after performing etching formation isolated groove 205 to substrate 201,
And then the isolated groove 205 formed is carried out, removes the polymer of etching technics residual；And
This cleaning covers bottom substrate 201 and isolated groove 205 and the pad oxygen of sidewall with being subsequently formed
Change layer and there is also certain time interval, in this time interval, substrate 201 and isolated groove 205
Bottom and sidewall are easily easily polluted by the external foreign matters or react with the gas in air, affect the oxidation of follow-up pad
The formation of layer.
Therefore, after substrate 201 is performed etching formation isolated groove 205, first pass through sulfuric acid solution,
Substrate 201 is once cleaned by one or several in hydrogen peroxide, ammonia or hydrofluoric acid solution,
Remove the polymer remained during forming isolated groove 205；Before forming pad oxide layer, pass through
Substrate 201 is carried out clearly by one or several in sulfuric acid solution, hydrogen peroxide or hydrofluoric acid solution again
Wash, remove the impurity being attached to bottom substrate 201 surface and isolated groove 205 and on sidewall, ensure
When forming pad oxide layer, bottom substrate 201 surface and isolated groove 205 and the cleaning of sidewall, enter
And ensure the form of pad oxide layer formed in subsequent technique.
With reference to Fig. 7, then, isolated groove 205 end is formed in covering substrate 201 surface and substrate 201
The pad oxide layer 207 of portion and sidewall.
The material of described pad oxide layer 207 is silicon oxide, the method forming described pad oxide layer 207
For thermal oxidation technology or chemical vapor deposition method.
In the present embodiment, form the method thermal oxidation technology of described pad oxide layer 207, as used oxidation
Stove performs, and in oxidation furnace, reacting gas is oxygen, and the temperature of gas is 1000 DEG C ~ 1200 DEG C, and flow is
10slm ~ 30slm, the response time is 1min ~ 5min.By forming pad oxide layer on substrate 201 surface
207, make the surfacing of substrate 201, it is to avoid electric charge substrate 201 surface convex portion accumulation and to lining
Damage is caused at the end 201, and then improves the stability of formed semiconductor device.
Then, described pad oxide layer 207 surface is carried out oxidation processes.
In the present embodiment, described oxidation processes is dry process, and the gas of described dry process is oxygen,
The flow of described oxygen is 10000sccm ~ 20000sccm, and described dry process temperature is 200 DEG C ~ 300
DEG C, the time is 10min ~ 30min.
In other embodiments, described oxidation processes can also be for wet treatment；Described wet treatment molten
Liquid is sulfuric acid solution or hydrogen peroxide；When the solution of wet treatment is sulfuric acid solution, wet treatment time
Between be 1min ~ 10min；When the solution of wet treatment is hydrogen peroxide, the time of wet treatment is
5min~30min。
By pad oxide layer 207 surface is carried out oxidation processes, pad oxide layer 207 surface can be made
Unstable siliconoxygen bond is transformed into the silicon dioxide of stable in properties.
Followed by, the substrate 201 that surface is formed pad oxide layer 207 carries out annealing process, to repair
Complex becomes in Fig. 6 during isolated groove 205, the damage that substrate 201 is caused by etching technics.
In the present embodiment, described annealing process is high-temperature thermal annealing (High Temperature Anneal, letter
It is referred to as HTA), the temperature of described high-temperature thermal annealing is 800 DEG C ~ 1200 DEG C, and the time of high-temperature thermal annealing is
60min~180min。
In carrying out annealing process procedure, owing to pad oxide layer 207 surface does not exist the silica of instability
Key, therefore, even if pad oxide layer 207 surface attachment has hydroxyl and water, is also not result in active area
The silicon atom on surface runs off, and then can avoid forming damage in surfaces of active regions.
With reference to Fig. 8, finally, isolation structure 209 is formed in the most described isolated groove 205.
In the present embodiment, the material of described isolation structure 209 is silicon oxide, forms isolation structure 209
Method is thermal oxidation technology or chemical vapor deposition method, and its concrete formation process is as art technology
The known technology of personnel, does not repeats at this.
In above-described embodiment, the substrate being formed with pad oxide layer is being carried out by the forming method of semiconductor device
Before annealing, pad oxide layer surface is carried out oxidation processes, make to be positioned at pad oxide layer surface unstable
Siliconoxygen bond aoxidize, form the silicon oxide of stable chemical nature, it is to avoid pad oxide layer surface is unstable
Fixed siliconoxygen bond and hydroxyl and water react the sulfurous acid forming liquid, and then can avoid substrate surface
Silicon atom runs off, and finally improves stability and the yield rate of formed semiconductor device.
Although the present invention discloses as above with preferred embodiment, but the present invention is not limited to this.Any
Skilled person, without departing from the spirit and scope of the present invention, all can make various changes or modifications,
Therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (13)
1. the forming method of a semiconductor device, it is characterised in that including:
Substrate is provided；
Etch described substrate, substrate is formed some isolated grooves；
The substrate being formed with isolated groove is carried out；
Formed and cover in substrate and substrate bottom isolated groove and the pad oxide layer of sidewall；
Described pad oxide layer surface is carried out oxidation processes；
Carry out annealing process；
Wherein, the described substrate to being formed with isolated groove be carried out particularly as follows:
Described substrate is once cleaned by one or several first passed through in sulfuric acid solution, hydrogen peroxide, ammonia and hydrofluoric acid solution, removes the polymer remained during forming described isolated groove；
By one or several in sulfuric acid solution, hydrogen peroxide and hydrofluoric acid solution, described substrate is carried out again again, removes the impurity being attached to bottom described substrate surface and described isolated groove and on sidewall.
2. the forming method of semiconductor device as claimed in claim 1, it is characterised in that the method that described pad oxide layer surface is carried out oxidation processes is wet treatment or dry process.
3. the forming method of semiconductor device as claimed in claim 2, it is characterised in that the solution of described wet treatment is sulfuric acid solution, and the time is 1min～10min.
4. the forming method of semiconductor device as claimed in claim 2, it is characterised in that the solution of described wet treatment is hydrogen peroxide, and the time is 5min～30min.
5. the forming method of semiconductor device as claimed in claim 2, it is characterized in that, the gas that described dry process uses is oxygen, and the flow of oxygen is 10000sccm～20000sccm, the temperature of described dry process is 200 DEG C～300 DEG C, and the time is 10min～30min.
6. the forming method of semiconductor device as claimed in claim 1, it is characterised in that the material of described pad oxide layer is silicon oxide.
7. the forming method of semiconductor device as claimed in claim 6, it is characterised in that the method forming described pad oxide layer is thermal oxidation technology or chemical vapor deposition method.
8. the forming method of semiconductor device as claimed in claim 1, it is characterised in that described annealing process is high-temperature thermal annealing；
Wherein, the temperature of described high-temperature thermal annealing is 800 DEG C～1200 DEG C.
9. the forming method of semiconductor device as claimed in claim 8, it is characterised in that the time of described high-temperature thermal annealing is 60min～180min.
10. the forming method of semiconductor device as claimed in claim 1, it is characterised in that the method etching described substrate is dry etching.
The forming method of 11. semiconductor device as claimed in claim 10, it is characterised in that the etching gas of described dry etching is CF4、CHF3, HBr and SF6In one or more, temperature is 50 DEG C～100 DEG C, and the time is 1min～10min, and pressure is 10mTorr～30mTorr, and supply frequency is 800W～1200W.
The forming method of 12. semiconductor device as claimed in claim 1, it is characterised in that after carrying out annealing process, also include: form isolation structure in described isolated groove.
The forming method of 13. semiconductor device as claimed in claim 12, it is characterised in that the material of described isolation structure is silicon oxide.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201210348133.9A CN103681450B (en) | 2012-09-18 | 2012-09-18 | The forming method of semiconductor device |
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| CN201210348133.9A CN103681450B (en) | 2012-09-18 | 2012-09-18 | The forming method of semiconductor device |
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| Publication Number | Publication Date |
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| CN103681450A CN103681450A (en) | 2014-03-26 |
| CN103681450B true CN103681450B (en) | 2016-10-05 |
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| CN111106057A (en) * | 2019-11-18 | 2020-05-05 | 华虹半导体(无锡)有限公司 | Method for manufacturing STI (shallow trench isolation) structure of flash memory device and flash memory device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6110793A (en) * | 1998-06-24 | 2000-08-29 | Taiwan Semiconductor Manufacturing Company | Method for making a trench isolation having a conformal liner oxide and top and bottom rounded corners for integrated circuits |
| CN101312147A (en) * | 2007-05-23 | 2008-11-26 | 中芯国际集成电路制造(上海)有限公司 | Process for preparing isolation of shallow channel |
| CN101459116A (en) * | 2007-12-13 | 2009-06-17 | 中芯国际集成电路制造(上海)有限公司 | Shallow groove isolation construction manufacturing method |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6110793A (en) * | 1998-06-24 | 2000-08-29 | Taiwan Semiconductor Manufacturing Company | Method for making a trench isolation having a conformal liner oxide and top and bottom rounded corners for integrated circuits |
| CN101312147A (en) * | 2007-05-23 | 2008-11-26 | 中芯国际集成电路制造(上海)有限公司 | Process for preparing isolation of shallow channel |
| CN101459116A (en) * | 2007-12-13 | 2009-06-17 | 中芯国际集成电路制造(上海)有限公司 | Shallow groove isolation construction manufacturing method |
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