CN103794548A - Method for forming local interconnection structure - Google Patents
Method for forming local interconnection structure Download PDFInfo
- Publication number
- CN103794548A CN103794548A CN201210428518.6A CN201210428518A CN103794548A CN 103794548 A CN103794548 A CN 103794548A CN 201210428518 A CN201210428518 A CN 201210428518A CN 103794548 A CN103794548 A CN 103794548A
- Authority
- CN
- China
- Prior art keywords
- metal
- contact hole
- dielectric layer
- formation method
- local interconnect
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
Abstract
A method for forming a local interconnection structure comprises the following steps: providing a semiconductor substrate of which the surface has a shallow trench isolation structure, a first metal gate structure surrounded by the shallow trench isolation structure and disposed above the semiconductor substrate, and a first dielectric layer flush with the first metal gate structure; forming a second dielectric layer and a third dielectric layer, which cover the first metal gate structure, on the surface of the first dielectric layer; exposing the surfaces of a source and a drain to form first contact holes; forming a metal silicide layer on the surfaces of the source and the drain; filling a fourth dielectric material in the first contact hole and forming a fourth dielectric layer; exposing the surface of the first metal gate structure to form a second contact hole; removing the fourth dielectric layer; and filling metal material in the first contact holes and the second contact hole to form a plug. By the adoption of the method forming a local interconnection structure, the steps of the process can be simplified, and the metal gate can be protected.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly a kind of formation method of local interconnect structure.
Background technology
Along with the development of ic manufacturing technology, the characteristic size of MOS transistor is also more and more less, according to scaled rule, in the time dwindling the overall dimensions of MOS transistor, has also dwindled source electrode, drain electrode, grid, the isostructural size of connector simultaneously.Owing to having difference in height between the grid structure of MOS transistor and source/drain electrode, in contact hole on forming grid structure and source/drain electrode, because the height of source electrode, drain and gate structure is inconsistent, forming contact hole and form contact hole on grid structure surface in source electrode and drain surface wants the degree of depth of etching different, can become very difficult, easily make grid be sustained damage by over etching.
After rear grid technique is prepared MOS transistor, conventionally form contact hole by Twi-lithography etching technics on the surface of source electrode, drain surface and the metal gates of MOS transistor, to address the above problem at present.
Please refer to Fig. 1, have isolation structure of shallow trench 20 in Semiconductor substrate 10, in the active area surrounding at described isolation structure of shallow trench 20, after adopting, grid technique forms MOS transistor.Described transistor comprises source electrode 11, drain electrode 12, metal-gate structures, and described metal-gate structures comprises metal gates 13, gate dielectric layer 14.Described semiconductor substrate surface has dielectric layer 30, the flush of the surface of described dielectric layer 30 and metal gates 13.
Please refer to Fig. 2, dielectric layer 30 described in etching, forms the first contact hole 41, and described the first contact hole 41 exposes the surface of source electrode 11 and drain electrode 12.Then, form metal silicide layer 50 on the surface of described source electrode 11 and drain electrode 12.The technique that forms metal silicide layer comprises, forms the processing of metal level after annealing at source electrode and drain surface, dielectric layer surface, the first contact hole sidewall, forms metal silicide layer 50 at described source electrode and drain surface.Then remove described metal level.Because metal gates 13 exposes, so also can form metal level on its surface, in the step of follow-up removal metal level, metal gates 13 easily sustains damage.
Please refer to Fig. 3, in the first contact hole, fill after metal material, described metal material planarization is formed to the first metal plug 42, described the first metal plug and metal gates 13 flush.In the process of described planarization, because metal gates 13 exposes, easily sustain damage.
Please refer to Fig. 4, form the 3rd dielectric layer 60 on described dielectric layer 30, the first metal plug 42, metal gates surface.The 3rd dielectric layer 60 described in etching, forms second contact hole 43 on the first metal plug surface and the 3rd contact hole 44 on metal gates 13 surfaces.Now, form the second contact hole 43 identical with the etching depth of the 3rd contact hole 44, can not make metal gates by over etching.
Please refer to Fig. 5, in the second contact hole and the 3rd contact hole, fill after metal material, form the second metal plug 45 and the 3rd metal plug 46.The second metal plug 45 and the first metal plug 42 have formed the metal plug at source electrode and drain electrode top.
In prior art, need by the planarization of twice etching and twice pair of metal plug, processing step complexity.And described metal gates easily sustains damage in the process of source electrode and drain electrode formation silicide layer and formation the first metal plug, affects transistorized performance.
More patents about formation contact hole please refer to the patent document that US publication is US7615494B2.
Summary of the invention
The problem that the present invention solves is a kind of formation method that proposes local interconnect structure, and the formation method of described local interconnect structure can simplify technique and protection metal gate is injury-free.
For addressing the above problem, the present invention proposes a kind of formation method of local interconnect structure, comprise: Semiconductor substrate is provided, described semiconductor substrate surface has isolation structure of shallow trench, is positioned at the first metal gates being surrounded by isolation structure of shallow trench and the first grid dielectric layer of Semiconductor substrate top, and described semiconductor substrate surface also has the first medium layer with the first metal-gate structures flush; Form the second medium layer that covers described the first metal-gate structures and the 3rd dielectric layer that is positioned at second medium layer surface on described first medium layer surface; Etching is positioned at the 3rd dielectric layer, second medium layer and the first medium layer directly over source electrode and drain electrode, exposes the surface of source electrode and drain electrode, forms the first contact hole; Form metal silicide layer at source electrode and drain surface; In described the first contact hole, fill the 4th dielectric material, described the 4th dielectric material is filled full the first contact hole and is covered the 3rd dielectric layer surface and forms the 4th dielectric layer; Etching is positioned at the 4th dielectric layer, the 3rd dielectric layer and the second medium layer directly over the first metal gates, exposes the surface of the first metal gates, forms the second contact hole; Remove the 4th dielectric layer; In described the first contact hole and the second contact hole, fill metal material, and to described metal material planarization, form connector.
Preferably, described semiconductor substrate surface also has the second metal-gate structures that is positioned at isolation structure of shallow trench surface, described the second metal-gate structures comprises the second metal gates and second gate dielectric layer, the bottom width of described the second metal-gate structures is less than the width of isolation structure of shallow trench, and is positioned at the surface of isolation structure of shallow trench completely.
Preferably, described the second metal-gate structures is connected with other transistors by connector as interconnection structure.
Preferably, described the second contact hole is formed on the surface of the second metal gates.
Preferably, described the second contact holes exposing goes out the part or all of surface of the first metal gates or the second metal gates.
Preferably, described the second contact hole and first contact hole adjacent with isolation structure of shallow trench are communicated with, and expose the surface of the part or all of surface of the second metal gates and the first medium layer between the second metal-gate structures and the first contact hole.
Preferably, the material of described first medium layer is silica.
Preferably, the material of described second medium layer is silicon nitride.
Preferably, the material of described the 3rd dielectric layer is silica.
Preferably, described the 4th dielectric material is bottom anti-reflective material.
Preferably, the technique of described removal the 4th dielectric layer is cineration technics.
Preferably, be tungsten to the metal material of filling in described the first contact hole and the second contact hole.
Preferably, the metal silicide forming in source electrode and drain surface is several combination in a kind of or nickle silicide in nickle silicide, titanium silicide, tungsten silicide, cobalt silicide, silication lead, platinum silicide, titanium silicide, tungsten silicide, cobalt silicide, silication lead, platinum silicide.
Preferably, the technique of formation the first contact hole is plasma etching.
Preferably, the technique of formation the second contact hole is plasma etching.
Compared with prior art, the present invention has the following advantages:
Technical scheme of the present invention, first form second medium layer and the 3rd dielectric layer on surface and the first metal-gate structures surface of first medium layer, then the 3rd dielectric layer, second medium layer and first medium layer described in etching successively, directly over transistorized source electrode and drain electrode, form the first contact hole, then form metal silicide on the surface of source electrode and drain electrode.Form in the process of metal silicide in described source electrode and drain surface, first will be at source electrode and drain electrode and the 3rd dielectric layer forming metal layer on surface after annealing, then remove described metal level.In technical scheme of the present invention, the first metal-gate structures is covered by second medium layer and the 3rd dielectric layer, so can not cause damage to the first metal-gate structures in the time removing metal level.Technical scheme of the present invention is after surfaces of active regions forms silicide, directly over the first metal-gate structures, form again the second contact hole, in the first contact hole and the second contact hole, fill metal material simultaneously after to described metal material carry out planarization form connector.Technical scheme of the present invention, only filling and the flatening process of needs one minor metal, simplified processing step.And in flatening process, metal gates does not expose, can not sustain damage.
Further, technical scheme of the present invention can also form the second contact hole at the second metal-gate structures top that is positioned at isolation structure of shallow trench surface, and form the second connector, described the second metal-gate structures as interconnection structure with can be connected with other MOS transistor, make to be connected to each other between the MOS transistor in Semiconductor substrate, be conducive to improve wiring density and wiring selectivity.
Accompanying drawing explanation
Fig. 1 to Fig. 5 is the generalized section of formation local interconnect structure of the prior art of the present invention;
Fig. 6 to Figure 15 is the generalized section of the formation local interconnect structure in the first embodiment of the present invention;
Figure 16 to Figure 19 is the generalized section of the formation local interconnect structure in the second embodiment of the present invention.
Embodiment
Because the height of transistorized source electrode, drain and gate structure is inconsistent, form contact hole and form contact hole on grid structure surface in source electrode and drain surface and want the degree of depth of etching different, easily make grid structure by over etching, sustain damage.If can make grid structure sustain damage so form contact hole in source electrode, drain and gate superstructure etching simultaneously, affect the performance of device.
And in prior art, respectively source is leaked and etching is carried out in grid structure top, the method for formation contact hole need to be carried out the filling of two minor metals and smooth, processing step complexity.And, forming in the process of silicide at source electrode and drain surface, metal gates exposes, and easily sustains damage, and affects the performance of electronic device.
For addressing the above problem, technical scheme of the present invention has proposed a kind of formation method of local interconnect structure.Surface, the first metal-gate structures surface at first medium layer form after second medium layer and the 3rd dielectric layer, first, the 3rd dielectric layer, second medium layer and first medium layer described in etching successively, directly over transistorized source electrode and drain electrode, form the first contact hole, then form metal silicide on the surface of source electrode and drain electrode, directly over the first metal-gate structures, form again the second contact hole, in the first contact hole and the second contact hole, fill metal material after to described metal material carry out planarization form connector.The formation method of described local interconnect structure, processing step is simple, and can protect grid injury-free.
For above-mentioned purpose of the present invention, feature and advantage can more be become apparent, below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.Described embodiment is only a part for embodiment of the present invention, rather than they are whole.Describing in detail when the embodiment of the present invention, for ease of explanation, schematic diagram can be disobeyed general ratio and be done local amplification, and described schematic diagram is example, and it should not limit the scope of the invention at this.In addition in actual fabrication, should comprise, the three-dimensional space of length, width and the degree of depth.According to described embodiment, those of ordinary skill in the art is obtainable all other execution modes under the prerequisite without creative work, all belong to protection scope of the present invention.Therefore the present invention is not subject to the restriction of following public concrete enforcement.
The first embodiment
Concrete, please refer to Fig. 6 to Figure 15, be the generalized section that forms local interconnect structure in the first embodiment.
Please refer to Fig. 6, Semiconductor substrate 100 is provided, described Semiconductor substrate 100 surfaces have MOS transistor, surround isolation structure of shallow trench 102 and the first medium layer 111 of described MOS transistor.Described isolation structure of shallow trench 102 surfaces also have the second metal-gate structures.
Concrete, in the present embodiment, the material of described Semiconductor substrate 100 is the semi-conducting materials such as silicon, germanium, SiGe, GaAs.Those skilled in the art can select according to the semiconductor device forming in Semiconductor substrate 100 type of described Semiconductor substrate 100, and therefore the type of described Semiconductor substrate should not limit the scope of the invention.In the present embodiment, Semiconductor substrate 100 is body silicon.
First in Semiconductor substrate, form the isolation structure of shallow trench 102 around active area, formation method is: after in Semiconductor substrate, etching forms shallow trench, form one deck pad oxide in flute surfaces, then fill full dielectric material in groove after, planarization forms fleet plough groove isolation structure 102.
In the active area surrounding at described isolation structure of shallow trench 102 again, form MOS transistor.After described MOS transistor adopts, grid technique forms.After forming the etching barrier layer 110 on the side wall 107 of the pseudo-grid of source electrode 108, drain electrode 109 and polysilicon and both sides thereof, surface, etching is removed the pseudo-grid of described polysilicon.And planarization deposit gate dielectric material layer and metal level in the groove of the pseudo-grid of described removal polysilicon after, forms first grid dielectric layer 101 and the first metal gates 106, and described first grid dielectric layer and the first metal gates form the first metal-gate structures.
Concrete, the formation technique of described source electrode 108 and 109 can be: carry out etching at semiconductor substrate surface and form groove, and in groove, utilize epitaxy technique to fill full germanium silicon material or carbofrax material, form source electrode and drain electrode, described germanium silicon material or carbofrax material at epitaxy technique situ doped with P type or N-type foreign ion.In other embodiments, also can form after described germanium silicon material or carbofrax material, utilize ion implantation technology in described germanium silicon material or carbofrax material doped with foreign ion.Utilize described germanium silicon material or carbofrax material to form source electrode and the lattice generation effect of stress of drain electrode meeting to MOS transistor channel region, be conducive to improve the migration rate of channel region charge carrier, improve transistorized electric property.In other embodiments of the invention, also can carry out P type or N-type Implantation to described source electrode and drain region, and carry out annealing in process, form source electrode 108 and drain electrode 109.
In the present embodiment, in forming the first metal-gate structures of MOS transistor, form the second metal-gate structures on described isolation structure of shallow trench 102 surfaces, described the second metal gates 104 and the first metal gates 106 are communicated with simultaneously.Described the second metal-gate structures comprises the second metal gates 104 and second gate dielectric layer 103.Described the second metal gates both sides have side wall 105.Described the second metal-gate structures is connected with other transistors by metal plug as interconnection structure.The bottom width of described the second metal-gate structures is less than or equal to the face width of described isolation structure of shallow trench 102, and is positioned at the top of isolation structure of shallow trench 102 completely.
Described etching barrier layer 110 surfaces also have first medium layer 111, the flush of the surface of first medium layer 111 and the first metal gates 106, the second metal gates 104.The material of described first medium layer 111 is silica.
Please refer to Fig. 7, form second medium layer 120 and the 3rd dielectric layer 130 that is positioned at second medium layer surface at semiconductor substrate surface.
Concrete, described second medium layer 120 is silicon nitride layer, as the etch stop layer of follow-up formation the second contact hole.Described the 3rd dielectric layer 130 is silicon oxide layer.The technique that forms described second medium layer 120 and the 3rd dielectric layer 130 is chemical vapour deposition (CVD).Described second medium layer 120 and the 3rd dielectric layer 130 form protection to metal gates in subsequent technique.
Please refer to Fig. 8, form graphical photoresist layer 140 on described the 3rd dielectric layer 130 surfaces.
Concrete, form after photoresist layer in the surperficial spin coating of the 3rd dielectric layer 130, by described photoresist layer is carried out to exposure imaging, form graphical photoresist layer 140.The graphics field that does not cover photoresist be positioned at source electrode 108 and drain electrode 109 directly over, correspond to the position that forms the first contact hole.The width of described graphics field is less than or equal to the face width of described source electrode and drain electrode.
Please refer to Fig. 9, take described graphical photoresist layer 140 as mask, etching is positioned at the 3rd dielectric layer 130, second medium layer 120 and first medium layer 111 directly over source electrode 108 and drain electrode 109 and etching barrier layer 110 and exposes the surface of source electrode 108 and drain electrode 109, forms the first contact hole 210.
Concrete, take described graphical photoresist layer 140 as mask, downward etching the 3rd dielectric layer 130, second medium layer 120 successively, first medium layer 111 and etching barrier layer 110, until expose the surface of source electrode 108 and drain electrode 109, form the first contact hole.The width of described the first contact hole is less than or equal to the face width of source electrode or drain electrode, and described etching technics is plasma etching.
Please refer to Figure 10, remove photoresist layer 140(and please refer to Fig. 9) after form metal silicide layers 201 at source electrode 108 and drain electrode 109 surfaces.
Concrete, in the present embodiment, remove described photoresist layer 140(and please refer to Fig. 9) technique be cineration technics.In other embodiments of the invention, also can adopt the method for wet etching to remove described photoresist layer 140.
The material of described metal silicide layer 201 is one or more the combination in nickle silicide, titanium silicide, tungsten silicide, cobalt silicide, silication lead, platinum silicide.In embodiments of the invention, the material of described metal silicide layer 201 is nickle silicide, adopts the technique of two step silication to form.First, adopt evaporation or sputtering technology, at the surface of source electrode 108, drain electrode 109 and the 3rd dielectric layer 130 and the side wall deposition Ni metal level of the first contact hole 210, then adopt boiler tube or short annealing equipment, in high-purity nitrogen environment, low temperature short annealing, for example 260 ℃ of reaction temperatures, 30 seconds duration, form rich nickel phase silicide; Subsequently, adopt the method for wet etching, remove unnecessary Ni metal level; Finally, adopt high temperature rapid thermal annealing, for example 500 ℃ of reaction temperatures, 30 seconds duration, rich nickel phase silicide is undergone phase transition, form silicide layer 201.In other embodiments of the invention, can also adopt a step silicification technics: first adopt evaporation or sputtering technology, at the surface at source electrode 108, drain electrode 109 and second medium layer 130 and the side wall deposition layer of Ni metal level of the first contact hole 210; Adopt boiler tube or short annealing equipment, high temperature rapid thermal annealing under highly purified nitrogen environment, forms nickel silicide; Finally, adopt wet etching method, remove unnecessary Ni, form metal silicide layer 201.In other embodiments of the invention, described metal level can also be one or more metallic elements in Ni, Ta, Ti, W, Co, Pt or Pd.
In the process of described formation metal silicide, because metal gate surface coverage has second medium layer 120 and the 3rd dielectric layer 130, so form in the process of metal silicide at source electrode and drain surface, can not form Ni metal levels at the first metal gates 106 and the second metal gates 104 surface, follow-uply in the time of removal Ni metal level, can not cause damage to the first metal gates 106 and the second metal gates 104.And in prior art, owing to forming in silicide process, also can form metal level on metal gates surface, in removing metal level, can also cause damage to metal gates.
Please refer to Figure 11, fill the 4th dielectric material in described the first contact hole, described the 4th dielectric material is filled full the first contact hole and is covered the 3rd dielectric layer surface and forms the 4th dielectric layer 150.
Concrete, described the 4th dielectric material is bottom anti-reflective material.Because described bottom anti-reflective material has mobility, can form by spin coating proceeding the 4th dielectric layer 150 of surfacing, do not need additionally to carry out planarization, can save processing step, reduce process costs.In other embodiments of the invention, also can adopt depositing operation, filled media material in the first contact hole, then carry out planarization formation the 4th dielectric layer.
Please refer to Figure 12, form graphical photoresist layer 160 on described the 4th dielectric layer 150 surfaces.
Concrete, form after photoresist layer in the surperficial spin coating of the 4th dielectric layer 150, by described photoresist layer is carried out to exposure imaging, form graphical photoresist layer 160.In the present embodiment, the graphics field that does not cover photoresist be positioned at the second metal gates 104 directly over, correspond to the position that forms the second contact hole, the width of described graphics field is less than or equal to the width of the second metal gates 104.In other embodiments of the invention, the described graphics field that does not cover photoresist also can be positioned at the first metal gates 106 directly over, form the second contact hole at the top of described the first metal gates 106.
Please refer to Figure 13, take described graphical photoresist layer 160 as mask, etching the 4th dielectric layer 150, the 3rd dielectric layer 130 and second medium layer 120, expose the surface of the second metal gates 104, forms the second contact hole 220.
Concrete, take described graphical photoresist layer 160 as mask, downward etching the 4th dielectric layer 150, the 3rd dielectric layer 130, second medium layer 120 successively, until expose the part or all of surface of the second metal gates 104, forms the second contact hole 220.The width of described the second contact hole is less than or equal to the face width of the second metal gates 104.In the present embodiment, described the second metal gates 104 and the first metal gates 106 are communicated with, so can form the second connector after the second contact hole is formed on the second metal gates 104 tops that are positioned at isolation structure of shallow trench surface, as the syndeton of described MOS transistor.In other embodiments of the invention, described the second metal gates 104 is not communicated with the first metal gates 106, after the second contact hole is formed on described the second metal gates 104 tops, form the second connector, described the second metal-gate structures can be used as interconnection structure and can be connected with other MOS transistor, make to be connected to each other between the MOS transistor in Semiconductor substrate, be conducive to improve wiring density and wiring selectivity.In other embodiments of the invention, described the second contact hole also can directly be formed at the first metal gates 106 tops of MOS transistor, as the syndeton of described MOS transistor.。
Please refer to Figure 14, remove graphical photoresist layer 160(and please refer to Figure 13) and the 4th dielectric layer 150(please refer to Figure 13).
Concrete, because photoresist and bottom anti-reflective material are all for the organic substance being made up of elements such as C, O, H, N forms, so adopt cineration technics in the present embodiment, described graphical photoresist layer and the 4th dielectric layer are removed simultaneously, expose the first contact hole 210 and the second contact hole 220.In other embodiments of the invention, also can adopt wet etching to remove described graphical photoresist layer and the 4th dielectric layer.
Please refer to Figure 15, please refer to Figure 14 at described the first contact hole 210() and the second contact hole 220(please refer to Figure 14) in fill metal material, and carry out planarization and form the first connector 211 and the second connector 221.
Concrete, described metal material is tungsten.After utilizing full described the first contact hole 210 of fill process filling and the second contact hole 220, by chemical mechanical milling tech, take the 3rd dielectric layer 130 as grinding barrier layer, remove the tungsten on the 3rd dielectric layer surface, form the first connector 211 and the second connector 221.Only once metal filled and planarisation step has just formed the first connector and the second connector simultaneously in the present embodiment.Compared with prior art, simplified processing step.And connector being carried out in the process of planarization, the first metal-gate structures is protected, can not be subject to causing damage in the process of planarization.In the present embodiment, described the second metal gates 104 and the first metal gates 106 are communicated with, and form the second connector, as the syndeton of described MOS transistor after the second contact hole is formed on the second metal gates 104 tops that are positioned at isolation structure of shallow trench surface.
In other embodiments of the invention, described the second metal gates 104 also can not be communicated with the first metal gates 106, after the second contact hole is formed on described the second metal gates 104 tops, form the second connector, described the second metal-gate structures can be used as interconnection structure and can be connected with other MOS transistor, make to be connected to each other between the MOS transistor in Semiconductor substrate, be conducive to improve wiring density and wiring selectivity.In other embodiments of the invention, described the second contact hole also can directly be formed at the first metal gates 106 tops of MOS transistor, as the syndeton of described MOS transistor.
The second embodiment
In another embodiment of the present invention, described the second metal-gate structures is not communicated with the first metal-gate structures of MOS transistor, can directly form the connection between the second metal-gate structures and MOS transistor source electrode 108.
Please refer to Figure 16, after adopting method formation the 4th dielectric layer 150 in the first embodiment, form graphical photoresist layer 170 on described the 4th dielectric layer 150 surfaces.
Concrete, form after photoresist layer in the surperficial spin coating of the 4th dielectric layer 150, by described photoresist layer is carried out to exposure imaging, form graphical photoresist layer 170.The graphics field that does not cover photoresist is positioned at the second metal-gate structures top to the first contact hole top, corresponds to the position that forms the second contact hole.The width of described graphics field is greater than the width of metal gate, across the position of metal gate and the first contact hole.
Please refer to Figure 17, take described graphical photoresist layer 170 as mask, etching the 4th dielectric layer 150, the 3rd dielectric layer 130, second medium layer 120 form the second contact hole 230.
16. is concrete, and take described graphical photoresist layer 170 as mask, downward etching the 4th dielectric layer 150, the 3rd dielectric layer 130, second medium layer 120 are until expose the surface of the second metal gates, formation the second contact hole 230 successively.Described the second contact hole 230 is across the subregion of the first extremely adjacent with the second metal gates 104 contact hole of the surface of the second metal gates 104.Expose the surface of the part or all of surface of the second metal gates 104 and the first medium layer between the second metal-gate structures and the first contact hole.
Please refer to Figure 18, remove graphical photoresist layer 170(and please refer to Figure 17) and the 4th dielectric layer 150(please refer to Figure 17).
Concrete, because photoresist and bottom anti-reflective material are all for the organic substance being made up of elements such as C, O, H, N forms, so adopt cineration technics in the present embodiment, described graphical photoresist layer and the 4th dielectric layer are removed simultaneously.After removing described graphical photoresist layer and the 4th dielectric layer, the second contact hole 230(originally please refer to Figure 17) and adjacent the first contact hole between be communicated with, form the 3rd contact hole 240.
Please refer to Figure 19, at described the first contact hole 210 and the interior filling metal material of the 3rd contact hole 240, and carry out planarization and form the first connector 211 and the 3rd connector 241.
Concrete, described metal material is tungsten.After utilizing full described the first contact hole of fill process filling and the 3rd contact hole, by chemical grinding technique, take the 3rd dielectric layer 130 as grinding barrier layer, planarization forms the first connector 211 and the 3rd connector 241.Described the 3rd connector 241 connects the second metal gate 104 and source electrode 108 simultaneously.Thereby directly realize the connection of the source electrode 108 of the second metal gates and MOS transistor.
Above-mentioned by the explanation of embodiment, should be able to make professional and technical personnel in the field understand better the present invention, and can reproduce and use the present invention.Those skilled in the art can do not depart from the spirit and scope of the invention in the situation that to above-described embodiment do various changes according to described principle herein and modification is apparent.Therefore, the present invention should not be understood to be limited to above-described embodiment shown in this article, and its protection range should be defined by appending claims.
Claims (15)
1. a formation method for local interconnect structure, is characterized in that, comprising:
Semiconductor substrate is provided, described semiconductor substrate surface has isolation structure of shallow trench, is positioned at Semiconductor substrate top, source electrode and the drain electrode of the first metal-gate structures being surrounded by isolation structure of shallow trench, the Semiconductor substrate that is positioned at the first metal-gate structures both sides, described the first metal-gate structures comprises the first metal gates and first grid dielectric layer, and described semiconductor substrate surface also has the first medium layer with the first metal-gate structures flush;
Form the second medium layer that covers described the first metal-gate structures and the 3rd dielectric layer that is positioned at second medium layer surface on described first medium layer surface;
Etching is positioned at the 3rd dielectric layer, second medium layer and the first medium layer directly over source electrode and drain electrode, exposes the surface of source electrode and drain electrode, forms the first contact hole;
Form metal silicide layer at source electrode and drain surface;
In described the first contact hole, fill the 4th dielectric material, described the 4th dielectric material is filled full the first contact hole and is covered the 3rd dielectric layer surface and forms the 4th dielectric layer;
Etching is positioned at the 4th dielectric layer, the 3rd dielectric layer and the second medium layer directly over the first metal gates, exposes the surface of the first metal gates, forms the second contact hole;
Remove the 4th dielectric layer;
In described the first contact hole and the second contact hole, fill metal material, and to described metal material planarization, form connector.
2. the formation method of local interconnect structure according to claim 1, it is characterized in that, described semiconductor substrate surface also has the second metal-gate structures that is positioned at isolation structure of shallow trench surface, described the second metal-gate structures comprises the second metal gates and second gate dielectric layer, the bottom width of described the second metal-gate structures is less than the width of isolation structure of shallow trench, and is positioned at the surface of isolation structure of shallow trench completely.
3. the formation method of local interconnect structure according to claim 2, is characterized in that, described the second metal-gate structures is connected with other transistors by connector as interconnection structure.
4. the formation method of local interconnect structure according to claim 3, is characterized in that, described the second contact hole is formed on the surface of the second metal gates.
5. according to the formation method of the local interconnect connecting structure described in claim 1 or 4, it is characterized in that, described the second contact holes exposing goes out the part or all of surface of the first metal gates or the second metal gates.
6. the formation method of local interconnect structure according to claim 4, it is characterized in that, described the second contact hole and first contact hole adjacent with isolation structure of shallow trench are communicated with, and expose the surface of the part or all of surface of the second metal gates and the first medium layer between the second metal-gate structures and the first contact hole.
7. the formation method of local interconnect connecting structure according to claim 1, is characterized in that, the material of described first medium layer is silica.
8. the formation method of local interconnect connecting structure according to claim 1, is characterized in that, the material of described second medium layer is silicon nitride.
9. the formation method of local interconnect connecting structure according to claim 1, is characterized in that, the material of described the 3rd dielectric layer is silica.
10. the formation method of local interconnect connecting structure according to claim 1, is characterized in that, described the 4th dielectric material is bottom anti-reflective material.
The formation method of 11. local interconnect connecting structures according to claim 1, is characterized in that, the technique of described removal the 4th dielectric layer is cineration technics.
The formation method of 12. local interconnect connecting structures according to claim 1, is characterized in that, is tungsten to the metal material of filling in described the first contact hole and the second contact hole.
The formation method of 13. local interconnect connecting structures according to claim 1, it is characterized in that, the metal silicide forming in source electrode and drain surface is several combination in wherein a kind of or nickle silicide in nickle silicide, titanium silicide, tungsten silicide, cobalt silicide, silication lead, platinum silicide, titanium silicide, tungsten silicide, cobalt silicide, silication lead, platinum silicide.
The formation method of 14. local interconnect connecting structures according to claim 1, is characterized in that, the technique that forms the first contact hole is plasma etching.
The formation method of 15. local interconnect connecting structures according to claim 1, is characterized in that, the technique that forms the second contact hole is plasma etching.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210428518.6A CN103794548B (en) | 2012-10-31 | 2012-10-31 | The formation method of local interconnect structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210428518.6A CN103794548B (en) | 2012-10-31 | 2012-10-31 | The formation method of local interconnect structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103794548A true CN103794548A (en) | 2014-05-14 |
| CN103794548B CN103794548B (en) | 2016-02-17 |
Family
ID=50670087
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210428518.6A Active CN103794548B (en) | 2012-10-31 | 2012-10-31 | The formation method of local interconnect structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103794548B (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104505460A (en) * | 2014-12-25 | 2015-04-08 | 上海华虹宏力半导体制造有限公司 | Preparing method of triaxial anisotropic magnetoresistor |
| CN105575885A (en) * | 2014-10-14 | 2016-05-11 | 联华电子股份有限公司 | Semiconductor element and manufacturing method thereof |
| CN108122824A (en) * | 2016-11-30 | 2018-06-05 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN108666270A (en) * | 2017-03-29 | 2018-10-16 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN109427677A (en) * | 2017-08-24 | 2019-03-05 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070155157A1 (en) * | 2006-01-04 | 2007-07-05 | Pei-Yu Chou | Structure of Metal Interconnect and Fabrication Method Thereof |
| CN101286473A (en) * | 2007-04-13 | 2008-10-15 | 中芯国际集成电路制造(上海)有限公司 | Fabricating method for semiconductor device |
| CN102347270A (en) * | 2010-07-28 | 2012-02-08 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing contact plug |
-
2012
- 2012-10-31 CN CN201210428518.6A patent/CN103794548B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070155157A1 (en) * | 2006-01-04 | 2007-07-05 | Pei-Yu Chou | Structure of Metal Interconnect and Fabrication Method Thereof |
| CN101286473A (en) * | 2007-04-13 | 2008-10-15 | 中芯国际集成电路制造(上海)有限公司 | Fabricating method for semiconductor device |
| CN102347270A (en) * | 2010-07-28 | 2012-02-08 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing contact plug |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105575885A (en) * | 2014-10-14 | 2016-05-11 | 联华电子股份有限公司 | Semiconductor element and manufacturing method thereof |
| CN105575885B (en) * | 2014-10-14 | 2021-07-06 | 联华电子股份有限公司 | Semiconductor element and manufacturing method thereof |
| CN104505460A (en) * | 2014-12-25 | 2015-04-08 | 上海华虹宏力半导体制造有限公司 | Preparing method of triaxial anisotropic magnetoresistor |
| CN104505460B (en) * | 2014-12-25 | 2017-12-22 | 上海华虹宏力半导体制造有限公司 | The preparation method of 3 axle anisotropic magnetoresistives |
| CN108122824A (en) * | 2016-11-30 | 2018-06-05 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN108666270A (en) * | 2017-03-29 | 2018-10-16 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN109427677A (en) * | 2017-08-24 | 2019-03-05 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103794548B (en) | 2016-02-17 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9087856B2 (en) | Semiconductor device with buried bit line and method for fabricating the same | |
| JP2013521651A (en) | Floating body cell, device including floating body cell, and method for forming floating body cell. | |
| CN103050407B (en) | Embedded Transistor | |
| US8623727B2 (en) | Method for fabricating semiconductor device with buried gate | |
| CN103794548B (en) | The formation method of local interconnect structure | |
| TW202143391A (en) | Semiconductor device structure with air gap structure and method for preparing the same | |
| TWI582841B (en) | Method for fabricating transistor gate and semiconductor device comprising transistor gate | |
| US7682450B2 (en) | Stacked semiconductor device and related method | |
| CN102376686B (en) | Semiconductor device and production method thereof | |
| CN104733374A (en) | Metal interconnecting structure and forming method thereof | |
| US9460957B2 (en) | Method and structure for nitrogen-doped shallow-trench isolation dielectric | |
| JP2012089772A (en) | Method of manufacturing semiconductor device | |
| US20080124814A1 (en) | Method for passivation of plasma etch defects in DRAM devices | |
| TW201637175A (en) | Capacitor strap connection structure and fabrication method | |
| JP3923014B2 (en) | Memory cell with trench and method of manufacturing the same | |
| US11742382B2 (en) | Method for preparing semiconductor device with air gap and boron nitride cap | |
| US9087928B2 (en) | High density memory cells using lateral epitaxy | |
| KR20110080783A (en) | Method of manufacturing semiconductor device | |
| CN106158640A (en) | A kind of semiconductor device and preparation method thereof, electronic installation | |
| CN105575786A (en) | Semiconductor device, preparation method thereof and electronic device with semiconductor device | |
| US20240047520A1 (en) | Semiconductor device with air gap and boron nitride cap and method for preparing the same | |
| CN115172267A (en) | Semiconductor structure and preparation method thereof | |
| KR100688060B1 (en) | Semiconductor device and method for fabrication of the same | |
| CN116072542A (en) | Preparation method of ring grid TFET device | |
| KR20100044557A (en) | Method of manufacturing semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |