CN103809920A - Realizing method of ultra-large capacity solid state disk - Google Patents
Realizing method of ultra-large capacity solid state disk Download PDFInfo
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- CN103809920A CN103809920A CN201410049417.7A CN201410049417A CN103809920A CN 103809920 A CN103809920 A CN 103809920A CN 201410049417 A CN201410049417 A CN 201410049417A CN 103809920 A CN103809920 A CN 103809920A
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Abstract
The invention provides a realizing method of an ultra-large capacity solid state disk. A solid state disk with the capacity of at least TB level can be realized. A storage medium which is large in single capacity and is provided with an SD/MMC interface is used on the disk; each storage channel can contain a plurality of storage media; the storage media in each storage channel share D[0 : 7]/CMD data buses of the SD/MMC interfaces; and SD/MMC interface clock signals of each storage channel are connected into the storage media through high-speed clock switch circuits, the SD/MMC interface clock signals are used as chip selection for controlling, so that the number of the storage media contained in a single storage channel of a disk controller is increased manifold, then the capacity of the disk is increased manifold, and the ultra-large capacity solid state disk is realized.
Description
Technical field
The present invention relates to field of data storage, particularly a kind of implementation method of vast capacity solid state hard disc.
Background technology
In the last few years, along with the solid state hard disc application based on flash media is increasingly extensive, the monomer capacity of this class hard disk was also proposed to larger requirement, particularly needed the application of mass data storage at database server, redundant array of inexpensive disk etc.
Conventional solid-state hard disk adopts the framework of multiple parallel memory channels to realize high-speed data read-write and capacity extension, each memory channel adopts the mode of chip selection signal control to select multiple flash chips, and therefore the max cap. of solid state hard disc is decided by the monomer capacity of memory channel number, sheet selected control number processed and the flash chip of its master controller etc.
Solid state hard disc master controller chip is limited to its framework and package pin number, and the parallel memory channel having and the quantity of sheet selected control system are all limited; Traditional flash chip adopts ONFI/Toggle data-interface agreement in addition, there is the shortcoming that monomer capacity is less than normal, data-interface number of pins is many, although along with the progress of integrated circuit processing technique, monomer capacity also has the trend progressively increasing, such as from 4GB to 8GB and even 16GB etc., but from large capacity applications, the monomer capacity of flash memory is still less than normal; From the volume of solid state hard disc, such as 2.5 inches of solid state hard discs of standard, also limit the configuration quantity of flash chip.
Therefore aspect the Design and implementation of large capacity, especially vast capacity more than TB level, there is very large bottleneck in traditional solid state hard disc.Therefore, for the above-mentioned defect existing in currently available technology, be necessary to study in fact, so that a kind of scheme to be provided, solve the defect existing in prior art.
Summary of the invention
In order to overcome the defect of above-mentioned prior art, the invention provides a kind of implementation method of solid state hard disc of vast capacity, the method adopts the monomer storage medium with SD/MMC interface capacious, more than capacity can reach TB level; Another object of the present invention is to provide a kind of memory channel capacity extension mechanism of solid state hard disc, and this mechanism increases many times of ground of storage medium quantity that the single memory channel of hard disk controller holds, thereby many times of ground of hard-disk capacity are increased.
The problem existing for solving prior art, technical scheme of the present invention is:
1) the solid state hard disc external interface of vast capacity adopts one of high-speed data communication interface forms such as SATA, SAS, eSATA or USB;
2) the solid state hard disc inside of vast capacity is provided with multiple parallel memory channels;
3) each memory channel all adopts SD/MMC data-interface, the storage medium of configuration with SD/MMC interface protocol, and storage medium can be the forms such as eMMC, iNAND, SD card or TF card;
4) each memory channel all adopts capacity extension mechanism, i.e. the storage medium of configurable multiple monomer SD/MMC interface capacious, thereby the capacity of the many times of each memory channels of expansion;
5), by the capacity extension of memory channel, realized the solid state hard disc of vast capacity.
The memory channel capacity extension mechanism of the solid state hard disc proposing according to one of goal of the invention, implementation method is:
The memory channel capacity extension mechanism of solid state hard disc mainly comprises: primary processor, DMA data channel, memory channel processor, SD/MMC sequential interface circuit, high-speed data on-off circuit, multiple storage medium and sheet selected control system etc. with SD/MMC interface.
Primary processor described in this memory channel capacity extension mechanism, issues respectively each memory channel processor by DMA data channel by LBA (Logical Block Addressing) data.
DMA data channel described in this memory channel capacity extension mechanism, provides the data link of primary processor and parallel memory channel.
Memory channel processor described in this memory channel capacity extension mechanism, is responsible for converting obtained LBA (Logical Block Addressing) to physical block address, and is responsible for calculating and distributing the physical block address of the each storage medium in passage.
Memory channel processor described in this memory channel capacity extension mechanism, selects the storage medium of required read-write according to physical block address.
Memory channel processor described in this memory channel capacity extension mechanism, is responsible for controlling the switching of high-speed data on-off circuit.
SD/MMC sequential interface circuit described in this memory channel capacity extension mechanism, be responsible for and passage in the data transmission in SD/MMC communications protocol mode of each storage medium.SD/MMC sequential interface circuit except clock line, other data lines (comprise D[0:7] and CMD) all in parallel, be connected and share with each storage medium in passage.
High-speed data on-off circuit described in this memory channel capacity extension mechanism, belongs to single-pole double-throw (SPDT) or hilted broadsword and the on-off mode such as throws more; Its common port (input end) is connected to the clock cable of SD/MMC sequential interface circuit, it throws end (output terminal) and links respectively the clock signal input terminal of each storage medium in passage, and its control end is connected to the control pin of memory channel processor.
Multiple storage mediums with SD/MMC interface described in this memory channel capacity extension mechanism, can be the forms such as eMMC, iNAND, SD card or TF card, and preferably selecting is monomer eMMC storage chip capacious.
The invention has the beneficial effects as follows:
User uses the present invention, can realize the solid state hard disc of vast capacity (more than TB level).
User uses the present invention, adopts the storage mediums such as monomer eMMC capacious, can be on the hard disk of smaller size smaller (as 2.5 inches), realize the vast capacity of TB level.
User uses the present invention, and the capacity of hard disk can not be subject to the memory channel number of hard disk master controller and the restriction of chip selection signal, can increase on many times of ground.
User uses the present invention, can not change encapsulation, number of pins and the memory channel number of existing hard disk master controller chip, is convenient to integrated and realizes.
User uses the present invention, in realizing the solid state hard disc of vast capacity, still keeps the performance of high-speed read-write speed
Can realize character in specific embodiment disclosed herein and the further understanding of advantage by reference to the remainder of this instructions and accompanying drawing.
Accompanying drawing explanation
Figure 1 shows that the theory diagram of embodiments of the invention 1;
Figure 2 shows that the further details block diagram of a memory channel (11) in embodiment 1;
Figure 3 shows that the theory diagram of embodiments of the invention 2;
Figure 4 shows that the further details of a memory channel (111) in embodiment 2.
Embodiment
In order to make object of the present invention, technical scheme and advantage clearer, below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that specific embodiment described herein, only in order to explain the present invention, is not intended to limit the present invention.
On the contrary, the present invention contain any defined by claim in marrow of the present invention and scope, make substitute, modification, equivalent method and scheme.Further, for the public is had a better understanding to the present invention, in below details of the present invention being described, detailed some specific detail sections of having described.Do not have for a person skilled in the art the description of these detail sections can understand the present invention completely yet.
The solid state hard disc (10) of Fig. 1 in showing according to one embodiment of present invention.Solid state hard disc (10) comprises an outbound data interface (4), a primary processor (5), high-speed serial data sequential interface and control module (2), a DMA passage (3), the parallel memory channel (11-14) of N same architecture.
Fig. 2 is that the further details of an above-mentioned memory channel 11 is described, comprise a data buffer (20), passage 1 processor (21), a SD/MMC sequential interface circuit (23), a high-frequency clock on-off circuit (27), on-off circuit control signal (26), the major parts such as M identical storage medium (41-43), also comprise in addition on-off circuit control signal (26), the clock signal clk 1 (22) of SD/MMC sequential interface circuit, the D[0:7 that storage medium is shared]/CMD data bus (25), the clock signal clk 1-1 (25) that storage medium is alone etc.
The working mechanism of the solid state hard disc (10) of a vast capacity of embodiment is as follows:
Solid state hard disc (10) is connected with external host (1) by external interface (4); Outside main high-speed serial data communication interface and control module (2) are received after the serial information of external host (1), through processing such as input and string conversions, then pass to primary processor (5); Primary processor (5), by desired external host (1) content that reads and writes data (comprising the information such as mathematical logic block address and data length), is averagely allocated to each memory channel (11-14) by DMA passage (3).
The operator scheme of each follow-up memory channel is all identical, take memory channel 1(11) be example, be described below:
The data message of DMA passage (3), through data buffer (20), passes to passage 1 processor (21).
Passage 1 processor (21) is responsible for converting the LBA (Logical Block Addressing) of data to physical block address, and physical block address is corresponding one by one with storage medium; Passage 1 processor (21) can, according to the data physical block address of required read-write, be selected corresponding storage medium (41-43); Passage 1 processor (21) is responsible for each storage medium (41-43) in passage to distribute different physical block address, is responsible for controlling the switching of high-frequency clock on-off circuit (27), is responsible for controlling SD/MMC sequential interface circuit (23).
The D[0:7 of SD/MMC sequential interface circuit (23)]/CMD data bus (25) is directly and each storage medium (41-43) connect and share; The clock signal clk 1 (22) of SD/MMC sequential interface circuit (23) accesses high-frequency clock on-off circuit (27), and after selecting and switching, be connected respectively to again each storage medium (41-43), such as being connected to storage medium 1(41) clock signal clk 1-1 (25).
Each storage medium (41-43) is set to transmission state (transfer) by passage 1 processor (21): in the time receiving clock signal and respective protocol order, this storage medium can enter transmission duty immediately, thereby keeps read or write speed at a high speed; In the time not receiving clock signal, other total interface pins of this storage medium all remain high impedance input state, and other storage mediums are shared D[0:7]/CMD data bus (25).
High-frequency clock on-off circuit (27) can be thrown data switch or other data switch circuit form by single-pole double-throw (SPDT) data switch, hilted broadsword more; Can adopt the mode of switch cascade etc.Preferably selecting is the data switch circuit that adopts single-pole double-throw (SPDT), and cascade is no more than two-stage.
The input end (common port) of high-frequency clock on-off circuit (27) connects the clock signal clk 1 (22) of SD/MMC sequential interface circuit (23); The output terminal (throwing end) of high-frequency clock on-off circuit (27) is connected respectively to the interface clock signal of each storage medium (41-43).The output terminal of high-frequency clock on-off circuit (27) switches, and is controlled by on-off circuit control signal (26).
When passage 1 processor (21) is according to physical block address, determine certain storage medium of required read-write, such as storage medium 1(41) time, passage 1 processor (21) is controlled high-frequency clock on-off circuit (27), clock signal clk 1 (22) is switched to CLK1-1 (25) port, then, passage 1 processor (21) can carry out read-write operation to storage medium 1 (41), completes selection and the reading writing working flow process of storage medium.
The solid state hard disc (10) of a vast capacity of above-described embodiment comprises N memory channel, and each memory channel contains M storage medium, and the population size of hard disk is the single storage medium capacity of M x N x.
Fig. 3 shows a kind of vast capacity solid state hard disc (100) according to another preferred embodiment, is a solid state hard disc with SATA interface that the total volume based on 128GB eMMC storage medium is 2TB.Solid state hard disc (100) comprises an external SATA data-interface (104), one 32 primary processors (105), SATA high-speed serial data sequential interface and control module (102), a DMA passage (103), the parallel memory channel (111-118) of 8 same architecture.
Fig. 4 is that the further details of a memory channel of above-mentioned Fig. 3 (111) is described, comprise a data buffer (120), passage 1 processor (121), a SD/MMC sequential interface circuit (123), the high-speed data switch (127) of a 1P2T, the eMMC(141-142 of 2 128GB) etc. major part, also comprise in addition on-off circuit control signal Switch_Sel(126), the clock signal clk 1 (22) of SD/MMC sequential interface circuit, the D[0:7 that eMMC is shared]/CMD data bus (125), the clock signal clk 1-1 (25) that eMMC is alone, CLK1-2 (128) etc.
The solid state hard disc (100) of a vast capacity of above-described embodiment comprises 8 memory channels, and each memory channel contains 2 128GB eMMC, the population size=8x2x128GB=2048GB=2TB of hard disk; This solid state hard disc (100) only comprises 16 eMMC chips in addition, can in 2.5 inches of hard disk sizes, realize.
The foregoing is only preferred embodiment of the present invention, not in order to limit the present invention, all any modifications of doing within the spirit and principles in the present invention, be equal to and replace and improvement etc., within all should being included in protection scope of the present invention.
Claims (10)
1. an implementation method for vast capacity solid state hard disc, is characterized in that, comprising:
The storage medium of employing with SD/MMC interface;
There are multiple memory channels;
In each memory channel, hold multiple storage mediums with SD/MMC interface;
Each memory channel carrys out sheet by the switching of the clock signal of SD/MMC interface and selects each storage medium in same passage.
2. the implementation method of a kind of vast capacity solid state hard disc described in claim 1, is characterized in that, the described storage medium with SD/MMC interface is any in eMMC storage chip, iNAND storage chip or SD/MMC storage card.
3. the implementation method of vast capacity solid state hard disc according to claim 1, is characterized in that, is also provided with: externally high speed interface, primary processor, DMA data channel and multiple parallel memory channel.
4. the implementation method of vast capacity solid state hard disc according to claim 1, is characterized in that, each memory channel is also provided with: memory channel processor, SD/MMC sequential interface circuit, high-frequency clock on-off circuit.
5. according to the implementation method of a kind of vast capacity solid state hard disc described in claim 1, it is characterized in that, each storage medium in each memory channel is shared the data bus of SD/MMC interface.
6. according to the implementation method of a kind of vast capacity solid state hard disc described in claim 1, it is characterized in that, the SD/MMC interface clock line of each memory channel is received the public input end of high-frequency clock on-off circuit, and the clock line of each storage medium is connected respectively to the output terminal of high-frequency clock on-off circuit.
7. according to the implementation method of a kind of vast capacity solid state hard disc described in claim 3, it is characterized in that, described outbound data interface can be as one of lower interface: SATA, eSATA, USB, IDE, SCSI, SAS, PCI/PCIE.
8. the implementation method of vast capacity solid state hard disc according to claim 4, it is characterized in that, described memory channel processor is responsible for distributing the physical block address of each storage medium in passage, and selects the storage medium of required read-write according to physical block address.
9. the implementation method of vast capacity solid state hard disc according to claim 4, it is characterized in that, described memory channel processor, by controlling high-frequency clock on-off circuit, switches the clock signal of SD/MMC sequential interface circuit and be connected to the clock cable of the storage medium of required read-write.
10. the implementation method of vast capacity solid state hard disc according to claim 4, is characterized in that, more described high-frequency clock on-off circuit can be thrown data switch by single-pole double-throw (SPDT) data switch or hilted broadsword and form; And can adopt the mode of switch cascade.
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Application publication date: 20140521 Assignee: SAGE MICROELECTRONICS CORP. Assignor: Hangzhou Electronic Science and Technology Univ Contract record no.: 2018330000073 Denomination of invention: Realizing method of ultra-large capacity solid state disk Granted publication date: 20170517 License type: Exclusive License Record date: 20180615 |
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