CN103824883A - Groove MOSFET with terminal voltage-withstanding structure and manufacturing method of groove MOSFET - Google Patents
Groove MOSFET with terminal voltage-withstanding structure and manufacturing method of groove MOSFET Download PDFInfo
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66666—Vertical transistors
Abstract
The invention brings forward a groove MOSFET with a terminal voltage-withstanding structure and a manufacturing method of the groove MOSFET. Grooves are formed in a cellular area and a terminal area of the groove MOSFET respectively. The grooves of the terminal area are at least two enclosed annular grooves which surround the cellular area. At least one annular groove, which is close to the cellular area, is an isolation ring which is connected with a zero potential. At least one annular groove, which is close to a scribing channel, is a cutoff ring which is connected with the scribing channel. According to the groove MOSFET with the terminal voltage-withstanding structure, the isolation ring is connected with the zero potential so that electric leakage can be effectively inhibited; and the cutoff ring is connected with the scribing channel so that carriers are not accumulated along the cutoff ring, and thus isolation effect and voltage-withstanding effect of the terminal voltage-withstanding structure are enhanced. According to the manufacturing method, voltage-withstanding and electric leakage problems of the groove MOSFET prepared by the three-layer photo-etching technology are solved, transverse electric leakage of the groove MOSFET is reduced, voltage withstanding of devices is enhanced, technology process is simplified and manufacturing cost is lowered without increasing technology complexity.
Description
Technical field
The invention belongs to essential electronic element field, relate to the preparation of semiconductor device, particularly a kind of terminal pressure-resistance structure and manufacture method thereof of groove MOSFET.
Background technology
Groove MOSFET is the power semiconductor of new generation that microelectric technique and power electronic technology merge, because it has high withstand voltage, large electric current, high input impedance, low on-resistance, the advantage such as switching speed is fast, be widely used in DC-DC transducer, pressurizer, power management module, the fields such as automotive electronics and Electromechanical Control.
Groove MOSFET was just just suggested as far back as 80 years, and in the development of groove MOSFET, the research that reduces product development cost launches around several respects such as the technological processes that obtains higher cellular density, lower conducting resistance, more reliable structure and more simplify.
Aspect raising cellular density reduction product cost, along with the development of process equipment and technology, by selecting more advanced hardware device, expose to the sun, adopt the lower Novel ion implanter of control Implantation Energy to form more shallow source electrode to guarantee channel length such as selecting the shorter mask aligner of wavelength to realize undersized painting, thereby reduce the critical size of technique, dwindle cellular size, integrated more device under equal area.But the problem that raising cellular density faces is: present Low voltage Trench MOSFET cellular size has been reduced to 1um, and the space of continuing decline is more and more less, and the increase that reduces to cause local field strength of size, must bring the reduction in device reliability life-span.
A kind of method reducing costs that also has extensive employing is to simplify processing step.Traditional handicraft is manufactured the method for groove MOSFET, as shown in Figure 2, normally on a block semiconductor substrate 1, form lightly doped N-type epitaxial loayer 2, the layer of silicon dioxide of growing on epitaxial loayer 2 layer, defines this tagma of P type with first block of P trap (P-well) light shield; Then at the silicon dioxide layer of silicon chip surface growth thick layer, define trench region with second groove light shield, on N-epitaxial loayer, form a series of grooves, by thermal oxidation, the gate oxide 7 of growing in groove, depositing polysilicon on gate oxide 7, then returns quarter to polysilicon, forms gate electrode 6; Then in this tagma of P type defining before, carry out the injection of the first p type impurity ion, diffuse to form this tagma 5 of P type; Adopt again the 3rd N+ light shield, in P well area, define territory, N+ source contact area 4, carry out injection and the diffusion of the second N-type foreign ion; At chip surface deposit insulating medium layer 3, adopt the 4th contact hole light shield definition contact hole graph subsequently, photoetching source hole 2 is filled barrier metal in hole, then at surface sputtering top-level metallic; Finally use the 5th metal level light shield, definition gate metal region and source metal region, and adopt dry etching to form gate metal electrode and source metal electrode, on the high substrate surface mixing up of N-type, deposited metal forms drain metal electrode 10.
This processing step comprises 5 layer photoetching mask plates, wherein there is trench mask layer (Poly layer), P trap mask layer (P-well layer), N+ mask layer (N+layer), contact hole mask layer (Contact layer) and metal mask layer (Metal layer), that is to say in device manufacturing processes, need to be through the process of 5 photoetching.Photoetching is for the figure on mask plate is transferred on wafer, and each photoetching need to be through at least 8 processing steps, comprise that gas phase becomes counterdie, spin coating, cures, exposure, baking after exposure is accompanied, develop, post bake dries accompanies and the inspection of developing, and these steps are occupied very large board and time scale in wafer manufacture.
In the groove MOSFET shown in Fig. 1, the surface of the cellular of wafer internal layer is in same current potential, there is not concentrating of electric field, but between edge of wafer place cellular and substrate and scribing road, there is larger electrical potential difference, need the upper concentrated problem of electric field that solves of design, that is the local highfield of reduction knot terminal, to improve surface breakdown voltage tolerance, the domain of the concrete terminal pressure-resistance structure adopting of groove MOSFET that this traditional handicraft is manufactured as shown in Figure 2, Fig. 3 is the sectional structure chart along A-A ' direction in Fig. 2, Fig. 4 is the sectional structure chart along B-B ' direction in Fig. 2, because this groove MOSFET puncture voltage is only 20-30V, the design of the terminal pressure ring at edge does not need very complicated, the field plate that utilizes gate pole metal to do P knot can meet the demands.
For further simplifying the manufacturing process of groove MOSFET, reduction manufacturing cost, can also adopt the technique of the novelties such as self-registered technology to reduce exposure frequency to reduce costs.The people such as the such as Korean Jongdae Kim improvement that the structure to groove MOSFET and technique are carried out in calendar year 2001, although this improvement can greatly reduce the production time of device, and manufactures cost, thereby reduces production costs.But, as shown in Figure 5, this processing step cannot limit P well area and N+ region, cannot continue to use traditional improving withstand voltage and reduce electric leakage at chip periphery formation P type annular pressure ring, need to propose the problem that new Terminal Design solution puncture voltage reduction and electric leakage increase.
Summary of the invention
The present invention is intended at least solve the technical problem existing in prior art, has proposed to special innovation a kind of terminal pressure-resistance structure and manufacture method thereof of groove MOSFET.
In order to realize above-mentioned purpose of the present invention, according to a first aspect of the invention, the invention provides a kind of groove MOSFET with terminal pressure-resistance structure, comprise the epitaxial loayer of substrate and upper formation thereof, the conduction type of described epitaxial loayer is identical with the conduction type of described substrate, in described epitaxial loayer, be formed with successively from top to bottom source region and well region, the conduction type of described well region and the conductivity type opposite of described substrate, the conduction type in described source region is identical with the conduction type of described substrate, the upper surface in described source region and the upper surface of described epitaxial loayer are in same plane, described epitaxial loayer is divided into cellular region and termination environment, described termination environment surrounds described cellular region, in described termination environment, be formed with grid lead district, in described cellular region He in termination environment, be formed with respectively groove, the degree of depth of described groove is greater than the thickness sum of described source region and well region, the groove of described termination environment is at least two ring-shaped grooves around the sealing of described cellular region, and described ring-shaped groove is not connected each other, in described groove, be formed with first medium layer and grid, on described epitaxial loayer, be formed with second medium layer, in described second medium layer, be formed with contact hole, described contact hole comprises gate contact hole, source electrode contact hole and cut-off loop contacts hole, be formed with gate metal layer, source metal and cut-off ring metal level on described second medium layer surface, described gate metal layer is connected with described grid by gate contact hole, described source metal is connected with described source region by source electrode contact hole, and described cut-off ring is connected with described cut-off ring metal level by cut-off loop contacts hole, and be formed with drain metal layer under described substrate.
Terminal pressure-resistance structure of the present invention utilizes multiple splitter box grooves to form isolation terminal, substitute traditional P type and inject knot terminal, in the situation that not increasing the reticle number of plies and technology difficulty, solve withstand voltage low and electric leakage problem, reduced the electric leakage of groove MOSFET, improved the withstand voltage of device.
In order to realize above-mentioned purpose of the present invention, according to a second aspect of the invention, the invention provides a kind of manufacture method of the groove MOSFET with terminal pressure-resistance structure, comprise the steps:
S1: substrate is provided;
S2: form epitaxial loayer on described substrate, the conduction type of described epitaxial loayer is identical with the conduction type of described substrate, in described epitaxial loayer, form successively well region and source region, the conduction type of described well region and the conductivity type opposite of described substrate, the conduction type in described source region is identical with the conduction type of described substrate, and the upper surface in described source region and the upper surface of described epitaxial loayer are in same plane;
S3: divide described epitaxial loayer and form cellular region and termination environment, described termination environment surrounds described cellular region, described termination environment comprises grid lead district, in described cellular region and termination environment, form groove, the degree of depth of described groove is greater than the thickness sum of described source region and well region, the groove of described termination environment is few two ring-shaped grooves around the sealing of described cellular region, described ring-shaped groove is not connected each other, in described groove, form first medium layer and grid, on described epitaxial loayer and described groove, form second medium layer, on described second medium layer, form contact hole, described contact hole comprises gate contact hole, source electrode contact hole and cut-off loop contacts hole, form gate metal layer on described second medium layer surface, source metal and cut-off ring metal level, described gate metal layer is connected with described grid by gate contact hole, described source metal is connected with described source region by source electrode contact hole, described cut-off ring is connected with described cut-off ring metal level by cut-off loop contacts hole respectively with scribing road,
S4: form drain metal layer under described substrate.
The manufacture method of the groove MOSFET with terminal pressure-resistance structure of the present invention is not increasing under the prerequisite of process complexity, solve the withstand voltage and electric leakage problem of groove MOSFET prepared by three layer photoetching techniques, reduce the horizontal electric leakage of groove MOSFET, improve the withstand voltage of device, simplify technical process, reduced manufacturing cost.
In a preferred embodiment of the present invention, along direction from inside to outside, be shading ring near at least one ring-shaped groove of described cellular region, described shading ring is connected with zero potential.
In another kind of preferred embodiment of the present invention, along direction from outside to inside, be cut-off ring near at least one ring-shaped groove in described scribing road, described cut-off ring is connected with scribing road.
In the groove MOSFET with terminal pressure-resistance structure of the present invention, shading ring is connected with zero potential, and the current potential of shading ring, lower than the current potential of its inner side well region, can not form inversion channel in well region, thereby effectively suppresses electric leakage; Cut-off ring is connected with scribing road, and the current potential of cut-off ring is identical with the current potential in scribing road, and charge carrier can, along the accumulation of cut-off ring, not improve isolation effect and the withstand voltage effect of this terminal pressure-resistance structure.
In a preferred embodiment of the present invention, the distance of shading ring and described gate metal layer is the minimum range that photoetching process allows, and the distance in described cut-off ring and described scribing road is the minimum range that photoetching process allows.Chip area has been saved in this design, has improved chip utilance.
In another kind of preferred embodiment of the present invention, between shading ring and cut-off ring, be formed with electric field expanded ring, electric field expanded ring is at least one ring-shaped groove around the sealing not being connected each other of shading ring, the current potential of electric field expanded ring is unsettled.
The present invention is formed with at least one electric field expanded ring between shading ring and cut-off ring, for shading ring and the isolation of cut-off ring and the extension of electric field, has improved the laterally withstand voltage of device.
Additional aspect of the present invention and advantage in the following description part provide, and part will become obviously from the following description, or recognize by practice of the present invention.
Accompanying drawing explanation
Above-mentioned and/or additional aspect of the present invention and advantage accompanying drawing below combination is understood becoming the description of embodiment obviously and easily, wherein:
Fig. 1 is cellular region and the termination environment profile that in prior art, five layer photoetching techniques are prepared groove MOSFET;
The cellular region of groove MOSFET and termination environment domain in prior art shown in Fig. 2 Fig. 1;
Fig. 3 is the sectional structure chart along the direction of A-A ' shown in Fig. 2;
Fig. 4 is the sectional structure chart along the direction of B-B ' shown in Fig. 2;
Fig. 5 is cellular region and the termination environment profile of the groove MOS FE that in prior art prepared by three layer photoetching techniques;
Electric leakage schematic diagram when first ring-shaped groove that Fig. 6 the present invention has a groove MOSFET of terminal pressure-resistance structure suspends;
Fig. 7 is the electric leakage schematic diagram of the outermost ring-shaped groove of the present invention's groove MOSFET with terminal pressure-resistance structure while suspending;
Fig. 8 is cellular region and the termination environment domain schematic diagram of the first preferred embodiment of the present invention's groove MOSFET with terminal pressure-resistance structure;
Fig. 9 is the cross-sectional view of the direction of C-C ' shown in Fig. 8 cellular region and termination environment;
Figure 10 is the cross-sectional view of the direction of D-D ' shown in Fig. 8 cellular region and termination environment;
Figure 11 is cellular region and the termination environment domain schematic diagram of the second preferred embodiment of the present invention's groove MOSFET with terminal pressure-resistance structure;
Figure 12 is the cellular region of the direction of E-E ' shown in Figure 11 and the cross-sectional view of termination environment;
Figure 13 is the cellular region of the direction of F-F ' shown in Figure 11 and the cross-sectional view of termination environment;
Reference numeral:
1 substrate; 2 epitaxial loayers; 3 well regions; 4 source regions; 5 first medium layers; 6 grids;
71 source electrode contact holes; 72 gate contact holes; 73 cut-off loop contacts holes; 8 second medium layers;
91 source metal; 92 gate metal layer; 93 drain metal layer; 94 cut-off ring metal levels;
10 shading rings; 11 cut-off rings; 12 cellular region; 13 termination environments; 14 scribing roads;
15 electric field expanded rings; 16 interdigital structures; 17 grid refer to; 18 grid lead districts.
Embodiment
Describe embodiments of the invention below in detail, the example of described embodiment is shown in the drawings, and wherein same or similar label represents same or similar element or has the element of identical or similar functions from start to finish.Be exemplary below by the embodiment being described with reference to the drawings, only for explaining the present invention, and can not be interpreted as limitation of the present invention.
In description of the invention, it will be appreciated that, term " longitudinally ", " laterally ", " on ", orientation or the position relationship of the indication such as D score, 'fornt', 'back', " left side ", " right side ", " vertically ", " level ", " top ", " end " " interior ", " outward " be based on orientation shown in the drawings or position relationship, only the present invention for convenience of description and simplified characterization, rather than indicate or imply that the device of indication or element must have specific orientation, construct and operation with specific orientation, therefore can not be interpreted as limitation of the present invention.
In description of the invention, unless otherwise prescribed and limit, it should be noted that, term " installation ", " being connected ", " connection " should be interpreted broadly, for example, can be mechanical connection or electrical connection, also can be the connection of two element internals, can be to be directly connected, and also can indirectly be connected by intermediary, for the ordinary skill in the art, can understand as the case may be the concrete meaning of above-mentioned term.
The present invention proposes the groove MOSFET with terminal pressure-resistance structure of a kind of embodiment, as shown in Figure 6 and Figure 7, this groove MOSFET comprises the epitaxial loayer 2 of substrate 1 and upper formation thereof, this substrate 1 is any backing material of preparation MOSFET, can be specifically but be not limited to SOI, silicon, germanium, GaAs, in the present embodiment, preferably adopt silicon.The material of epitaxial loayer 2 can be specifically but be not limited to silicon, germanium, GaAs, and in the present embodiment, the material preferably adopting is silicon, and this substrate 1 is heavy doping, and epitaxial loayer 2 is light dope, and its conduction type is identical with the conduction type of substrate 1.In epitaxial loayer 2, be formed with successively from top to bottom source region 4 and well region 3, the conductivity type opposite of the conduction type of well region 3 and substrate 1, the conduction type in source region 4 is identical with the conduction type of substrate 1, and the upper surface of the upper surface in source region 4 and epitaxial loayer 2 is in same plane.
In the groove of cellular region 12 and termination environment 13, be formed with first medium layer 5 and grid 6, the material of this first medium layer 5 can be any material of preparing gate dielectric layer, can be specifically but be not limited to high K dielectric, silicon dioxide, in the present embodiment, first medium layer 5 adopts silicon dioxide.On first medium layer 5 in groove, be formed with the packed layer of conduction as grid 6, this packed layer is full of groove, and the material of this packed layer can be any material of preparing grid, can be specifically but be not limited to polysilicon or metal, in the present embodiment, packed layer preferably adopts polysilicon.
On epitaxial loayer 2 and groove, be formed with second medium layer 8, this second medium layer 8 is used for preventing that foreign matter from entering affects MOSFET performance on the one hand, having porefilling capability makes silicon chip surface planarization on the one hand in addition, and the material of this second medium layer 8 can be but be not limited to boron-phosphorosilicate glass.On this second medium layer 8, be formed with contact hole, this contact hole comprises gate contact hole 72, source electrode contact hole 71 and cut-off loop contacts hole 73.In the present embodiment, this gate contact hole 72 connects the second medium layer 8 on grid 6, and source electrode contact hole 71 connects the second medium layer 8 on the source region 4 of groove both sides, and cut-off loop contacts hole 73 connects the second medium layer 8 on cut-off ring 11.Be formed with gate metal layer 92, source metal 91 and cut-off ring metal level 94 on second medium layer 8 surface, gate metal layer 92 is connected with grid 6 by gate contact hole 72, source metal 91 is connected with source region 4 by source electrode contact hole 71, cut-off ring 11 is connected with cut-off ring metal level 94 by cut-off loop contacts hole 73, is also formed with drain metal layer 93 under substrate 1.It should be noted that, in the present embodiment, as shown in Fig. 8 or Figure 11, because the gate metal layer 92 in grid lead district 18 is arranged at the periphery of cellular region, gate metal layer 92 need to refer to that 17 are connected with grid 6 by grid, refer to be provided with gate contact hole 72 on the second medium layer 8 on 17 at grid, grid refer to that 17 are connected with gate metal layer 92 by gate contact hole 72.
The isolation of groove MOSFET of the present invention peripheral ring-shaped groove Terminal Design realization electric leakage that adopts at least two group sealings in cellular region and the expansion of electric field, for preventing leak channel, all grooves are the ring-shaped groove of sealing.Along direction from inside to outside, along the direction of mind-set termination environment 13 in cellular region 12, at least one ring-shaped groove near cellular region 12 is shading ring 10, shading ring 10 is connected with zero potential, in a kind of preferred implementation of the present invention, only having the ring-shaped groove nearest with cellular region 12 is shading ring 10, in the present embodiment, shading ring 10 current potentials can not suspend, as shown in Figure 6, if the electric potential floating of shading ring 10, electric field expansion makes the current potential of shading ring 10 higher than the current potential of its inner side well region 4, can cause well region 4 transoids, form leak channel.Along direction from outside to inside, along the direction at 12 centers, 13Xiang cellular region, termination environment, be cut-off ring 11 near at least one ring-shaped groove in scribing road 14, cut-off ring 11 is connected with scribing road 14, in the present embodiment, a ring-shaped groove that only has the most close scribing road 14 is cut-off ring 11, its current potential and scribing road 14 short circuits.The current potential of cut-off ring 11 can not suspend, if the electric potential floating of cut-off ring 11, as shown in Figure 7, the current potential of the cut-off ring 11 suspending is lower than the current potential of the epitaxial loayer 2 in its outside, be conducive to hole along cut-off ring 11 and gather, can cause isolation effect variation, the current potential of cut-off ring 11 is fixed as to the current potential in scribing road 14, make charge carrier can, along 11 accumulation of cut-off ring, not improve isolation effect and the withstand voltage effect of terminal pressure-resistance structure.It should be noted that, in the present invention, zero potential refers to the minimum current potential in each conductive region of groove MOSFET, is not that numerical value is zero current potential.
In the present embodiment, for saving area, improve chip utilance, the position of shading ring 10 is near gate metal layer 92, and the position of cut-off ring 11 is as far as possible near scribing road 14.The scheme that specifically can adopt is that shading ring 10 is the minimum range that photoetching process allows with the distance of gate metal layer 92, and cut-off ring 11 is the minimum range that photoetching process allows with the distance in scribing road 14.It should be noted that; the minimum range that photoetching process of the present invention allows refers to the minimum range in the photoetching process that current preparation MOSFET generally adopts, and along with the progress of technique, this numerical value can constantly dwindle; but it determines that method is consistent, still among protection scope of the present invention.
In the present embodiment, between shading ring 10 and cut-off ring 11, be formed with electric field expanded ring 15, this electric field expanded ring 15 is at least one ring-shaped groove around the sealing not being connected each other of shading ring, the current potential of this electric field expanded ring 15 is unsettled, for shading ring 10 and the isolation of cut-off ring 11 and the extension of electric field.
In a kind of preferred implementation of the present invention, as shown in Fig. 8, Fig. 9 and Figure 10, this peripheral terminal design is made up of the ring-shaped groove of 4 sealings, as shown in figure 10, the ring-shaped groove of innermost layer, it is shading ring 10, source electrode contact hole 71 by interdigital structure 16 and periphery, cellular region is connected to source metal 91, outermost ring-shaped groove ends ring 11, by cut-off loop contacts hole 73 and scribing road 14 equipotentials, in figure, cut-off ring 11, by two cut-off loop contacts holes 73 and scribing road 14 equipotentials, is limited in high potential the position of cut-off ring 11.It should be noted that, shown in figure, 4 ring-shaped grooves are as just example, actual need to guarantee that innermost ring has at least a ring-shaped groove to be connected to the electronegative potential of source metal 91, outer shroud has a ring-shaped groove and scribing road 14 equipotentials at least, and this equipotential ring-shaped groove approaches with scribing road 14 as far as possible, the object that plays restriction high potential and save area.The middle ring-shaped groove suspending can adopt multiple rings, plays isolation and extension electric field action.
In another kind of preferred implementation of the present invention, as shown in Figure 11, Figure 12 and Figure 13, this peripheral terminal design is to be also made up of the ring-shaped groove of 4 sealings, as shown in figure 13, the ring-shaped groove of innermost layer is shading ring 10, shading ring 10 refers to that with grid 17 are connected, and shading ring 10 is connected to gate metal layer 92 by gate contact hole 72.Outermost ring-shaped groove, i.e. cut-off ring 11, by cut-off loop contacts hole 73 and scribing road 14 equipotentials, in figure, cut-off ring 11, by two cut-off loop contacts holes 73 and scribing road 14 equipotentials, is limited in high potential the position of cut-off ring.It should be noted that, shown in figure, 4 ring-shaped grooves are as just example, actual need to guarantee that innermost ring has at least a ring-shaped groove to be connected to the electronegative potential of gate metal layer 92, outer shroud has a ring-shaped groove and scribing road 14 equipotentials at least, and this equipotential ring-shaped groove approaches with scribing road as far as possible, the object that plays restriction high potential and save area.The middle ring-shaped groove suspending can adopt multiple rings, plays isolation and extension electric field action.
The manufacture method that the invention allows for a kind of groove MOSFET with terminal pressure-resistance structure, it comprises the steps:
S1: substrate 1 is provided;
S2: form epitaxial loayer 2 on substrate 1, the conduction type of epitaxial loayer 2 is identical with the conduction type of substrate 1, in epitaxial loayer 2, form successively well region 3 and source region 4, the conductivity type opposite of the conduction type of well region 3 and substrate 1, the conduction type in source region 4 is identical with the conduction type of substrate 1, and the upper surface of the upper surface in source region 4 and epitaxial loayer 2 is in same plane;
S3: divide epitaxial loayer and form cellular region 12 and termination environment 13, this termination environment 13 comprises grid lead district 18, in the present embodiment, cellular region 12 is positioned at central area, grid lead district 18 surrounds cellular region 12, termination environment 13 surrounds grid lead district 18 and cellular region 12, at the interior formation groove in cellular region 12 and termination environment 13, the degree of depth of groove is greater than the thickness sum of source region 3 and well region 4, the groove of termination environment 13 is few two ring-shaped grooves around the sealing of cellular region 12, and groove is not connected each other, along direction from inside to outside, at least one ring-shaped groove near cellular region 12 is shading ring 10, along direction from outside to inside, be cut-off ring 11 near at least one ring-shaped groove in scribing road 14, in groove, form first medium layer 5 and grid 6, on epitaxial loayer 2 and groove, form second medium layer 8, on second medium layer 8, form contact hole, contact hole comprises gate contact hole 72, source electrode contact hole 71 and cut-off loop contacts hole 73, surface at second medium layer 8 forms gate metal layer 92, source metal 91 and cut-off ring metal level 94, gate metal layer 92 is connected with grid 6 by gate contact hole 92, source metal 91 is connected with source region 4 by source electrode contact hole 71, cut-off ring 11 is connected with cut-off ring metal level 94 by cut-off loop contacts hole 73,
S4: form drain metal layer 93 under substrate 1.
In the present embodiment, step S3 specifically comprises the steps:
S41: photoetching on epitaxial loayer 2, etching cellular region 12 and termination environment 13 form groove, the degree of depth of groove is greater than the thickness sum of source region 3 and well region 4, the groove of termination environment 13 is at least two ring-shaped grooves around the sealing of cellular region, along direction from inside to outside, at least one ring-shaped groove near cellular region 12 is shading ring 10, along direction from outside to inside, be cut-off ring 11 near at least one ring-shaped groove in scribing road 14;
S42: the inner surface along groove forms first medium layer 5, forms grid 6 on the first medium layer 5 in groove, and grid 6 is full of described groove;
S43: on epitaxial loayer 2 and groove, form second medium layer 8, photoetching, etching second medium layer 8 forms contact hole, and contact hole comprises gate contact hole 72, source electrode contact hole 71 and cut-off loop contacts hole 73;
S44: at the forming metal layer on surface of second medium layer 8, photoetching, form gate metal layer 92, source metal 91 and cut-off ring metal level 94, gate metal layer 92 is connected with grid 6 by gate contact hole 72, source metal 91 is connected with well region 4 by source electrode contact hole 71, and cut-off ring 11 is connected with cut-off ring metal level 94 by cut-off loop contacts hole 73.
In a kind of preferred implementation of the present invention, prepare groove MOSFET of the present invention and need following steps:
The first step: substrate 1 is provided, and the material of this substrate 1 is any backing material of preparation MOSFET, can be specifically but be not limited to SOI, silicon, germanium, GaAs, and in the present embodiment, preferably adopt silicon, this substrate 1 is heavy doping.
Second step: form epitaxial loayer 2 on substrate 1, the material of this epitaxial loayer 2 can be specifically but be not limited to silicon, germanium, GaAs, in the present embodiment, the material preferably adopting is silicon, this epitaxial loayer 2 is light dope, its conduction type is identical with the conduction type of substrate 1, and the concrete grammar that forms epitaxial loayer 2 can be but be not limited to chemical vapor deposition.
The 3rd step: form successively well region 3 and source region 4 in epitaxial loayer 2, the conductivity type opposite of the conduction type of well region 3 and substrate 1, the conduction type in source region 4 is identical with the conduction type of substrate 1, and the upper surface of the upper surface in source region 3 and epitaxial loayer 2 is in same plane, in the present embodiment, form well region 3 and source region 4 concrete grammar can for but be not limited to the mode of Implantation.
The 4th step: pass through photoetching for the first time on epitaxial loayer 2, etching cellular region 12 and termination environment 13 form groove, specifically utilize mask plate, apply photoresist, by exposure, develop and expose the upper surface of the trench region that needs etching, carry out etching and form groove, concrete lithographic method can be but be not limited to wet etching and dry etching, preferably adopt dry etching, in the present embodiment, the degree of depth of groove is greater than the thickness sum of source region 4 and well region 3, the groove of termination environment 13 is at least two ring-shaped grooves around the sealing of cellular region 12, along direction from inside to outside, at least one ring-shaped groove near cellular region 12 is shading ring 10, along direction from outside to inside, be cut-off ring 11 near at least one ring-shaped groove in scribing road 14, in the other preferred implementation of the present invention, between shading ring 10 and cut-off ring 11, can be formed with electric field expanded ring 15, electric field expanded ring 15 is at least one ring-shaped groove not being connected each other around shading ring 10, the current potential of electric field expanded ring 15 is unsettled.
The 5th step: form first medium layer 5 at grooved inner surface, the material of this first medium layer 5 can be any material of preparing gate dielectric layer, can be specifically but be not limited to silicon dioxide, in the present embodiment, first medium layer 5 adopts silicon dioxide, annealed rear formation gate oxide.On first medium layer 5 in groove, form the packed layer of conduction, this packed layer is full of groove, the material of this packed layer can be any material of preparing grid, can be specifically but be not limited to polysilicon or metal, in the present embodiment, packed layer preferably adopts polysilicon, and the method that forms first medium layer and grid can be but be not limited to chemical vapor deposition.
The 6th step: form second medium layer 8 on epitaxial loayer 2 and groove, carry out photoetching photoetching for the second time, etching second medium layer 8 forms contact hole, contact hole comprises gate contact hole 72, source electrode contact hole 71 and cut-off loop contacts hole 73.This second medium layer 8 is used for preventing that foreign matter from entering affect MOSFET performance on the one hand, and having porefilling capability makes silicon chip surface planarization on the one hand in addition, and these second medium layer 8 materials can be but be not limited to boron-phosphorosilicate glass.In the present embodiment, gate contact hole 72 connects the second medium layer 8 on grid 6, and source electrode contact hole 71 connects the second medium layer 8 on the source region 4 of groove both sides, and cut-off loop contacts hole 73 connects the second medium layer 8 on cut-off ring 11.In the other preferred implementation of the present invention, this gate contact hole 72 connects the second medium layer 8 on grid 6 and is deep into grid 6 inside, source electrode contact hole 71 connects the second medium layer 8 on the source region 4 of groove both sides and is deep into 4 inside, source region, and the second medium layer 8 that cut-off loop contacts hole 73 connects on cut-off ring 11 is also deep into cut-off ring 11 inside.In the present embodiment, form second medium layer 8 method can for but be not limited to chemical vapor deposition, on second medium layer, form contact hole method can for but be not limited to wet etching and dry etching, in the present embodiment, preferably adopt dry etching.
The 7th step: at second medium layer 8 forming metal layer on surface, the method that forms this metal level can be but be not limited to ion beam sputtering or evaporation technology, then carry out photoetching for the third time, this metal level of etching forms gate metal layer 92, source metal 91 and cut-off ring metal level 94, concrete lithographic method can be but be not limited to wet etching and dry etching, in the present embodiment, preferably adopt wet etching.Gate metal layer 92 is connected with grid 6 by gate contact hole 72, and source metal 91 is connected with well region 4 by source electrode contact hole 71, and cut-off ring 11 is connected with cut-off ring metal level 94 by cut-off loop contacts hole 73.In a kind of preferred implementation of the present invention, shading ring 10 is connected with source metal 91 with source electrode contact hole 71 by interdigital structure 16, and this interdigital structure 16 forms according to identical step with shading ring 10 simultaneously.In another preferred implementation of the present invention, shading ring 10 is connected with gate metal layer 92 by gate contact hole 72.
The 8th step: form drain metal layer 93 under substrate 1.
The preparation method of groove MOSFET according to the present invention, in a kind of preferred implementation of the present invention, only describes as an example of the groove MOSFET prepared on N-shaped substrate example, for the device of preparing at the bottom of p-type, according to contrary doping type doping.Concrete steps are: first, make the lightly doped epitaxial loayer 2 of N-shaped on the heavily doped substrate 1 of N-shaped.Then, form successively the lightly doped well region 3 of p-type and the heavily doped source region 4 of N-shaped in the interior method of utilizing Implantation of epitaxial loayer 2, the upper surface of the upper surface in source region 4 and epitaxial loayer 2 is in same plane.Again, on epitaxial loayer 2, utilize mask plate, apply photoresist, expose the upper surface of the groove that needs etching by exposure, development, adopt dry etching method to form groove in cellular region and termination environment etching, the groove of termination environment is four ring-shaped grooves around the sealing of cellular region.Subsequently, utilize CVD (Chemical Vapor Deposition) method deposited oxide layer in groove, after excessive temperature annealing, form the gate oxide that thickness is 800 dusts, this gate oxide is as first medium layer 5.Again, on the first medium layer 5 in groove, depositing polysilicon is as packed layer, and this polysilicon forms the grid 6 of MOSFET.Then, deposit boron-phosphorosilicate glass, as second medium layer 8, defines contact hole region on the surface of second medium layer 8 by photoetching, and etching forms contact hole.Subsequently, adopt sputtering technology depositing metal at the upper surface of second medium layer 8 and contact porose area; By photoetching, and etching forms gate metal layer 92, source metal 91 and cut-off ring metal level 94.Finally, under substrate 1, form drain metal layer 93.
The manufacture method of the groove MOSFET with terminal pressure-resistance structure of the present invention is not increasing under the prerequisite of process complexity, solve the withstand voltage and electric leakage problem of groove MOSFET prepared by three layer photoetching techniques, reduce the horizontal electric leakage of groove MOSFET, improve the withstand voltage of device, simplify technical process, reduced manufacturing cost.
In the description of this specification, the description of reference term " embodiment ", " some embodiment ", " example ", " concrete example " or " some examples " etc. means to be contained at least one embodiment of the present invention or example in conjunction with specific features, structure, material or the feature of this embodiment or example description.In this manual, the schematic statement of above-mentioned term is not necessarily referred to identical embodiment or example.And specific features, structure, material or the feature of description can be with suitable mode combination in any one or more embodiment or example.
Although illustrated and described embodiments of the invention, those having ordinary skill in the art will appreciate that: in the situation that not departing from principle of the present invention and aim, can carry out multiple variation, modification, replacement and modification to these embodiment, scope of the present invention is limited by claim and equivalent thereof.
Claims (14)
1. a groove MOSFET with terminal pressure-resistance structure, is characterized in that, comprising:
The epitaxial loayer of substrate and upper formation thereof, the conduction type of described epitaxial loayer is identical with the conduction type of described substrate, in described epitaxial loayer, be formed with successively from top to bottom source region and well region, the conduction type of described well region and the conductivity type opposite of described substrate, the conduction type in described source region is identical with the conduction type of described substrate, and the upper surface in described source region and the upper surface of described epitaxial loayer are in same plane;
Described epitaxial loayer is divided into cellular region and termination environment, described termination environment surrounds described cellular region, in described termination environment, be formed with grid lead district, in described cellular region He in termination environment, be formed with respectively groove, the degree of depth of described groove is greater than the thickness sum of described source region and well region, the groove of described termination environment is at least two ring-shaped grooves around the sealing of described cellular region, and described ring-shaped groove is not connected each other;
In described groove, be formed with first medium layer and grid;
On described epitaxial loayer, be formed with second medium layer, in described second medium layer, be formed with contact hole, described contact hole comprises gate contact hole, source electrode contact hole and cut-off loop contacts hole;
Be formed with gate metal layer, source metal and cut-off ring metal level on described second medium layer surface, described gate metal layer is connected with described grid by gate contact hole, described source metal is connected with described source region by source electrode contact hole, and described cut-off ring is connected with described cut-off ring metal level by cut-off loop contacts hole; And
Under described substrate, be formed with drain metal layer.
2. the groove MOSFET with terminal pressure-resistance structure as claimed in claim 1, is characterized in that, along direction from inside to outside, is shading ring near at least one ring-shaped groove of described cellular region, and described shading ring is connected with zero potential.
3. the groove MOSFET with terminal pressure-resistance structure as claimed in claim 2, is characterized in that, along direction from outside to inside, is cut-off ring near at least one ring-shaped groove in described scribing road, and described cut-off ring is connected with scribing road.
4. the groove MOSFET with terminal pressure-resistance structure as claimed in claim 3, it is characterized in that, the distance of described shading ring and described gate metal layer is the minimum range that photoetching process allows, and the distance in described cut-off ring and described scribing road is the minimum range that photoetching process allows.
5. the groove MOSFET with terminal pressure-resistance structure as claimed in claim 2, is characterized in that, described shading ring is connected with described source metal with source electrode contact hole by interdigital structure.
6. the groove MOSFET with terminal pressure-resistance structure as claimed in claim 2, is characterized in that, described shading ring is connected with described gate metal layer by gate contact hole.
7. the groove MOSFET with terminal pressure-resistance structure as claimed in claim 3, it is characterized in that, between described shading ring and cut-off ring, be formed with electric field expanded ring, described electric field expanded ring is at least one ring-shaped groove around the sealing not being connected each other of described shading ring, and the current potential of described electric field expanded ring is unsettled.
8. a manufacture method with the groove MOSFET of terminal pressure-resistance structure, is characterized in that, comprises the steps:
S1: substrate is provided;
S2: form epitaxial loayer on described substrate, the conduction type of described epitaxial loayer is identical with the conduction type of described substrate, in described epitaxial loayer, form successively well region and source region, the conduction type of described well region and the conductivity type opposite of described substrate, the conduction type in described source region is identical with the conduction type of described substrate, and the upper surface in described source region and the upper surface of described epitaxial loayer are in same plane;
S3: divide described epitaxial loayer and form cellular region and termination environment, described termination environment surrounds described cellular region, described termination environment comprises grid lead district, in described cellular region and termination environment, form groove, the degree of depth of described groove is greater than the thickness sum of described source region and well region, the groove of described termination environment is few two ring-shaped grooves around the sealing of described cellular region, described ring-shaped groove is not connected each other, in described groove, form first medium layer and grid, on described epitaxial loayer and described groove, form second medium layer, on described second medium layer, form contact hole, described contact hole comprises gate contact hole, source electrode contact hole and cut-off loop contacts hole, form gate metal layer on described second medium layer surface, source metal and cut-off ring metal level, described gate metal layer is connected with described grid by gate contact hole, described source metal is connected with described source region by source electrode contact hole, described cut-off ring is connected with described cut-off ring metal level by cut-off loop contacts hole respectively with scribing road,
S4: form drain metal layer under described substrate.
9. the manufacture method of the groove MOSFET with terminal pressure-resistance structure as claimed in claim 8, is characterized in that, described step S3 comprises the steps:
S31: described in photoetching on described epitaxial loayer, etching, cellular region and termination environment form groove, and the degree of depth of described groove is greater than the thickness sum of described source region and well region, and the groove of described termination environment is at least two ring-shaped grooves around the sealing of described cellular region;
S32: the inner surface along described groove forms first medium layer, forms grid on the first medium layer in described groove, and described grid is full of described groove;
S33: on described epitaxial loayer and described groove, form second medium layer, photoetching, second medium layer forms contact hole described in etching, and described contact hole comprises gate contact hole, source electrode contact hole and cut-off loop contacts hole;
S34: at described second medium layer forming metal layer on surface, photoetching, form gate metal layer, source metal and cut-off ring metal level, described gate metal layer is connected with described grid by gate contact hole, described source metal is connected with described well region by source electrode contact hole, and described cut-off ring is connected with described cut-off ring metal level by cut-off loop contacts hole.
10. the manufacture method as claimed in claim 8 or 9 with the groove MOSFET of terminal pressure-resistance structure, is characterized in that, along direction from inside to outside, is shading ring near at least one ring-shaped groove of described cellular region, and described shading ring is connected with zero potential.
The manufacture method of 11. groove MOSFETs with terminal pressure-resistance structure as claimed in claim 10, is characterized in that, along direction from outside to inside, is cut-off ring near at least one ring-shaped groove in described scribing road, and described cut-off ring is connected with scribing road.
The manufacture method of 12. groove MOSFETs with terminal pressure-resistance structure as claimed in claim 10, is characterized in that, described shading ring is connected with described source metal with source electrode contact hole by interdigital structure.
The manufacture method of 13. groove MOSFETs with terminal pressure-resistance structure as claimed in claim 10, is characterized in that, described shading ring is connected with described gate metal layer by gate contact hole.
The manufacture method of 14. groove MOSFETs with terminal pressure-resistance structure as claimed in claim 11, it is characterized in that, between described shading ring and cut-off ring, be formed with electric field expanded ring, described electric field expanded ring is at least one ring-shaped groove not being connected each other around described shading ring, and the current potential of described electric field expanded ring is unsettled.
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| PCT/CN2013/087270 WO2014075632A1 (en) | 2012-11-19 | 2013-11-15 | Trench mosfet and method for forming the same |
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