CN103853591A - Device used for a virtual machine manager to acquire abnormal instruction and control method - Google Patents
Device used for a virtual machine manager to acquire abnormal instruction and control method Download PDFInfo
- Publication number
- CN103853591A CN103853591A CN201210505800.XA CN201210505800A CN103853591A CN 103853591 A CN103853591 A CN 103853591A CN 201210505800 A CN201210505800 A CN 201210505800A CN 103853591 A CN103853591 A CN 103853591A
- Authority
- CN
- China
- Prior art keywords
- instruction
- stage
- command identification
- cam
- virtual machine
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Advance Control (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Abstract
The invention relates to acquiring of abnormal instructions of virtual machine managers in virtual machine systems, in particular to a device (300) used for a virtual machine manager to acquire abnormal instructions and a control method. The virtual machine manager (220) runs between a physical machine (210) comprising a central processing unit (CPU) (212) and a virtual machine (230), the device comprises a content addressable memory (CAM) (330), a special register (SPR) (350) to which the virtual machine manager can access, and a control logic circuit (310), the control logic circuit (310) has an input end connected with the CPU and an output end connected with the CAM, the input end receives data from an instruction fetching stage and a write-back stage of a CPU instruction assembly line respectively, and the output end enables instructions from the instruction fetching stage of the CPU instruction assembly line to be stored into CAM and triggers the CAM to output the instructions, belonging to the abnormal instructions, stored in the CAM to the SPR.
Description
Technical field
The present invention relates to dummy machine system, more specifically, relate to virtual machine manager obtaining exceptional instructions in dummy machine system.
Background technology
In most of environment, such as server, desktop, even in embedded system, it is more and more general that Intel Virtualization Technology has become.Intel Virtualization Technology provides multiple benefit, comprises IT optimization, resource management flexibly etc.In general, virtual is a kind of wide in range concept, and it is conventionally relevant with the subregion of true (physics) data processing resources; That is, make individual data process resource, for example server, data storage device, operating system or application seem to serve as the effect of multiple logical OR virtual resources.This concept is enough wide to such an extent as to also comprise the gathering of True Data processor resource; That is, make multiple physical resources, for example server or data storage device look like single logical resource.In virtualized environment, between hardware and the operating system of virtual machine, moving virtual machine manager (Hypervisor) or monitor of virtual machine (VMM, Virtual Machine Monitor).Virtual machine manager plays an important role at the aspect such as execution and share host hardware resource (host hardwareresources) of managing virtual machines software.A function of virtual machine manager, in the time that hardware sends abnormal interruption, the abnormal reason of interrupting of identification, and process accordingly, for example simulation (emulate) causes abnormal instruction that interrupt, that carry out self virtualizing machine, i.e. exceptional instructions (faultinginstruction).For this reason, first virtual machine manager needs to navigate to exceptional instructions.In prior art, virtual machine manager is that this mode efficiency is not high by the address mapped location exceptional instructions of the address space different.
Summary of the invention
For the situation of prior art, an object of the present invention is to improve the mode of virtual machine manager acquisition exceptional instructions.
On the one hand, a kind of device (300) that obtains exceptional instructions for virtual machine manager is provided, wherein, described virtual machine manager (220) moves between the physical machine that comprises central processor CPU (212) (210) and virtual machine (230), and described device comprises: Content Addressable Memory CAM (330); The addressable special register SPR of virtual machine manager (350); And control logic circuit (310), there is the connected input end of CPU and the output terminal being connected with CAM, input end receives the fetching stage and the data that write back the stage from cpu instruction streamline respectively, output terminal makes to be stored in CAM from the instruction in the fetching stage of cpu instruction streamline, and trigger CAM by wherein storage the instruction that belongs to exceptional instructions output to SPR.
On the other hand, a kind of control method of obtaining exceptional instructions for virtual machine manager is provided, wherein, described virtual machine manager (220) moves between the physical machine that comprises central processor CPU (212) (210) and virtual machine (230), and described control method comprises: make to be stored in Content Addressable Memory from the instruction in fetching stage of cpu instruction streamline; According to the result that the stage that writes back of cpu instruction streamline produces, trigger CAM the instruction that belongs to exceptional instructions of wherein storage is outputed to the addressable special register of virtual machine manager.
Again on the one hand, provide the control device that obtains accordingly exceptional instructions with the above-mentioned control method of obtaining exceptional instructions for virtual machine manager for virtual machine manager.
Brief description of the drawings
In conjunction with the drawings disclosure illustrative embodiments is described in more detail, above-mentioned and other object of the present disclosure, Characteristics and advantages will become more obvious, wherein, in disclosure illustrative embodiments, identical reference number represents same parts conventionally.
Fig. 1 shows the block diagram that is suitable for the exemplary computer system for realizing embodiment of the present invention 100;
Fig. 2 A is the schematic diagram that represents to be suitable for the virtualized environment of realizing the embodiment of the present invention;
Fig. 2 B schematically shows the instruction pipelining of processor;
Fig. 3 A schematically shows according to the block diagram of the device of one embodiment of the invention;
Fig. 3 B further illustrates according to the block diagram of the device of one embodiment of the invention;
Fig. 3 C schematically shows according to the block diagram of the partial structurtes of the device of one embodiment of the invention;
Fig. 3 D-3F schematically shows according to the operation of the device of the embodiment of the present invention;
Fig. 4 A-4C schematically shows according to the process flow diagram of the control method of the embodiment of the present invention; And
Fig. 5 A-5C schematically shows according to the block diagram of the control device of the embodiment of the present invention.
Embodiment
Preferred implementation of the present disclosure is described below with reference to accompanying drawings in more detail.Although shown preferred implementation of the present disclosure in accompanying drawing, but should be appreciated that, can realize the disclosure and the embodiment that should do not set forth limits here with various forms.On the contrary, it is in order to make the disclosure more thorough and complete that these embodiments are provided, and can be by the those skilled in the art that conveys to complete the scope of the present disclosure.
Fig. 1 shows the block diagram that is suitable for the exemplary computer system for realizing embodiment of the present invention 100.As shown in Figure 1, computer system 100 can comprise: CPU (CPU (central processing unit)) 101, RAM (random access memory) 102, ROM (ROM (read-only memory)) 103, system bus 104, hard disk controller 105, keyboard controller 106, serial interface controller 107, parallel interface controller 108, display controller 109, hard disk 110, keyboard 111, serial external unit 112, parallel external unit 113 and display 114.In these equipment, there are CPU101, RAM 102, ROM 103, hard disk controller 105, keyboard controller 106, serialization controller 107, parallel controller 108 and a display controller 109 with system bus 104 is coupled.Hard disk 110 is coupled with hard disk controller 105, keyboard 111 is coupled with keyboard controller 106, serial external unit 112 is coupled with serial interface controller 107, and parallel external unit 113 is coupled with parallel interface controller 108, and display 114 is coupled with display controller 109.Should be appreciated that the structured flowchart described in Fig. 1 is only used to the object of example, instead of limitation of the scope of the invention.In some cases, can increase as the case may be or reduce some equipment.
Person of ordinary skill in the field knows, the present invention can be implemented as system, method or computer program.Therefore, the disclosure can specific implementation be following form, that is: can be completely hardware, also can be software (comprising firmware, resident software, microcode etc.) completely, can also be the form of hardware and software combination, be commonly referred to as " circuit ", " module " or " system " herein.In addition, in certain embodiments, the present invention can also be embodied as the form of the computer program in one or more computer-readable mediums, comprises computer-readable program code in this computer-readable medium.
Can adopt the combination in any of one or more computer-readable media.Computer-readable medium can be computer-readable signal media or computer-readable recording medium.Computer-readable recording medium for example may be-but not limited to-electricity, magnetic, optical, electrical magnetic, infrared ray or semi-conductive system, device or device, or any above combination.The example more specifically (non exhaustive list) of computer-readable recording medium comprises: have the electrical connection, portable computer diskette, hard disk, random access memory (RAM), ROM (read-only memory) (ROM), erasable type programmable read only memory (EPROM or flash memory), optical fiber, Portable, compact disk ROM (read-only memory) (CD-ROM), light storage device, magnetic memory device of one or more wires or the combination of above-mentioned any appropriate.In presents, computer-readable recording medium can be any comprising or stored program tangible medium, and this program can be used or be combined with it by instruction execution system, device or device.
Computer-readable signal media can be included in the data-signal of propagating in base band or as a carrier wave part, has wherein carried computer-readable program code.The combination of electromagnetic signal that the data-signal of this propagation can adopt various ways, comprises---but being not limited to---, light signal or above-mentioned any appropriate.Computer-readable signal media can also be any computer-readable medium beyond computer-readable recording medium, and this computer-readable medium can send, propagates or transmit the program for being used or be combined with it by instruction execution system, device or device.
The program code comprising on computer-readable medium can be with any suitable medium transmission, comprises that---but being not limited to---is wireless, electric wire, optical cable, RF etc., or the combination of above-mentioned any appropriate.
Can combine to write the computer program code for carrying out the present invention's operation with one or more programming languages or its, described programming language comprises object-oriented programming language-such as Java, Smalltalk, C++, also comprise conventional process type programming language-such as " C " language or similar programming language.Program code can fully be carried out, partly on subscriber computer, carries out, carry out or on remote computer or server, carry out completely as an independently software package execution, part part on subscriber computer on remote computer on subscriber computer.In the situation that relates to remote computer, remote computer can be by the network of any kind---comprise LAN (Local Area Network) (LAN) or wide area network (WAN)-be connected to subscriber computer, or, can be connected to outer computer (for example utilizing ISP to pass through Internet connection).
Process flow diagram and/or block diagram below with reference to method, device (system) and the computer program of the embodiment of the present invention are described the present invention.Should be appreciated that the combination of each square frame in each square frame of process flow diagram and/or block diagram and process flow diagram and/or block diagram, can be realized by computer program instructions.These computer program instructions can offer the processor of multi-purpose computer, special purpose computer or other programmable data treating apparatus, thereby produce a kind of machine, these computer program instructions are carried out by computing machine or other programmable data treating apparatus, have produced the device of the function/operation specifying in the square frame in realization flow figure and/or block diagram.
Also these computer program instructions can be stored in and can make in computing machine or the computer-readable medium of other programmable data treating apparatus with ad hoc fashion work, like this, the instruction being stored in computer-readable medium just produces a manufacture (manufacture) that comprises the command device (Instruction means) of the function/operation specifying in the square frame in realization flow figure and/or block diagram.
Also computer program instructions can be loaded on computing machine, other programmable data treating apparatus or miscellaneous equipment, make to carry out sequence of operations step on computing machine, other programmable data treating apparatus or miscellaneous equipment, to produce computer implemented process, thus the process of function/operation that the instruction that makes to carry out on computing machine or other programmable device specifies during the square frame in realization flow figure and/or block diagram can be provided.
Process flow diagram in accompanying drawing and block diagram have shown according to architectural framework in the cards, function and the operation of the system of multiple embodiment of the present invention, method and computer program product.In this, the each square frame in process flow diagram or block diagram can represent a part for module, program segment or a code, and a part for described module, program segment or code comprises one or more for realizing the executable instruction of logic function of regulation.Also it should be noted that what the function marking in square frame also can be marked to be different from accompanying drawing occurs in sequence in some realization as an alternative.For example, in fact two continuous square frames can be carried out substantially concurrently, and they also can be carried out by contrary order sometimes, and this determines according to related function.Also be noted that, the combination of the square frame in each square frame and block diagram and/or process flow diagram in block diagram and/or process flow diagram, can realize by the special hardware based system of the function putting rules into practice or operation, or can realize with the combination of specialized hardware and computer instruction.
Computer system 100 shown in Fig. 1, can be used for realizing the processor in the virtualized environment the present invention relates to.Processing of obtaining exceptional instructions for virtual machine of the present invention also can be carried out in the computer system 100 shown in Fig. 1.
General plotting of the present invention is to realize virtual machine manager in the virtualized environment quick obtaining to exceptional instructions by the hardware of suitable setting.
With reference to the accompanying drawings, various embodiment of the present invention is described.
First referring to Fig. 2 A, this figure schematically shows the block diagram that is suitable for the virtualized environment of realizing therein the embodiment of the present invention.
Virtualized environment 200 as shown in Figure 2 A, comprises hardware (hereinafter referred to as " physical machine ") 210, virtual machine manager (Hypervisor) 220 and virtual machine (VM) 230.Physical machine 210 comprises at least one processor (CPU) 212, the PowerPC of the RISC framework of for example I BM company, in addition, can also comprise other hardware resource, for example computer-readable storage medium (do not give and illustrating), input/output interface (do not give and illustrating) etc.Virtualized environment can provide the virtual machine of the hardware resource of multiple shared physical machine 210, each virtual machine 230 comprise its oneself operating system with and oneself application.
In the abnormal reason of interrupting of identification and before processing accordingly, virtual machine manager need to obtain exceptional instructions.The process that obtains exceptional instructions is conventionally as follows:
-virtual machine state the data structure safeguarded from virtual machine manager, obtain the virtual address GVA (Guest Virtual Address) of virtual machine exceptional instructions, for example program counter value and Process identifier;
-according to the page table of virtual machine (page table), be virtual machine physical address GPA (Guest Physical Address) by the virtual address translation of virtual machine;
-be main frame virtual address (Host Virtual Address) according to the memory management mechanism of virtual machine manager by virtual machine physical address translations;
-providing interface function with operating system nucleus or Virtual Machine Manager, for example the copy_from_user () function under Linux, extracts exceptional instructions at main frame virtual address place.
In said process, extracting when exceptional instructions from main frame virtual address, also may trigger other extremely, for example new page fault or data TLB disappearance are abnormal.
Therefore, virtual machine manager obtains the process of exceptional instructions, need repeatedly address translation, need between the different address space of virtual machine, physical machine, virtual machine manager, switch, extremely interrupt frequently, not only bring burden to virtual machine manager, and can cause serious delay.
Inventor imagination, virtual machine manager is for fear of above-mentioned complex operations, the instruction that can directly utilize CPU 212 to obtain in the fetching stage of instruction pipelining.
Fig. 2 B schematically shows the instruction pipelining of processor.
Person of ordinary skill in the field knows, high performance processor nearly all adopts instruction pipelining.Shown in Fig. 2 B, be typical RI SC instruction pipelining.There is shown 5 instruction pipelinings, each instruction pipelining is divided into double teacher (stage): fetching (IF), decoding (ID), carry out (EX), memory access (MEM) and write back (WB).
Stage 1: in the fetching stage, according to programmable counter (Program Counter) value and Process identifier PID (Proces sIdentifier), obtain the instruction that next will be carried out.
Stage 2: in the decoding stage, the Instruction decoding of obtaining in the fetching stage is become to the executable code of machine.
Stage 3: the execute phase, carry out the instruction code after decoding.
Stage 4: memory access stage, according to the execution of instruction code is carried out to corresponding read-write operation to storer.
Stage 5: write back the stage, produce the result of the execution to instruction.For exceptional instructions, write back in the result in stage and comprise and indicate the mark of exceptional instructions and the context of exceptional instructions, for example, the stage that writes back produces and represents that present instruction belongs to the look-at-me of exceptional instructions, in machine status register(MSR) corresponding to the stage that writes back, retaining program counter value corresponding to this instruction and Process identifier.
In existing instruction pipelining design, the instruction that the fetching stage is obtained is just dropped after the decoding stage.Even if virtual machine manager 220 has obtained occurring the notice of exceptional instructions in the stage of writing back, also cannot from instruction pipelining, directly obtain this exceptional instructions.
Inventor's imagination, in the case of the instruction pipelining architecture that does not change CPU, can, by the hardware suitably configuring, preserve the instruction originally being abandoned by instruction pipelining, and identify the exceptional instructions in preserved instruction in the stage of writing back, directly read for Virtual Machine Manager machine.
Referring to Fig. 3 A, the figure shows and obtain the block diagram of the device 300 of exceptional instructions according to one embodiment of the invention for virtual machine manager.
As shown in the figure, described virtual machine manager 220 moves between the physical machine 210 that comprises central processing unit (CPU) 212 and virtual machine 230.Device 300 comprises a Content Addressable Memory (CAM, content addressable memory) 330, the addressable special register of virtual machine manager 220 (SPR) 350 and a control logic circuit 310..Control logic circuit has the connected input end of CPU and the output terminal being connected with CAM, input end receives the fetching stage and the data that write back the stage from cpu instruction streamline respectively, output terminal makes to be stored in CAM from the instruction in the fetching stage of cpu instruction streamline, and trigger CAM by wherein storage the instruction that belongs to exceptional instructions output to SPR.
Person of ordinary skill in the field knows, Content Addressable Memory CAM (Content-Addressable Memory) is a kind of special storage array that carries out addressing with content.The mode of operation of CAM, comprises write mode and basic manipulation mode.Under write mode, can be in CAM data writing.Under basic manipulation mode, CAM reads input data and automatically compares with the data that are stored in CAM inputting data (also claiming " input index value ") simultaneously, differentiate the data of storing in these input data and CAM and whether match, and output and the data corresponding informance mating.
As mentioned before, the fetching stage of cpu instruction streamline, obtain the instruction that next will be carried out, obtained instruction will be sent to the decoding stage.Control logic circuit 310 can obtain the instruction that the finger stage obtains, and obtains the uniqueness command identification of this instruction simultaneously.Further, control logic circuit 310 can make CAM enter write mode, and obtained instruction and command identification are stored in CAM explicitly.
In the stage that writes back of cpu instruction streamline, control logic circuit 310 also can obtain the mark of present instruction, and control logic circuit 310 also can, according to writing back the result that the stage produces, judge that present instruction is exceptional instructions.If exceptional instructions can control CAM 330 and enter basic manipulation mode, and input index value using the mark of present instruction as CAM.CAM compares the mark of present instruction and the command identification being stored in CAM automatically, and by the instruction corresponding with the marking matched command identification of present instruction, i.e. exceptional instructions, outputs to SPR 350.
The above-mentioned functions of control logic circuit, can realize by the combination of hardware logic elements completely.
Because SPR 350 is that virtual machine manager 220 is addressable, in the time writing back stage instruction and occur exceptional instructions, make virtual machine manager 220 directly read SPR, just can directly obtain exceptional instructions.On basis of the present invention, person of ordinary skill in the field is not difficult, by the method for programming, existing virtual machine manager is carried out to suitable setting, makes virtual machine manager directly obtain exceptional instructions from SPR.
Fig. 3 B is at length exemplified with according to a kind of specific implementation of the control logic circuit of one embodiment of the invention 310.The control logic circuit 310 of Fig. 3 B, as shown in dotted line frame, comprises: instruction acquisition module 311, the first command identification acquisition module 312, instruction cache module 313.The function of above-mentioned each module is as described below.
As mentioned before, the fetching stage of cpu instruction streamline, obtain the instruction that next will be carried out, obtained instruction is sent to the decoding stage.In application, can, in the case of not changing the logic of instruction pipelining, according to the data stream of instruction pipelining, instruction acquisition module 311 be arranged to such an extent that can intercept and capture the obtained instruction of fetching stage.
The first command identification acquisition module 312 is configured to such an extent that obtain the first command identification for the fetching Phase I F from cpu instruction streamline.
Command identification for uniqueness identify an instruction.In different environment, can be different for the form of the command identification that identifies instruction.In existing instruction pipelining, the combination that conventionally adopts program counter value PC and Process identifier PID as uniqueness identify the command identification of an instruction.In machine status register(MSR) corresponding to the different phase of instruction pipelining, retaining the context of current generation, comprise PC and the PID of instruction corresponding to current generation.
According to one embodiment of the invention, the first command identification acquisition module 312 further can be configured for obtaining program counter value PC and Process identifier PID from machine status register(MSR) corresponding to IF stage, and for example, by the combination of the PC obtaining from machine status register(MSR) corresponding to IF stage and PID (combination of " PC+PID " or " PID+PC " form), as the first command identification.
Person of ordinary skill in the field knows, in concrete application, the which couple between the output terminal of machine status register(MSR) corresponding to the input end by the first command identification acquisition module 312 and IF stage, just can obtain PC and PID.Concrete circuit design, needn't elaborate any further at this.
Referring to Fig. 3 C, this figure schematically shows according to the operation of the device of one embodiment of the invention.The schematically illustrated instruction pipelining that comprises IF, ID, EX, MEM and WB double teacher of Fig. 3 C, and according to control logic circuit 310 of the present invention, CAM 330 and SPR 350.As shown in the figure, CAM330 can hold n CAM item (also claiming " CAM data item " or " data item ") entry_1, entry_2, entry_n, wherein, the number of CAM item is no less than the number of the instruction on instruction pipelining, each CAM item IncFlds 331,333 and 335.The length in territory 331 is for example 64 (bit), for a storage program Counter Value PC; The length in territory 333 is for example 14, for a storage process identifier PI D; The length in territory 335 is for example 32, for storing an instruction INSTR.Relative position between territory 331,333 and 335 can preset, and is not limited to shown in figure; In addition, the coding form of INSTR also can be depending on concrete application, and the present invention does not also limit this.
What the arrow 321,322,323,324,325 and 326 in figure represented is the operation of control logic circuit 310.Arrow 321 represents, control logic circuit 310 obtains an instruction INSTR from the fetching Phase I F of cpu instruction streamline, and this operation can be carried out by instruction acquisition module 311.Arrow 322 represents, in obtaining instruction INSTR, control logic circuit 310 is also obtained the first command identification from the fetching Phase I F of cpu instruction streamline, and this operation can be carried out by the first command identification acquisition module 312.The first command identification acquisition module 312 can obtain program counter value PC and Process identifier PID from machine status register(MSR) corresponding to IF, and using the combination of PC and PID as the first command identification.
Return to Fig. 3 B, according to one embodiment of the invention, control logic circuit 310 further comprises the second command identification acquisition module 314, abnormality detection module 315 and instruction output module 316.The second command identification acquisition module 314 is configured to such an extent that obtain the second command identification for the stage that writes back from instruction pipelining.
As described above, according to one embodiment of the invention, the first command identification acquisition module 312 can be further configured for obtaining program counter value PC and Process identifier PID from machine status register(MSR) corresponding to IF stage, and by the program counter value of obtaining from machine status register(MSR) corresponding to IF stage and the combination of Process identifier, as the first command identification.
Correspondingly, according to one embodiment of the invention, the second command identification acquisition module 314 further can be configured for obtaining program counter value PC and Process identifier PID from machine status register(MSR) corresponding to WB stage, and for example, by the combination of the program counter value PC obtaining from machine status register(MSR) corresponding to WB stage and Process identifier PID (combination of " PC+PID " or " PID+PC " form), as the second command identification.
With similar about described in the first command identification acquisition module 312 above, in concrete application, the which couple of the output terminal by the input end of the second command identification acquisition module 314 machine status register(MSR) corresponding with the WB stage, just can obtain PC and PID.
Point out in passing, the first command identification acquisition module 312 is identical with the function of the second command identification acquisition module 314, is purposes difference, is respectively used to PC and the PID of the related instruction of different phase of obtaining instruction pipelining.In specific implementation, can substitute these two modules by single module.Specifically without repeating.
Turn 3C with the aid of pictures.Arrow 324 in Fig. 3 C, represents that control logic circuit 310 obtains the second command identification from the WB stage of instruction pipelining, and this operation can be carried out by the second command identification acquisition module 314.The second command identification acquisition module 314 can obtain program counter value PC and Process identifier PID from machine status register(MSR) corresponding to WB stage, and using the combination of PC and PID as the second command identification.
Return to Fig. 3 B, further describe abnormality detection module 315.
This function is as shown in the arrow 325 in Fig. 3 C.This arrow represents that control logic circuit 310 detects the abnormal look-at-me Exception_Indicator that the stage that the writes back WB of instruction pipelining sends, and this operation can be carried out by abnormality detection module 315.Abnormal look-at-me Exception_Indicator represents whether present instruction is exceptional instructions, for example,, if Exception_Indicator=" 1 " represents that present instruction is exceptional instructions, if Exception_Indicator=" 0 ", represents that present instruction is not exceptional instructions.
Turn 3B with the aid of pictures, instruction output module 316 is configured to such an extent that in response to abnormal look-at-me instruction, exceptional instructions has occurred, and makes the instruction being associated with the second command identification in Content Addressable Memory CAM output to special register 350.
Referring to Fig. 3 C, the operation of control logic circuit 310 after intercepting and capturing write back the result in stage is as shown in arrow 326.The program counter value of supposing present instruction is pc_1, the Process identifier of present instruction is pid_1, Exception_Indicator=" 1 ", the combination " pc_1+pid_1 " of control logic circuit 310 use program counter value pc_1 and Process identifier pid_1 is as index value, navigate to the data item that comprises same program Counter Value pc_1 and Process identifier pid_1 in Content Addressable Memory 330-be the data item entry_1 shown in Fig. 3 C, and the instruction instr_1 in this data item is outputed to special register 350.
In specific implementation, can, according to concrete conditions such as the numbers of instruction pipelining, the number of the open ended data item of CAM330 (entry) or CAM item be set, make the each unsettled instruction in instruction pipelining can have a corresponding data item.In addition, in specific design, can make the storage space of CAM item corresponding to each instruction, after this instruction is finished, be released, for the instruction of entry instruction streamline subsequently.
According to one embodiment of the invention, control logic circuit 310 also comprises a CAM administration module (do not give and illustrating), and it is configured for having discharged the not storage space of the Content Addressable Memory data item at the instruction place on instruction pipelining.
Referring to Fig. 3 C, can be at the data item of Content Addressable Memory 330 (entry_1, entry_2 ... the mark domain 332 of one 1 (bit) is set entry_n), whether be effectively used to indicate place data item, or whether place storage space is occupied.For example, when the value of mark domain 332 is " 1 ", represent that place data item is effective, control logic circuit 310 can not write new data item in the position of this data item; When the value of mark domain is " 0 ", represent that place data item is invalid, the storage space of this data item is released, and control logic circuit 310 can write new data item in the position of this data item.
According to one embodiment of the invention, instruction cache module 313 is configured to obtain the instruction of position storage instruction acquisition module 311 of the data item that only value of the mark domain in Content Addressable Memory is 0 and the first command identification that the first command identification acquisition module 312 obtains, CAM administration module be configured when instruction cache module 313 writes instruction and the first command identification, the zone bit of this data item is set to effectively.For example, as shown in Figure 3 C, suppose that the value of the mark domain of entry_1 is 0 at the beginning, instruction cache module 313 is data writing pc_1, pid_1 and instr_1 in entry_1, and CAM administration module arranges 1 by the value of mark domain simultaneously.
According to one embodiment of the invention, 316 of instruction output modules operate for the active data item in CAM 330, and this can be by realizing " 1 "+PC+PID as the input index value of CAM.
When the instruction that makes to be associated with the second command identification in CAM when instruction output module 316 outputs to SPR, it is invalid that CAM administration module is set to the mark domain 332 of the place data item of this instruction in CAM simultaneously.
For example, as shown in Fig. 3 C and Fig. 3 D, instruction output module 316 makes the instruction instr_1 in the data item entry_1 in the CAM330 shown in Fig. 3 C output to special register 350, meanwhile, it is invalid that CAM administration module is set to the mark domain of this data item 332, as shown in Figure 3 D, result, the value of the mark domain of data item entry_1 becomes as " 0 ".
Even if abnormality detection module 315 can't detect the generation of exceptional instructions, instruction output module 316 does not make CAM 330 to SPR 350 output orders, and it is invalid that CAM administration module is also set to the mark domain 332 of the CAM data item at the second command identification place.For example, as shown in Fig. 3 E, certain valid data item entry_1 stores the first command identification " pc_2+pid_2 " and instruction instr_2.If the second command identification acquisition module to have obtained the second command identification identical with the first command identification, be also " pc_2+pid_2 " simultaneously, abnormality detection module 315 can't detect the generation of exceptional instructions.In this case, it is invalid that CAM administration module is just set to the mark domain 332 of the second command identification place data item, result is as shown in Fig. 3 F, instruction instr_2 does not output to special register 350, but the value of the mark domain 332 of CAM administration module data item entry_1 is set to 0, represents that the storage space of this data item is released.
Use CAM 330, just the instruction of buffer memory wherein can be outputed to special register 350 a clock period.In CAM data item, arrange and service marking position 332, the CAM data item that the instruction on instruction pipelining does not take can be discharged, can reduce as far as possible thus the aggregate demand to CAM storage space.
The various embodiments of the device that obtains exceptional instructions for virtual machine manager of the present invention have more than been described.According to same inventive concept, the present invention is also provided for virtual machine manager and obtains control method and the corresponding control device of exceptional instructions.
Referring to Fig. 4 A, this figure schematically shows according to the high level flow chart of the control method of one embodiment of the invention.Control method 400 as shown in the figure, obtain exceptional instructions for virtual machine manager, wherein, described virtual machine manager 220 moves between the physical machine 210 that comprises central processor CPU 212 and virtual machine 230, and described control method comprises step S410 and S420:
Make to be stored in Content Addressable Memory CAM (S410) from the instruction in fetching stage of cpu instruction streamline;
According to the result that the stage that writes back of cpu instruction streamline produces, trigger CAM the instruction that belongs to exceptional instructions of wherein storage is outputed to the addressable special register SPR of virtual machine manager (S420).
Referring to Fig. 4 B, according to one embodiment of the invention, above-mentioned step S410 comprises step S412-S414:
Obtain instruction (S412) from the fetching stage of cpu instruction streamline;
Obtain the first command identification (S414) from the fetching stage of cpu instruction streamline;
Obtained instruction and the first command identification are stored in to (S416) in CAM explicitly.
Referring to Fig. 4 C, according to one embodiment of the invention, above-mentioned step S420 comprises step S422-S426:
Obtain the second command identification (S422) from the stage that writes back of instruction pipelining;
The abnormal look-at-me (S424) that the stage that writes back of detection instruction pipelining sends; And
There is exceptional instructions in response to abnormal look-at-me instruction, made the instruction being associated with the second command identification in CAM output to SPR (S426).Outputing to the instruction in SPR, is exactly in fact to cause abnormal exceptional instructions.
According to one embodiment of the invention, above-mentioned steps S412 comprises: obtain program counter value PC and Process identifier PID from machine status register(MSR) corresponding to fetching stage, and using the combination of the PC obtaining from machine status register(MSR) corresponding to fetching stage and PID as the first command identification.
According to one embodiment of the invention, above-mentioned steps S422 comprises: obtain program counter value PC and Process identifier PID from machine status register(MSR) corresponding to WB stage, and using the combination of the PC obtaining from machine status register(MSR) corresponding to WB stage and PID as the second command identification.
According to one embodiment of the invention, described control method 400 further comprises: discharged the not storage space of the Content Addressable Memory data item at the instruction place on instruction pipelining.
Referring to Fig. 5 A, this figure schematically shows the block diagram according to one embodiment of the invention.Control device 500 as shown in the figure, obtains exceptional instructions for virtual machine manager, and wherein, described virtual machine manager 220 moves between the physical machine 210 that comprises central processor CPU 212 and virtual machine 230, and described control device comprises:
For making to be stored in from the instruction in fetching stage of cpu instruction streamline the device 510 of Content Addressable Memory CAM; For the result triggering CAM producing according to the stage that writes back of cpu instruction streamline, the instruction that belongs to exceptional instructions of wherein storage is outputed to the device 520 of the addressable special register SPR of virtual machine manager.
Referring to Fig. 5 B, according to one embodiment of the invention, above-mentioned device 510 comprises: the device 512 that obtains instruction for the fetching stage from cpu instruction streamline; For obtain the device 514 of the first command identification from the fetching stage of cpu instruction streamline; And for obtained instruction and the first command identification being stored in explicitly to the device 516 of CAM.
Referring to Fig. 5 C, according to one embodiment of the invention, above-mentioned device 520 comprises: for obtain the device 522 of the second command identification from the stage that writes back of instruction pipelining; The device 524 of the abnormal look-at-me of sending for detection of the stage that writes back of instruction pipelining; And in response to abnormal look-at-me instruction, exceptional instructions having occurred, make the instruction being associated with the second command identification in CAM output to the device 526 of SPR.
According to one embodiment of the invention, said apparatus 512 is further configured for obtaining program counter value PC and Process identifier PID from machine status register(MSR) corresponding to fetching stage, and using the combination of the PC obtaining from machine status register(MSR) corresponding to fetching stage and PID as the first command identification.
According to one embodiment of the invention, said apparatus 522 is further configured for obtaining program counter value PC and Process identifier PID from machine status register(MSR) corresponding to WB stage, and using the combination of the PC obtaining from machine status register(MSR) corresponding to WB stage and PID as the second command identification.
According to one embodiment of the invention, described control method 400 is further used for having discharged the not device of the storage space of the Content Addressable Memory data item at the instruction place on instruction pipelining.
More than illustrate and of the present inventionly obtained the control method of exceptional instructions and the various embodiments of control device for virtual machine manager.Owing to having described the various embodiments of the device that obtains exceptional instructions for virtual machine manager of the present invention above in detail, to the explanation of obtaining the control method of exceptional instructions and the various embodiments of control device for virtual machine manager, omit and the content that repeat or that can therefrom derive to the explanation of obtaining the various embodiments of the device of exceptional instructions for virtual machine manager.
Process flow diagram in accompanying drawing and block diagram have shown according to architectural framework in the cards, function and the operation of the system of multiple embodiment of the present invention, method and computer program product.In this, the each square frame in process flow diagram or block diagram can represent a part for module, program segment or a code, and a part for described module, program segment or code comprises one or more for realizing the executable instruction of logic function of regulation.Also it should be noted that what the function marking in square frame also can be marked to be different from accompanying drawing occurs in sequence in some realization as an alternative.For example, in fact two continuous square frames can be carried out substantially concurrently, and they also can be carried out by contrary order sometimes, and this determines according to related function.Also be noted that, the combination of the square frame in each square frame and block diagram and/or process flow diagram in block diagram and/or process flow diagram, can realize by the special hardware based system of the function putting rules into practice or operation, or can realize with the combination of specialized hardware and computer instruction.
Below described various embodiments of the present invention, above-mentioned explanation is exemplary, not exhaustive, and be also not limited to disclosed each embodiment.In the case of not departing from the scope and spirit of illustrated each embodiment, many modifications and changes are all apparent for those skilled in the art.The selection of term used herein, is intended to explain best principle, practical application or the improvement to the technology in market of each embodiment, or makes other those of ordinary skill of the art can understand the each embodiment disclosing herein.
Claims (21)
1. one kind is obtained the device (300) of exceptional instructions for virtual machine manager, wherein, described virtual machine manager (220) moves between the physical machine that comprises central processor CPU (212) (210) and virtual machine (230), and described device comprises:
Content Addressable Memory CAM (330);
The addressable special register SPR of virtual machine manager (350); And
Control logic circuit (310), there is the connected input end of CPU and the output terminal being connected with CAM, input end receives the fetching stage and the data that write back the stage from cpu instruction streamline respectively, output terminal makes to be stored in CAM from the instruction in the fetching stage of cpu instruction streamline, and trigger CAM by wherein storage the instruction that belongs to exceptional instructions output to SPR.
2. the device of claim 1, wherein, control logic circuit comprises:
Instruction acquisition module (311), is configured to such an extent that obtain instruction for the fetching stage from cpu instruction streamline;
The first command identification acquisition module (312), is configured to such an extent that obtain the first command identification for the fetching stage from cpu instruction streamline;
Instruction cache module (313), is configured to such an extent that be stored in explicitly CAM for the first command identification that the instruction of instruction acquisition module and the first command identification acquisition module are obtained.
3. the device of claim 1, wherein, control logic circuit further comprises:
The second command identification acquisition module (314), is configured to such an extent that obtain the second command identification for the stage that writes back from instruction pipelining;
Abnormality detection module (315), is configured to obtain the abnormal look-at-me sent for detection of the stage that writes back of instruction pipelining; And
Instruction output module (316), is configured to such an extent that in response to abnormal look-at-me instruction, exceptional instructions has occurred, and makes the instruction being associated with the second command identification in CAM output to SPR.
4. the device of claim 2, wherein, control logic circuit further comprises:
The second command identification acquisition module (314), is configured to such an extent that obtain the second command identification for the stage that writes back from instruction pipelining;
Abnormality detection module (315), is configured to obtain the abnormal look-at-me sent for detection of the stage that writes back of instruction pipelining; And
Instruction output module (316), is configured to such an extent that in response to abnormal look-at-me instruction, exceptional instructions has occurred, and makes the instruction being associated with the second command identification in CAM output to SPR.
5. the device of claim 2, wherein, the first command identification acquisition module is further configured for obtaining program counter value PC and Process identifier PID from machine status register(MSR) corresponding to fetching stage, and using the combination of the program counter value of obtaining from machine status register(MSR) corresponding to fetching stage and Process identifier as the first command identification.
6. the device of claim 3, wherein, the second command identification acquisition module is further configured for obtaining PC and PID from writing back machine status register(MSR) corresponding to stage, and using from the combination that writes back PC that machine status register(MSR) corresponding to stage obtain and PID as the second command identification.
Claim 1-6 one of any device, wherein, control logic circuit further comprises:
CAM administration module, is configured for having discharged the not storage space of the Content Addressable Memory data item at the instruction place on instruction pipelining.
8. one kind is obtained the control method of exceptional instructions for virtual machine manager, wherein, described virtual machine manager (220) moves between the physical machine that comprises central processor CPU (212) (210) and virtual machine (230), and described control method comprises:
Make to be stored in Content Addressable Memory CAM from the instruction in fetching stage of cpu instruction streamline;
According to the result that the stage that writes back of cpu instruction streamline produces, trigger CAM the instruction that belongs to exceptional instructions of wherein storage is outputed to the addressable special register SPR of virtual machine manager.
9. the control method of claim 8, wherein, described in make to be stored in Content Addressable Memory CAM from the instruction in fetching stage of cpu instruction streamline and comprise:
Obtain instruction from the fetching stage of cpu instruction streamline;
Obtain the first command identification from the fetching stage of cpu instruction streamline;
Store explicitly obtained instruction and the first command identification into CAM.
10. the control method of claim 8, wherein, the result triggering CAM that the described stage that writes back according to cpu instruction streamline produces outputs to the addressable special register SPR of virtual machine manager by the instruction that belongs to exceptional instructions of wherein storing and comprises:
Obtain the second command identification from the stage that writes back of instruction pipelining;
The abnormal look-at-me that the stage that writes back of detection instruction pipelining sends; And
There is exceptional instructions in response to abnormal look-at-me instruction, made the instruction being associated with the second command identification in CAM output to SPR.
The control method of 11. claims 9, wherein, the result triggering CAM that the described stage that writes back according to cpu instruction streamline produces outputs to the addressable special register SPR of virtual machine manager by the instruction that belongs to exceptional instructions of wherein storing and comprises:
Obtain the second command identification from the stage that writes back of instruction pipelining;
The abnormal look-at-me that the stage that writes back of detection instruction pipelining sends; And
There is exceptional instructions in response to abnormal look-at-me instruction, made the instruction being associated with the second command identification in CAM output to SPR.
The control method of 12. claims 9, wherein, the described fetching stage from cpu instruction streamline obtains the first command identification and comprises: obtain program counter value PC and Process identifier PID from machine status register(MSR) corresponding to fetching stage, and using the combination of the PC obtaining from machine status register(MSR) corresponding to fetching stage and PID as the first command identification.
The control method of 13. claims 10, wherein, the described stage that writes back from instruction pipelining obtains the second command identification and comprises: obtain program counter value PC and Process identifier PID from writing back machine status register(MSR) corresponding to stage, and using from the combination that writes back PC that machine status register(MSR) corresponding to stage obtain and PID as the second command identification.
One of any control method of 14. claim 8-13, further comprises: discharged the not storage space of the Content Addressable Memory data item at the instruction place on instruction pipelining.
15. 1 kinds are obtained the control device of exceptional instructions for virtual machine manager, wherein, described virtual machine manager (220) moves between the physical machine that comprises central processor CPU (212) (210) and virtual machine (230), and described control device comprises:
Be stored in Content Addressable Memory CAM device for making from the instruction in fetching stage of cpu instruction streamline;
For the result triggering CAM producing according to the stage that writes back of cpu instruction streamline, the instruction that belongs to exceptional instructions of wherein storage is outputed to the device of the addressable special register SPR of virtual machine manager.
The control device of 16. claims 15, wherein, described for the device that is stored in Content Addressable Memory CAM from the instruction in fetching stage of cpu instruction streamline is comprised:
For obtaining the device of instruction from the fetching stage of cpu instruction streamline;
For obtain the device of the first command identification from the fetching stage of cpu instruction streamline;
For obtained instruction and the first command identification being stored explicitly into the device of CAM.
The control device of 17. claims 15, wherein, the described device that the instruction that belongs to exceptional instructions of wherein storage is outputed to the addressable special register SPR of virtual machine manager for the result triggering CAM producing according to the stage that writes back of cpu instruction streamline comprises:
For obtain the device of the second command identification from the stage that writes back of instruction pipelining;
The device of the abnormal look-at-me of sending for detection of the stage that writes back of instruction pipelining; And
For in response to abnormal look-at-me instruction, exceptional instructions having occurred, make the instruction being associated with the second command identification in CAM output to the device of SPR.
The control device of 18. claims 16, wherein, describedly triggers CAM for the result producing according to stage that writes back of cpu instruction streamline and the instruction that belongs to exceptional instructions of storage is wherein outputed to the addressable special register SPR of virtual machine manager comprises:
For obtain the device of the second command identification from the stage that writes back of instruction pipelining;
The device of the abnormal look-at-me of sending for detection of the stage that writes back of instruction pipelining; And
For in response to abnormal look-at-me instruction, exceptional instructions having occurred, make the instruction being associated with the second command identification in CAM output to the device of SPR.
The control device of 19. claims 16, wherein, the described device that obtains the first command identification for the fetching stage from cpu instruction streamline is configured for obtaining program counter value PC and Process identifier PID from machine status register(MSR) corresponding to fetching stage, and using the combination of the PC obtaining from machine status register(MSR) corresponding to fetching stage and PID as the first command identification.
The control device of 20. claims 17, wherein, describedly be configured for obtaining program counter value PC and Process identifier PID from writing back machine status register(MSR) corresponding to stage for obtain the device of the second command identification from the stage that writes back of instruction pipelining, and using from the combination that writes back PC that machine status register(MSR) corresponding to stage obtain and PID as the second command identification.
One of any control device of 21. claim 15-20, further comprises for having discharged the not device of the storage space of the Content Addressable Memory data item at the instruction place on instruction pipelining.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210505800.XA CN103853591B (en) | 2012-11-30 | 2012-11-30 | The device and control method of exceptional instructions are obtained for virtual machine manager |
| TW102133833A TW201435743A (en) | 2012-11-30 | 2013-09-18 | Apparatus and control method for hypervisor to obtain faulting instruction |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210505800.XA CN103853591B (en) | 2012-11-30 | 2012-11-30 | The device and control method of exceptional instructions are obtained for virtual machine manager |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103853591A true CN103853591A (en) | 2014-06-11 |
| CN103853591B CN103853591B (en) | 2017-06-16 |
Family
ID=50861283
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210505800.XA Active CN103853591B (en) | 2012-11-30 | 2012-11-30 | The device and control method of exceptional instructions are obtained for virtual machine manager |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN103853591B (en) |
| TW (1) | TW201435743A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111026504A (en) * | 2019-12-06 | 2020-04-17 | 海光信息技术有限公司 | Processing method and device for configuring instruction for acquiring processor information in virtual machine, CPU chip, system on chip and computer |
| CN114327648A (en) * | 2021-12-16 | 2022-04-12 | 北京安天网络安全技术有限公司 | Drive debugging method and device, electronic equipment and storage medium |
| CN116795493A (en) * | 2023-08-22 | 2023-09-22 | 飞腾信息技术有限公司 | Method for processing instructions, processing system and computer readable storage medium |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1450450A (en) * | 2003-05-15 | 2003-10-22 | 复旦大学 | 32-bit embedded microprocessor adopting double instruction set |
| CN1508690A (en) * | 2002-12-19 | 2004-06-30 | �Ҵ���˾ | Method and system for tracing repeated instruction |
| US20070005942A1 (en) * | 2002-01-14 | 2007-01-04 | Gil Vinitzky | Converting a processor into a compatible virtual multithreaded processor (VMP) |
| US20100005272A1 (en) * | 2004-04-20 | 2010-01-07 | Miljan Vuletic | Virtual memory window with dynamic prefetching support |
| US8055886B2 (en) * | 2007-07-12 | 2011-11-08 | Texas Instruments Incorporated | Processor micro-architecture for compute, save or restore multiple registers and responsive to first instruction for repeated issue of second instruction |
-
2012
- 2012-11-30 CN CN201210505800.XA patent/CN103853591B/en active Active
-
2013
- 2013-09-18 TW TW102133833A patent/TW201435743A/en unknown
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070005942A1 (en) * | 2002-01-14 | 2007-01-04 | Gil Vinitzky | Converting a processor into a compatible virtual multithreaded processor (VMP) |
| CN1508690A (en) * | 2002-12-19 | 2004-06-30 | �Ҵ���˾ | Method and system for tracing repeated instruction |
| CN1450450A (en) * | 2003-05-15 | 2003-10-22 | 复旦大学 | 32-bit embedded microprocessor adopting double instruction set |
| US20100005272A1 (en) * | 2004-04-20 | 2010-01-07 | Miljan Vuletic | Virtual memory window with dynamic prefetching support |
| US8055886B2 (en) * | 2007-07-12 | 2011-11-08 | Texas Instruments Incorporated | Processor micro-architecture for compute, save or restore multiple registers and responsive to first instruction for repeated issue of second instruction |
Non-Patent Citations (1)
| Title |
|---|
| 何海涛: "周期精准的流水线仿真模型", 《微计算机信息》 * |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111026504A (en) * | 2019-12-06 | 2020-04-17 | 海光信息技术有限公司 | Processing method and device for configuring instruction for acquiring processor information in virtual machine, CPU chip, system on chip and computer |
| CN111026504B (en) * | 2019-12-06 | 2023-04-07 | 海光信息技术股份有限公司 | Processing method and device for configuring instruction for acquiring processor information in virtual machine, CPU chip, system on chip and computer |
| CN114327648A (en) * | 2021-12-16 | 2022-04-12 | 北京安天网络安全技术有限公司 | Drive debugging method and device, electronic equipment and storage medium |
| CN114327648B (en) * | 2021-12-16 | 2024-02-02 | 北京安天网络安全技术有限公司 | Driving debugging method and device, electronic equipment and storage medium |
| CN116795493A (en) * | 2023-08-22 | 2023-09-22 | 飞腾信息技术有限公司 | Method for processing instructions, processing system and computer readable storage medium |
| CN116795493B (en) * | 2023-08-22 | 2023-10-31 | 飞腾信息技术有限公司 | Method for processing instructions, processing system and computer readable storage medium |
Also Published As
| Publication number | Publication date |
|---|---|
| TW201435743A (en) | 2014-09-16 |
| CN103853591B (en) | 2017-06-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| RU2664413C2 (en) | Architectural mode configuration in computing system | |
| US9489229B2 (en) | Transparent dynamic code optimization | |
| JP7379502B2 (en) | Directed interrupt virtualization methods, systems, and programs with fallback | |
| US8572604B2 (en) | Method and apparatus to support virtualization with code patches | |
| JP5717847B2 (en) | Method for managing events in a computing environment, computer program for executing the same, and computer system | |
| US10877793B2 (en) | Extending the base address register by modifying the number of read-only bits associated with a device to be presented to a guest operating system | |
| RU2562372C2 (en) | Computation medium adapter activation/deactivation | |
| JP7398465B2 (en) | Interrupt signal transmission method, system, and program for virtualization of directed interrupts | |
| JP6006248B2 (en) | Instruction emulation processor, method and system | |
| JP7459119B2 (en) | Directed interrupt methods, systems and programs for multi-level virtualization using interrupt tables | |
| ES2745709T3 (en) | Instrumentation notification at runtime | |
| JP7450627B2 (en) | How to virtualize directed interrupts using running indicators, systems, programs | |
| JP7448550B2 (en) | How to virtualize directed interrupts using blocking indicators, systems, and programs | |
| US20110161641A1 (en) | SPE Software Instruction Cache | |
| TW201610667A (en) | Managing processing associated with selected architectural facilities | |
| JP2022520928A (en) | How to virtualize directed interrupts using interrupt tables, systems, programs | |
| MX2012014861A (en) | Converting a message signaled interruption into an i/o adapter event notification. | |
| TW201610708A (en) | Common boot sequence for control utility able to be initialized in multiple architectures | |
| JP5934350B2 (en) | Management of operator message buffer for the combined facility | |
| JP2022520713A (en) | Directed interrupt virtualization methods, systems, programs | |
| WO2021061411A1 (en) | Path prediction method used for instruction cache, access control unit, and instruction processing apparatus | |
| JP2013534664A (en) | Computer system, method, and computer program for facilitating communication of actions performed in response to adapter events | |
| CN104364769A (en) | Run-time instrumentation monitoring of processor characteristics | |
| JP5911568B2 (en) | Transmit operator message commands to the binding facility | |
| US20160117200A1 (en) | Resource mapping in multi-threaded central processor units |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant |