CN103855025A - Nmos transistor and manufacturing method thereof - Google Patents
Nmos transistor and manufacturing method thereof Download PDFInfo
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- CN103855025A CN103855025A CN201210516329.4A CN201210516329A CN103855025A CN 103855025 A CN103855025 A CN 103855025A CN 201210516329 A CN201210516329 A CN 201210516329A CN 103855025 A CN103855025 A CN 103855025A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7843—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being an applied insulating layer
Abstract
The invention provides an NMOS transistor and a manufacturing method thereof. The manufacturing method of the NMOS transistor comprises the steps of providing a semiconductor substrate, forming a gate structure on the semiconductor substrate, forming a source electrode and a drain electrode in the semiconductor substrate on the two sides of the gate structure, forming tensile stress layers which cover the gate structure and the semiconductor substrate, removing the tensile stress layer covering the gate structure, and forming a pressure stress layer on the gate structure. According to the NMOS transistor and the manufacturing method thereof, the stress layer with tensile stress on a gate is removed, then the stress layer with pressure stress is formed, downward pressure can be directly generated to the gate, so that the gate generates downward pressure to the substrate, the downward pressure is converted into tension stress in the length direction of a channel, the mobility ratio of electrons in the channel is further improved, and therefore the NMOS transistor is made to have a higher operation speed.
Description
Technical field
The present invention relates to field of semiconductor fabrication, relate in particular to a kind of nmos pass transistor and preparation method thereof.
Background technology
Along with the development of ic manufacturing technology, the characteristic size of integrated circuit constantly reduces; In this development process, in order semiconductor device not to be caused damage, certainly will the operating voltage of integrated circuit also constantly to be reduced accordingly.But in order to guarantee that integrated circuit can keep good performance under less operating voltage, the way conventionally adopting is at present that stress is put in MOS transistor, thereby causes lattice strain, to improve the mobility in charge carrier (electronics or hole).Have a variety of to the technology of MOS transistor stress application, such as: stress memory technique (Stress memorization technique, SMT), dual stressed layers (Dual stress liners, DSL), stress approaches technology (Stress proximity technique, SPT), implant SiGe or SiC(eSiGe/eSiC) form stress liner layer etc., relevant can be CN101924107A Chinese invention patent application with reference to publication No. to the information of CMOS transistor stress application.
In the manufacturing process of high K high-k/metal gate (HKMG) MOS transistor, as follows to a kind of mode of MOS transistor stress application: first in semiconductor device, to form high-K gate dielectric layer, be positioned at the polysilicon dummy gate (dummy poly gate) on gate dielectric layer; Then deposit one or more layers interlayer dielectric layer, utilize chemico-mechanical polishing (CMP) technique to carry out planarization until expose polysilicon dummy gate to interlayer dielectric layer; Remove polysilicon dummy gate, and at polysilicon dummy gate position formation groove, depositing metal layers is so that metal level is filled described groove, and the high-k/metal gate being made up of metal level like this can substitute polysilicon dummy gate, and high-K gate dielectric layer forms high-k/metal gate together with metal level.Wherein, one or more layers interlayer dielectric layer depositing before planarization comprises contact hole etching stop-layer (Contact etch stop layers, CESL), the etching stop layer while forming contact hole as etching interlayer dielectric layer.The material of CESL is generally silicon nitride, and quality is harder.It can produce tensile stress or compression to the semiconductor device of its covering, is specifically determined by the process conditions that form in the depositing operation of silicon nitride.So this one deck silicon nitride, except as CESL, is gone back as the stressor layers to MOS transistor stress application.General, the CESL in nmos pass transistor provides tensile stress, and the CESL in PMOS transistor provides compression.But in this mode, the improvement of pair nmos transistor performance is also not obvious.And, still can not meet the demand for the higher running speed of nmos pass transistor.Therefore, be necessary to provide a kind of nmos pass transistor that can further increase the charge carrier mobility of raceway groove.
Summary of the invention
The problem that the present invention solves is to utilize deposition stressor layers to improve the DeGrain of nmos pass transistor performance.
For addressing the above problem, technical scheme of the present invention has proposed a kind of manufacture method of nmos pass transistor, comprising:
Semiconductor substrate is provided;
In described Semiconductor substrate, form dummy gate, described dummy gate comprises high K medium layer and pseudo-gate material layer;
In the Semiconductor substrate of described dummy gate both sides, form source electrode and drain electrode;
Form tension stress layer, described tension stress layer covers described dummy gate and described Semiconductor substrate;
Removal covers the tension stress layer of described dummy gate top;
Remove described pseudo-gate material layer, and fill grid material at former pseudo-gate material layer place, make described grid material and high K medium layer form high-k/metal gate;
Above described high-k/metal gate, locate to form compressive stress layer.
Optionally, described dummy gate is multiple; After described formation tension stress layer, before removing the tension stress layer that covers described dummy gate top, be also included on tension stress layer and form dielectric layer, to fill up the space between described multiple dummy gate.
Optionally, form after dielectric layer, adopt the mode of cmp to carry out overall planarization, described cmp proceeds to and exposes described dummy gate, to realize the removal of the tension stress layer above described dummy gate.
Optionally, the mode that forms compressive stress layer above described high-k/metal gate is:
After forming high-k/metal gate, on remaining tension stress layer and high-k/metal gate, form interlayer dielectric layer;
Interlayer dielectric layer described in etching forms opening above high-k/metal gate;
In described opening, fill described compressive stress layer.
Optionally, locate to form compressive stress layer above high-k/metal gate after, also comprise:
Above source electrode, drain electrode, form contact hole, and form contact hole in described compressive stress layer.
Optionally, before the step of described formation tension stress layer, be formed with self-aligned metal silicate on the surface of described source electrode and drain electrode.
Technical scheme of the present invention also provides the manufacture method of another kind of nmos pass transistor, comprising:
Semiconductor substrate is provided;
In described Semiconductor substrate, form grid structure, in the Semiconductor substrate of grid structure both sides, form source electrode and drain electrode;
Form tension stress layer, described tension stress layer covers described grid structure and described Semiconductor substrate;
Removal covers the tension stress layer of described grid structure top;
Above grid structure, locate to form compressive stress layer.
Optionally, described grid structure is multiple; After described formation tension stress layer, before removing the tension stress layer that covers described grid structure top, be also included on tension stress layer and form dielectric layer, to fill up the space between described multiple grid structure.
Optionally, form after dielectric layer, adopt the mode of cmp to carry out overall planarization, described cmp proceeds to and exposes described grid structure, to realize the removal of the tension stress layer above described grid structure.
Optionally, the mode that forms compressive stress layer above grid structure is:
After tension stress layer above removal covers described grid structure, on remaining tension stress layer and grid structure, form interlayer dielectric layer;
Interlayer dielectric layer described in etching forms opening above described grid structure;
In described opening, fill described compressive stress layer.
Optionally, described grid structure comprises gate insulator and gate material layers, and wherein, described gate insulator is silica, and described gate material layers is polysilicon.
Optionally, locate to form compressive stress layer above grid structure after, also comprise:
Above source electrode, drain electrode, form contact hole, and form contact hole in described compressive stress layer.
Optionally, before the step of described formation tension stress layer, be formed with self-aligned metal silicate on the surface of described source electrode and drain electrode.
Technical scheme of the present invention also provides a kind of nmos pass transistor, comprising:
Be formed on grid structure in Semiconductor substrate and be arranged in the source-drain area of the Semiconductor substrate of described grid structure both sides;
Cover the stressor layers of the Semiconductor substrate of described grid structure and grid structure both sides, wherein, what be positioned at grid structure top is compressive stress layer, in the Semiconductor substrate of the sidewall of grid structure and grid structure both sides, is tensile stress layer.
Optionally, comprising: in the compressive stress layer on described grid structure, lead to the contact hole that connects described grid structure, the area of the contact-making surface of described contact hole and described grid structure is less than the area of the contact-making surface of described compressive stress layer and described grid structure.
Optionally, described grid structure is polysilicon gate or high-k/metal gate.
Compared with prior art, technical scheme of the present invention has the following advantages:
Technical scheme of the present invention is by removing the stressor layers with tension stress of grid top, form again the stressor layers with compression, the stressor layers with compression forming above grid can directly produce downward pressure to grid, thereby make grid can produce downward pressure to substrate, thereby be converted into the tensile stress along orientation, the mobility of electronics in raceway groove is further increased, thereby make nmos pass transistor there is higher running speed.
Accompanying drawing explanation
Fig. 1 is the schematic diagram that covers tensile stress layer on the source electrode of nmos pass transistor, drain and gate;
Fig. 2 to Fig. 9 is the schematic diagram that forms nmos pass transistor in the embodiment of the present invention.
Embodiment
Inventor finds, for the stressor layers with tensile stress covering on grid and the source-drain electrode of nmos pass transistor, its stress types producing for raceway groove is different.As shown in Figure 1, in source S, drain D and the grid G of nmos pass transistor 3, cover tensile stress layer 300.Inventor is through repeatedly putting into practice and test discovery, and covering the effect that the tensile stress layer 300 in source S and drain D produces for the raceway groove of nmos pass transistor is the tensile stress along orientation with stretching.And the effect of the 300 pairs of raceway groove of part tensile stress layer that grid G top covers is to have compression.That is to say, the stress that the 300 pairs of raceway groove of tensile stress layer that cover at top portions of gates produce is contrary with the stress that the mobility of charge carrier in raising NMOS raceway groove needs, like this, not only can not play the effect that improves NMOS channel performance, also produce minus effect, weakened the effect of source S and drain D upper stress layer 300.
In order to address this problem, and the performance of the raising nmos pass transistor of trying one's best, the creationary proposition of inventor removed grid G top stressor layers 300, then forms the method for the stressor layers with compression.Like this, the stressor layers with tension stress 300 of grid G top has been removed, remove improving the reactive factor of carrier mobility in raceway groove, and the stressor layers with compression forming directly produces downward pressure to grid, make grid produce downward pressure to substrate, thereby be converted into the tensile stress along orientation, the mobility of electronics in raceway groove further increased, thereby make nmos pass transistor there is higher running speed.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.
Embodiment mono-
Following structure chart 2 to Fig. 9 is set forth and in the present embodiment, is formed the process of nmos pass transistor and the structure of the final nmos pass transistor forming.
As shown in Figure 2, provide Semiconductor substrate 100, in described Semiconductor substrate 100, form source S, drain D and the grid structure of nmos pass transistor, and cover the stressor layers 103 in grid structure and described Semiconductor substrate 100.
In the present embodiment, described Semiconductor substrate can be the lightly doped Semiconductor substrate of P type, or has the Semiconductor substrate of P trap.Described source S, drain D and grid structure are formed in the region at P trap place.
Described grid structure comprises gate insulator 101 and gate material layers 104.
In this step of the present embodiment, described grid structure is dummy gate, and wherein, described gate insulator 101 is high K medium layer, and described gate material layers 104 is pseudo-gate material layer, and material is polysilicon.Described pseudo-gate material layer 104 is preformed according to the needs of the rear grid technique of formation high-K metal gate in this step, and it can be removed in subsequent technique, and then fills out new grid material, forms the real grid of nmos pass transistor.
Described source S, drain D are the N-type high-concentration dopant district that is arranged in the Semiconductor substrate 100 of described grid structure both sides.
The material of described stressor layers 103 is silicon nitride, and its effect has two kinds: the one, when in subsequent technique, etching interlayer dielectric layer forms contact hole, as contact hole etching stop-layer (Contact etch stop layers, CESL); Another effect is that the raceway groove of pair nmos transistor provides tensile stress.
Wherein, also have the metal silicide (not shown) that adopts self-registered technology to form in source S, drain D, described metal silicide is NiSi or NiPtSi, and in NiPtSi metal silicide, the shared mass percent of Pt is 5 ~ 10%.The effect of described metal silicide is to reduce in the nmos pass transistor finally having formed, the contact resistance between source S, drain D and contact hole.In the present embodiment, before described self-aligned metal silicate is formed on stressor layers 103 coverings.Like this, can make stressor layers 103 be retained in nmos pass transistor surface, maintain transistorized raceway groove stress application.Common stressor layers supplying method comprises stress memory technique etc., stress memory technique is that the mode by having annealed after having formed stressor layers is remembered in substrate stress, in the process of annealing, silicon in substrate can expand, and stressor layers can fetter the expansion of the silicon of substrate surface, keep the lattice structure similar with stressor layers, the stress in stressor layers is remembered in substrate like this, and raceway groove is produced to stress.Then, then stressor layers remove.After stressor layers is removed, just can form the processing step that self-aligned metal silicate, formation inter-level dielectric etc. need to directly be processed substrate.And in the present embodiment, can come raceway groove stress application by retaining stressor layers.Do not need just can make stress can be applied on raceway groove by this step of annealing, can avoid so the bad impact of annealing and making the Impurity Diffusion in the ion doped region in the substrate such as source S, drain D and bring.And the impact bringing on metal silicide of avoiding annealing to bring.Meanwhile, owing to not needing to remove stressor layers, the impact on metal silicide surface resistance can also avoid removing stressor layers time.
Next, as shown in Figure 3, form dielectric layer 105 on the surface of stressor layers 103.
Shown in figure, be only a grid structure, but those skilled in the art can imagine, in the process of whole semiconductor technology, relate to several grid structures that are positioned on same semiconductor base.After forming stressor layers 103 through previous step, the stressor layers 103 between grid structure and grid structure can be formed with depression.In order to make overall planarization, form again one deck dielectric layer 105 on described stressor layers 103 surfaces, to fill up the space between grid structure and grid structure, until the surface of described dielectric layer 105 at least exceedes grid structure surface.
Described dielectric layer 105 is the conventional materials of interlayer dielectric layer such as silica or advanced low-k materials, and generation type can be deposition or spin coating.
Next, as shown in Figure 4, remove dielectric layer 105 and the stressor layers 103 on grid structure surface.
In the present embodiment, removing the dielectric layer 105 on grid structure surface and the mode of stressor layers 103 is cmp, and described cmp proceeds to and exposes pseudo-gate material layer 104 and stop.Like this, dielectric layer 105 and stressor layers 103 on grid structure have been removed, but the dielectric layer in other region 105 and stressor layers 103 are still withed a hook at the end.
Next, as shown in Figure 5, remove the pseudo-gate material layer 104 in grid structure, form breach 20 in the position at its original place.
In previous step, removed dielectric layer 105 and the stressor layers 103 on grid structure surface by cmp, expose gate material layers 104.In this step, can directly remove by wet etching the pseudo-gate material layer 104 coming out.In the present embodiment, the grid structure of removing is dummy gate, in order that form high-k/metal gate according to rear grid technique.The object of removing pseudo-gate material layer 104 in this step is for being packed into workfunction layers at pseudo-gate material layer 104 places in subsequent technique, to form high-k/metal gate with high K medium layer 101.
Next, as shown in Figure 6, deposition one NMOS workfunction layers 106, in the interior formation one NMOS workfunction layers 106 of breach 20 as shown in Figure 5, to form the grid structure of high-k/metal gate with high K medium layer 101.The formation method of described formation NMOS workfunction layers 106 is deposition or plating.
Next, as shown in Figure 7, on workfunction layers 106, stressor layers 103 and dielectric layer 105, form interlayer dielectric layer 107.
Described interlayer dielectric layer 107 can be silica, advanced low-k materials or ultra-low dielectric constant material.Generation type can be deposition or spin coating.
Then, continue with reference to shown in figure 7, in the interlayer dielectric layer 107 directly over high-k/metal gate, form opening 22.Preferably, described opening 22 just in time exposes described high-k/metal gate completely.
The mode of described formation opening 22 can be plasma dry etch process, can be also wet etching.Concrete operations can be: above interlayer dielectric layer 107, cover one deck photoresist, form photoetching offset plate figure by photoetching and expose the interlayer dielectric layer 107 above high-k/metal gate, then thereby etching is removed the interlayer dielectric layer 107 coming out and is formed opening 22, then utilizes ashing method to remove photoresist.
Wherein, the size of above-mentioned opening 22 has determined in subsequent technique, to be filled in the size of the compressive stress layer in opening 22, thereby has determined the size of the pressure that grid receives.Described compressive stress layer does not cover high-k/metal gate completely, can make the pressure that high-k/metal gate is subject to not reach maximum, and effect can not be best.And, for fear of follow-up on high-k/metal gate, form contact hole after, the shell of compression that can also try one's best in many described openings 22 of reservation, it is large that described opening 22 should be tried one's best.And if described compressive stress layer has exceeded described high-k/metal gate, can make pressure pass to Semiconductor substrate from the interlayer dielectric layer of high-k/metal gate both sides, transistorized performance is improved to the passive effect of playing.The size of described opening 22 and position are take the upper surface that just exposes high-k/metal gate structure as optimum, the compressive stress layer being filled in after can making like this in opening 22 just in time covers the upper surface of living high-k/metal gate completely, can offer the pressure of high-k/metal gate maximum in the cards, and transistorized performance not improved and produces negative effect.
Next, as shown in Figure 8, in described opening 22, form compressive stress layer 108, described compressive stress layer 108 has compression.
The method that forms compressive stress layer 108 can be deposition, and concrete operations are: in the semiconductor structure shown in Fig. 7, form compressive stress layer 108 by deposition, described compressive stress layer 108 has compression, fill full gate mouth 22.Process parameter control by deposition can make described compressive stress layer 108 have compression.The compressive stress layer 108 that the overall situation forms also has the surperficial part that covers interlayer dielectric layer 107.Then, by cmp or eat-back, the surperficial part that covers interlayer dielectric layer 107 is removed, only retained the part being filled in opening 22.
The compressive stress layer 108 being formed on high-k/metal gate can produce direct pressure to high-k/metal gate, thereby make high-k/metal gate produce downward pressure to substrate, thereby be converted into the tensile stress along orientation, the mobility of electronics in raceway groove is further increased, thereby make nmos pass transistor there is higher running speed.
So far, form the nmos pass transistor that the present embodiment provides, it comprises:
Be formed on grid structure in Semiconductor substrate 100 and be arranged in source region S and the drain region D of the Semiconductor substrate of described grid structure both sides;
Cover the stressor layers 103 and 108 of the Semiconductor substrate of described grid structure and grid structure both sides, wherein, what be positioned at grid structure top is compressive stress layer 108, in the Semiconductor substrate of the sidewall of grid structure and grid structure both sides, is tensile stress layer 103.
The source region S of described nmos pass transistor and drain region D also can also lead to realize and realize with other semiconductor device the contact hole 13 being electrically connected, in the compressive stress layer 108 of described grid structure top, lead to and realize the contact hole 14 of realizing the described grid structure being electrically connected with other semiconductor device, the area of the contact-making surface of described contact hole 14 and described grid structure is less than the area of the contact-making surface of described compressive stress layer and described grid structure.Described grid structure is high-k/metal gate, comprises workfunction layers 106 and high K medium layer 101.
What those skilled in the art can understand is, although the contact hole on described high-k/metal gate 14 can be through compressive stress layer 108, but because the area of contact hole 14 and high-k/metal gate contact-making surface is less than the upper surface of high-k/metal gate, thereby, described compressive stress layer 108 also can reserve part around contact hole, grid is produced to compression, thereby the raceway groove of pair nmos transistor produces tensile stress.
Embodiment bis-
In the present embodiment, described nmos pass transistor is the nmos pass transistor of general polysilicon gate, and described grid structure comprises gate insulator and gate material layers.Described gate insulation layer is silica, and described gate material layers is polysilicon.After forming well, directly as the grid of nmos pass transistor, do not need removal to form again high-k/metal gate.In addition, other processing step of the present embodiment and operation and embodiment mono-are similar.
Concrete, the step of the present embodiment comprises:
Semiconductor substrate is provided, in described Semiconductor substrate, forms source electrode, the drain and gate structure of nmos pass transistor, and cover the tensile stress layer in grid structure and described Semiconductor substrate.The material of described tensile stress layer is silicon nitride, and its effect has two kinds: the one, when in subsequent technique, etching interlayer dielectric layer forms contact hole, as contact hole etching stop-layer (Contact etch stop layers, CESL); Another effect is that the raceway groove of pair nmos transistor provides tensile stress;
Form another layer of dielectric layer on the surface of silicon nitride, to be filled to the surface that exceedes grid structure.The material of described dielectric layer can be silica, and it act as the space of filling up between grid structure and grid structure, until the surface of described dielectric layer at least exceedes grid structure surface;
Adopt cmp to carry out overall planarization and remove dielectric layer and the contact hole etching stop-layer on grid structure surface;
On grid structure surface, tensile stress layer and silica, form interlayer dielectric layer, and form opening in interlayer dielectric layer directly over grid structure;
In described opening, form compressive stress layer;
Above source electrode, drain and gate structure, form contact hole.
So far, the nmos pass transistor of the polysilicon gate that formation the present embodiment provides, it comprises:
Be formed on grid structure in Semiconductor substrate and be arranged in the source-drain area of the Semiconductor substrate of described grid structure both sides;
Cover the stressor layers of the Semiconductor substrate of described grid structure and grid structure both sides, wherein, what be positioned at grid structure top is compressive stress layer, in the Semiconductor substrate of the sidewall of grid structure and grid structure both sides, is tensile stress layer.
In compressive stress layer on described grid structure, lead to the contact hole that connects described grid structure, the area of the contact-making surface of described contact hole and described grid structure is less than the area of the contact-making surface of described compressive stress layer and described grid structure.
Described grid structure is polysilicon gate.
The above, be only preferred embodiment of the present invention, not the present invention done to any pro forma restriction.
Although the present invention discloses as above with preferred embodiment, but not in order to limit the present invention.Any those of ordinary skill in the art, do not departing from technical solution of the present invention scope situation, all can utilize method and the technology contents of above-mentioned announcement to make many possible variations and modification to technical solution of the present invention, or be revised as the equivalent embodiment of equivalent variations.Therefore, every content that does not depart from technical solution of the present invention,, all still belongs in the scope of technical solution of the present invention protection any simple modification made for any of the above embodiments, equivalent variations and modification according to technical spirit of the present invention.
Claims (16)
1. a manufacture method for nmos pass transistor, is characterized in that, comprising:
Semiconductor substrate is provided;
In described Semiconductor substrate, form dummy gate, described dummy gate comprises high K medium layer and pseudo-gate material layer;
In the Semiconductor substrate of described dummy gate both sides, form source electrode and drain electrode;
Form tension stress layer, described tension stress layer covers described dummy gate and described Semiconductor substrate;
Removal covers the tension stress layer of described dummy gate top;
Remove described pseudo-gate material layer, and fill grid material at former pseudo-gate material layer place, make described grid material and high K medium layer form high-k/metal gate;
Above described high-k/metal gate, locate to form compressive stress layer.
2. manufacture method as claimed in claim 1, is characterized in that, described dummy gate is multiple; After described formation tension stress layer, before removing the tension stress layer that covers described dummy gate top, be also included on tension stress layer and form dielectric layer, to fill up the space between multiple described dummy gates.
3. manufacture method as claimed in claim 2, it is characterized in that, form after dielectric layer, adopt the mode of cmp to carry out overall planarization, described cmp proceeds to and exposes described dummy gate, to realize the removal of the tension stress layer above described dummy gate.
4. manufacture method as claimed in claim 1, is characterized in that, the mode that forms compressive stress layer above described high-k/metal gate is:
After forming high-k/metal gate, on remaining tension stress layer and high-k/metal gate, form interlayer dielectric layer;
Interlayer dielectric layer described in etching forms opening above high-k/metal gate;
In described opening, fill described compressive stress layer.
5. the manufacture method as described in claim 1 or 4, is characterized in that, after locating to form compressive stress layer, also comprises above high-k/metal gate:
Above source electrode, drain electrode, form contact hole, and form contact hole in described compressive stress layer.
6. manufacture method as claimed in claim 1, is characterized in that, before carrying out the step of described formation tension stress layer, the surface of described source electrode and drain electrode is formed with self-aligned metal silicate.
7. a manufacture method for nmos pass transistor, is characterized in that, comprising:
Semiconductor substrate is provided;
In described Semiconductor substrate, form grid structure, in the Semiconductor substrate of grid structure both sides, form source electrode and drain electrode;
Form tension stress layer, described tension stress layer covers described grid structure and described Semiconductor substrate;
Removal covers the tension stress layer of described grid structure top;
Above grid structure, locate to form compressive stress layer.
8. manufacture method as claimed in claim 7, is characterized in that, described grid structure is multiple; After described formation tension stress layer, before removing the tension stress layer that covers described grid structure top, be also included on tension stress layer and form dielectric layer, to fill up the space between multiple described grid structures.
9. manufacture method as claimed in claim 8, it is characterized in that, form after dielectric layer, adopt the mode of cmp to carry out overall planarization, described cmp proceeds to and exposes described grid structure, to realize the removal of the tension stress layer above described grid structure.
10. the manufacture method as described in claim 7 or 9, is characterized in that, the mode that forms compressive stress layer above grid structure is:
After tension stress layer above removal covers described grid structure, on remaining tension stress layer and grid structure, form interlayer dielectric layer;
Interlayer dielectric layer described in etching forms opening above described grid structure;
In described opening, fill described compressive stress layer.
11. manufacture methods as claimed in claim 7, is characterized in that, described grid structure comprises gate insulator and gate material layers, and wherein, described gate insulator is silica, and described gate material layers is polysilicon.
12. manufacture methods as claimed in claim 7, is characterized in that, after locating to form compressive stress layer, also comprise above grid structure:
Above source electrode, drain electrode, form contact hole, and form contact hole in described compressive stress layer.
13. manufacture methods as claimed in claim 7, is characterized in that, before the step of described formation tension stress layer, are formed with self-aligned metal silicate on the surface of described source electrode and drain electrode.
14. 1 kinds of nmos pass transistors, is characterized in that, comprising:
Be formed on grid structure in Semiconductor substrate and be arranged in the source-drain area of the Semiconductor substrate of described grid structure both sides;
Cover the stressor layers of the Semiconductor substrate of described grid structure and grid structure both sides, wherein, what be positioned at grid structure top is compressive stress layer, in the Semiconductor substrate of the sidewall of grid structure and grid structure both sides, is tensile stress layer.
15. nmos pass transistors as claimed in claim 14, it is characterized in that, in compressive stress layer on described grid structure, lead to the contact hole that connects described grid structure, the area of the contact-making surface of described contact hole and described grid structure is less than the area of the contact-making surface of described compressive stress layer and described grid structure.
16. nmos pass transistors as claimed in claim 14, is characterized in that, described grid structure is polysilicon gate or high-k/metal gate.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2023077461A1 (en) * | 2021-11-05 | 2023-05-11 | 苏州晶湛半导体有限公司 | Hemt device and manufacturing method therefor |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6717216B1 (en) * | 2002-12-12 | 2004-04-06 | International Business Machines Corporation | SOI based field effect transistor having a compressive film in undercut area under the channel and a method of making the device |
| US20060125028A1 (en) * | 2004-12-15 | 2006-06-15 | Chien-Hao Chen | MOSFET device with localized stressor |
| CN101207126A (en) * | 2006-12-22 | 2008-06-25 | 国际商业机器公司 | Scalable strained fet device and method of fabricating the same |
| CN101388399A (en) * | 2007-09-14 | 2009-03-18 | 国际商业机器公司 | Metal oxide semiconductor junction using hybrid orientation and method for manufacturing same |
| CN103094108A (en) * | 2011-10-29 | 2013-05-08 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method for semiconductor device |
-
2012
- 2012-12-05 CN CN201210516329.4A patent/CN103855025B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6717216B1 (en) * | 2002-12-12 | 2004-04-06 | International Business Machines Corporation | SOI based field effect transistor having a compressive film in undercut area under the channel and a method of making the device |
| US20060125028A1 (en) * | 2004-12-15 | 2006-06-15 | Chien-Hao Chen | MOSFET device with localized stressor |
| CN101207126A (en) * | 2006-12-22 | 2008-06-25 | 国际商业机器公司 | Scalable strained fet device and method of fabricating the same |
| CN101388399A (en) * | 2007-09-14 | 2009-03-18 | 国际商业机器公司 | Metal oxide semiconductor junction using hybrid orientation and method for manufacturing same |
| CN103094108A (en) * | 2011-10-29 | 2013-05-08 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method for semiconductor device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023077461A1 (en) * | 2021-11-05 | 2023-05-11 | 苏州晶湛半导体有限公司 | Hemt device and manufacturing method therefor |
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