CN103870407B - The memorizer of mobile terminal and the method for attachment of processor and attachment structure - Google Patents
The memorizer of mobile terminal and the method for attachment of processor and attachment structure Download PDFInfo
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- CN103870407B CN103870407B CN201210532216.3A CN201210532216A CN103870407B CN 103870407 B CN103870407 B CN 103870407B CN 201210532216 A CN201210532216 A CN 201210532216A CN 103870407 B CN103870407 B CN 103870407B
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Abstract
The present invention relates to the memorizer of a kind of mobile terminal simplifying printed circuit board (PCB) cabling and the method for attachment of processor, it is applicable to synchronous DRAM, this memorizer includes multiple first data pin, every 8 the first data pin corresponding multiple first control pin, this processor includes multiple second data pin, every 8 the second data pin corresponding multiple second control pin, and the method comprises the following steps: by byte, the first data pin of this memorizer and the first control pin of correspondence thereof are divided into multiple first pin set；Second data pin of this processor and the second control pin of correspondence thereof are divided into multiple second pin set by byte；The plurality of first pin set is matched with the plurality of second pin set；And between the first pin set and the second pin set forming pairing, control pin by first and the second control pin connects correspondingly, and 8 the first data pin are at random connected with 8 the second data pin.
Description
Technical field
The present invention relates to the printed circuit board layout design of mobile terminal, more particularly, it relates to a kind of mobile
The memorizer of terminal and the method for attachment of processor and attachment structure.
Background technology
Along with gradually popularizing of smart mobile phone and panel computer, have call, online browsing, multimedia application,
The mobile terminal of the functions such as digital map navigation becomes the daily necessities of people.Due to ever-increasing application
Demand, mobile terminal disposal ability improves constantly, and storage medium capacity constantly increases, and operating system is the most increasingly
Complicated.Correspondingly, the figure place of processor and memorizer has risen to considerable 32 and has continued growth.
So, the line of the components and parts on the printed circuit board (PCB) (PCB) within mobile terminal will be more complicated.
As a example by memorizer, mobile phone often uses SDRAM(synchronous DRAM), example
As mono-in SDR-SDRAM(times of speed synchronous DRAM) or DDR-SDRAM(Double Data Rate
Synchronous DRAM), DDR2-SDRAM or DDR3-SDRAM empty as the operation of code
Between.When using the DDR-SDRAM chip of 32 bit wides, conventionally can be by the number of processor (CPU)
Do as shown in Figure 1A, 1B according to data pin D31-D0 of pin D31-D0 Yu DDR-SDRAM chip
Connection correspondingly, connected mode is as follows:
Data pin D0 of CPU is connected with data pin D0 of DDR-SDRAM chip；
Data pin D1 of CPU is connected with data pin D1 of DDR-SDRAM chip；
Data pin D2 of CPU is connected with data pin D2 of DDR-SDRAM chip；
Data pin D3 of CPU is connected with data pin D3 of DDR-SDRAM chip；
…………
The like；
Data pin D28 of CPU is connected with data pin D28 of DDR-SDRAM chip；
Data pin D29 of CPU is connected with data pin D29 of DDR-SDRAM chip；
Data pin D30 of CPU is connected with data pin D30 of DDR-SDRAM chip；
Data pin D31 of CPU is connected with data pin D31 of DDR-SDRAM chip.
Due to the necessary one_to_one corresponding of the data pin between processor and DDR chip, and require isometric
Line, this brings extreme difficulties to the cabling of pcb board.
Summary of the invention
The technical problem to be solved is to provide a kind of mobile end that can simplify printed circuit board (PCB) cabling
The memorizer of end with and the method for attachment of processor and attachment structure.
Conventional processor and the connected mode of memorizer, when connecting the data pin of processor and memorizer,
Habitually the data pin of same position is connected, to ensure the accurate of the transmission of data between the two and command operation
Property.But present inventor is by finding after analyzing, for synchronized SRAM, due to
The ultimate unit of its storage is " byte ", when connecting the data pin of processor and memorizer, as long as by number
It is one group according to pin with 8 (i.e. 1 byte) to be divided into some groups and connect respectively, and does not consider each data in group
Corresponding annexation between pin, though exist data pin dislocation connect, do not result in yet data transmission and
The accuracy of command operation.
Based on above-mentioned analysis, the present invention proposes the memorizer of a kind of mobile terminal and the method for attachment of processor, suitable
For synchronous DRAM, this memorizer includes multiple first data pin, every 8 the first data
Pin corresponding multiple first controls pin, and this processor includes multiple second data pin, every 8 second numbers
Controlling pin according to pin corresponding multiple second, the method comprises the following steps: by the first data of this memorizer
First control pin of pin and correspondence thereof is divided into multiple first pin set by byte；By the second of this processor
Second control pin of data pin and correspondence thereof is divided into multiple second pin set by byte；By the plurality of first
Pin set is matched with the plurality of second pin set；And draw in the first pin set and second forming pairing
Between foot group, control pin by first and the second control pin connects correspondingly, and by 8 first numbers
At random connect according to pin and 8 the second data pin.
In one embodiment of this invention, the plurality of first pin set is joined with the plurality of second pin set
To step include: the first pin set and the second pin set that are in same position are matched.
In one embodiment of this invention, the plurality of first pin set is joined with the plurality of second pin set
To step include: the first pin set and the second pin set that are in diverse location are matched.
In one embodiment of this invention, by 8 the first data pin with 8 the second data pin at random
The step connected includes: the cabling of the printed circuit board (PCB) installed with this processor according to this memorizer require into
Row connects.
The present invention separately proposes the memorizer of a kind of mobile terminal and the attachment structure of processor, it is adaptable to synchronize dynamic
State random access memory, this attachment structure includes memorizer and processor.This memorizer includes multiple first data
Pin, every 8 the first data pin corresponding multiple first control pin.This processor includes multiple second number
According to pin, every 8 the second data pin corresponding multiple second control pin.Wherein, the first of this memorizer
First control pin of data pin and correspondence thereof is divided into multiple first pin set by byte, the of this processor
Second control pin of two data pin and correspondence thereof is divided into multiple second pin set by byte；The plurality of first
Pin set and the plurality of second pin set form pairing respectively, and are forming first pin set and second of pairing
Between pin set, the first control pin and second controls pin and connects correspondingly, and 8 the first data
Pin and 8 the second data pin at random connect.
In one embodiment of this invention, carry out the first pin set of matching and the second pin set is in identical
Position.
In one embodiment of this invention, the first pin set carrying out matching is at least part of with the second pin set
It is in diverse location.
In one embodiment of this invention, this memorizer is single times of speed synchronous DRAM.
In one embodiment of this invention, this memorizer is Double Data Rate synchronous DRAM.
In one embodiment of this invention, the first data pin of this memorizer is 16,32 or 64,
Second data pin of this processor is 16,32 or 64.
Due to the fact that time the synchronization static random access memory of mobile terminal and processor are attached, by number
Being grouped according to pin and allow the data pin in group to be arbitrarily attached, this makes can basis when design
PCB signal connection, carries out holding wire and adjusts to find the company simplifying PCB trace each data pin
Connect mode.
Accompanying drawing explanation
For the above-mentioned purpose of the present invention, feature and advantage can be become apparent, below in conjunction with accompanying drawing to this
Bright detailed description of the invention elaborates, wherein:
Figure 1A, 1B illustrate processor and the conventional connected mode of memory chip in mobile phone.
Fig. 2 A-2C illustrates the processor of one embodiment of the invention and the connected mode of memory chip.
Fig. 3 illustrates that the least-significant byte data between the processor of one embodiment of the invention and memory chip exist mistake
The situation that position connects.
Fig. 4 illustrates that the byte between the processor of one embodiment of the invention and memory chip exists dislocation and connects
Situation.
Fig. 5 illustrates the processor of one embodiment of the invention and the method for attachment of memory chip.
Detailed description of the invention
For synchronized SRAM (SDRAM), the ultimate unit of its storage is " byte ",
And every 8 bit data pins are equipped with conversion and control pin.For current SDRAM, control pin
Quantity is two.At present conventional method method is by first data pin of SDRAM and processor
(CPU) the second data pin connects correspondingly.That is, the data pin of same position is attached.
As a example by least-significant byte data pin, can be by the D0 ~ D7 of CPU and the D0 ~ D7 of synchronized SRAM
One_to_one corresponding is connected, second data pin D0 of CPU and first data pin D0 of SDRAM
Connecting, second data pin D1 of CPU is connected with first data pin D1 of SDRAM, with this type of
Push away.According to conventional method of attachment, when printed circuit board (PCB) (PCB) connects up, there will be data wire unavoidably
Situation about intersecting, therefore there will be the situation changing layer or coiling during PCB layout.
But found by analysis, it is not necessary for connecting correspondingly between above-mentioned data pin.Number
Connect according to the dislocation between pin and appear to be kind of a mistake, but it was unexpected that the read-write of data is not had by it
Impact.
As a example by D0 ~ D7 bit data, as shown in Figure 3, it is assumed that the connection between CPU and SDRAM is
The D1 of D0 with SDRAM of CPU is connected, and the D0 of D1 with SDRAM of CPU is connected, remaining letter
Number line D2 ~ D7 one_to_one corresponding.Writing data at the A address being intended in CPU in SDRAM is 0000
0001, then misplacing owing to data wire intersects, in SDRAM space, at A address, stored data is actual is 0000
0010；When CPU is intended to read least-significant byte data at the A address of SDRAM, actual in SDRAM deposit
Storage data are 00000010, but misplace owing to data wire intersects, and after reading CPU inside, data should be 0000
0001, this explanation CPU reads data still after writing data 00000001 at A address again at this address
It is 00000001.
Therefore that analyze it was concluded that in D0 ~ D7 error in data for CPU, carrying out least-significant byte data reading
When writing be do not have influential.This conclusion can be generalized to the data pin of optional position, such as most-significant byte number
According to pin.
Further, above-mentioned dislocation does not interferes with the CPU command operation to SDRAM.According to SDRAM
Matter understand, CPU to SDRAM(SDR-SDRAM, DDR-SDRAM, DDR2-SDRAM,
DDR3-SDRAM) command operation, completely relevant by control signal wire and address wire, unrelated with data wire.
Command operation includes: depositor write and depositor read, Burst is arranged and burst operation, precharge set
Put and all of command operations such as precharge operation, as shown in 1B, command operation only with CKE, CK, CK#,
CS, WE, CAS, RAS, BANK0, BANK1, Address are relevant, unrelated with data signal line,
So the dislocation of data pin does not interferes with the CPU command operation to SDRAM.
So, when connecting the data pin of CPU and SDRAM, as long as by data pin with 8 (i.e. 1
Byte) it is one group and is divided into and some assembles connection, and do not consider the corresponding connection between each data pin in group
Relation, even if the dislocation that there is data pin connects, does not results in data transmission and the accuracy of command operation yet.
In the context of the present invention, SDRAM comprise SDR-SDRAM, DDR-SDRAM,
DDR2-SDRAM, DDR3-SDRAM, and the memorizer of the SDRAM type occurred from now on.
Therefore, the memorizer of a kind of mobile terminal proposed by the invention and the method for attachment of processor, with reference to figure
Shown in 5, the method comprises the following steps:
In step 501, first data pin of SDRAM and the first control pin of correspondence thereof are pressed byte
It is divided into multiple first pin set.Shown in reference Fig. 2 A and 2B, first data pin D31-D0 of SDRAM,
And the first control pin DQS3-DQS0, DQM3-DQM0 of correspondence is divided into 4 the first pin set.
Here, be referred to as pin set 0, pin set 1, pin set 2, pin set 3 from low to high by byte.
In step 502, second data pin of CPU and the second control pin of correspondence thereof are divided into by byte
Multiple second pin set.Shown in reference Fig. 2 A and 2B, second data pin D31-D0 of CPU, and
The second corresponding control pin DQS3-DQS0, DQM3-DQM0 is divided into 4 the second pin set.?
This, be referred to as pin set 0, pin set 1, pin set 2, pin set 3 from low to high by byte.
In step 503, multiple first pin set are matched with multiple second pin set.
Referring still to shown in Fig. 2 A and 2B, common pairing, same position (the most identical sequence can be will be located in
Number) pin set match.Such as, the pin set 0 of the pin set 0 and CPU of SDRAM is matched,
The pin set 1 of the pin set 1 and CPU of SDRAM is matched, drawing of the pin set 2 and CPU of SDRAM
Foot group 2 is matched, and the pin set 3 of the pin set 3 and CPU of SDRAM is matched.
In step 504, between the first pin set and the second pin set forming pairing, control to draw by first
Foot and second controls pin and connects correspondingly, and 8 the first data pin is drawn with 8 the second data
Foot at random connects.
Referring still to shown in Fig. 2 A and 2B, between the pin set of each pairing formed, control pin still
Strictly connect one to one.Such as SDRAM wherein one first control pin DQS0 Yu CPU its
In one second control pin DQS0 and connect, another of SDRAM first controls pin DQS0 Yu CPU
Another second control pin DQS0 connects.But, can at random connect between 8 bit data pins.Example
As can be any between least-significant byte data pin D7-D0 and the least-significant byte data pin of CPU of SDRAM
Connect.Rectangle frame in Fig. 2 A, 2B illustrates this any annexation.
The benefit of above-mentioned any connection is, but can be according to PCB signal connection, to each data pin
Carry out holding wire adjustment.In such manner, it is possible to find more excellent mode, complete the holding wire between data pin and connect.
It is desired that the mode of a kind of optimum can be found, with one layer of PCB, complete the signal of data pin
Line connects.So, both can simplify PCB trace, occur without intersection, data wire can well have been controlled again
Isometric requirement.
It should be noted that the data focused between SDRAM and CPU of embodiments of the invention
The connected mode of pin, and the annexation between address pin and master control pin is not specially limited.Logical
It is attached still according to mode one to one between Chang Eryan, these address pin and master control pin, example
As shown in Figure 2 C.
In the step 503 of above-described embodiment, it it is the pin set that will be located in same position (i.e. same sequence number)
Match.But in another embodiment, can draw be in diverse location (i.e. different sequence number) first
Foot group and the second pin set are matched.In other words, the pairing of pin set can not consider that each pin set is in institute
There is location in pin set, and arbitrarily match.Referring for example to shown in Fig. 4, such as, by SDRAM
The pin set 1 of pin set 0 and CPU match, the pin set 0 of the pin set 1 and CPU of SDRAM
Matching, the pin set 2 of the pin set 2 and CPU of SDRAM is matched, the pin set 3 and CPU of SDRAM
Pin set 3 match.So, at least one is carried out between the pin set matched between SDRAM and CPU
It is partially in diverse location.At this moment, the annexation between the data pin in the pin set after pairing is still
Can be arbitrary.
In above embodiment, although illustrate as a example by the SDRAM of 32, it is to be understood that
It is that embodiments of the invention are applicable between the CPU of 16 or the SDRAM of 64 and identical figure place
Connect.
The synchronization static random access memory of mobile terminal is being attached by embodiments of the invention with processor
Time, data pin is grouped and allow the data pin in group be arbitrarily attached, this makes can when design
With according to PCB signal connection, each data pin is carried out holding wire and adjusts to find simplification PCB to walk
The connected mode of line.
Although the present invention describes with reference to current specific embodiment, but common skill in the art
Art personnel are it should be appreciated that above embodiment is intended merely to the present invention is described, without departing from present invention essence
Change or the replacement of various equivalence also can be made, therefore, as long as at the connotation of the present invention in the case of god
In the range of change, the modification of above-described embodiment all will be fallen in the range of following claims.
Claims (10)
1. the memorizer of a mobile terminal and the method for attachment of processor, it is adaptable to synchronous dynamic random stores
Device, this memorizer includes that multiple first data pin, every 8 the first data pin corresponding multiple first control
Pin, this processor includes multiple second data pin, corresponding multiple second controls of every 8 the second data pin
Making foot, the method comprises the following steps:
First control pin of the first data pin of this memorizer and correspondence thereof is divided into multiple the by byte
One pin set；
Second control pin of the second data pin of this processor and correspondence thereof is divided into multiple the by byte
Two pin set；
The plurality of first pin set is matched with the plurality of second pin set；And
Between the first pin set and the second pin set forming pairing, control pin and second by first and control
Pin connects correspondingly, and 8 the first data pin is at random connected with 8 the second data pin.
2. the method for attachment of the memorizer of mobile terminal as claimed in claim 1 and processor, it is characterised in that
The step that the plurality of first pin set and the plurality of second pin set carry out matching is included:
First pin set and the second pin set with same sequence number are matched.
3. the method for attachment of the memorizer of mobile terminal as claimed in claim 1 and processor, it is characterised in that
The step that the plurality of first pin set and the plurality of second pin set carry out matching is included:
First pin set and the second pin set with different sequence number are matched.
4. the method for attachment of the memorizer of mobile terminal as claimed in claim 1 and processor, it is characterised in that
The step that 8 the first data pin are at random connected with 8 the second data pin is included:
The cabling of the printed circuit board (PCB) installed with this processor according to this memorizer requires to be attached.
5. the memorizer of a mobile terminal and the attachment structure of processor, it is adaptable to synchronous dynamic random stores
Device, this attachment structure includes:
Memorizer, including multiple first data pin, every 8 the first data pin corresponding multiple first control
Pin；
Processor, including multiple second data pin, every 8 the second data pin corresponding multiple second control
Pin；
Wherein, the first data pin of this memorizer and the first control pin of correspondence thereof are divided into multiple by byte
First pin set, the second data pin of this processor and the second control pin of correspondence thereof are divided into many as byte
Individual second pin set；The plurality of first pin set and the plurality of second pin set form pairing respectively, and in shape
Becoming between the first pin set and second pin set of pairing, first controls pin and the second control pin one a pair
Should connect on ground, and 8 the first data pin are at random connected with 8 the second data pin.
6. the attachment structure of the memorizer of mobile terminal as claimed in claim 5 and processor, it is characterised in that
Carry out the first pin set of matching and the second pin set is respectively provided with same sequence number.
7. the attachment structure of the memorizer of mobile terminal as claimed in claim 5 and processor, it is characterised in that
The first pin set carrying out matching at least partly has different sequence number from the second pin set.
8. the attachment structure of the memorizer of mobile terminal as claimed in claim 5 and processor, this memorizer is
Single times of speed synchronous DRAM.
9. the attachment structure of the memorizer of mobile terminal as claimed in claim 5 and processor, this memorizer is
Double Data Rate synchronous DRAM.
10. the attachment structure of the memorizer of mobile terminal as claimed in claim 5 and processor, this memorizer
First data pin is 16,32 or 64, and the second data pin of this processor is 16,32
Or 64.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201210532216.3A CN103870407B (en) | 2012-12-11 | 2012-12-11 | The memorizer of mobile terminal and the method for attachment of processor and attachment structure |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201210532216.3A CN103870407B (en) | 2012-12-11 | 2012-12-11 | The memorizer of mobile terminal and the method for attachment of processor and attachment structure |
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| CN103870407A CN103870407A (en) | 2014-06-18 |
| CN103870407B true CN103870407B (en) | 2016-12-21 |
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| CN113987991B (en) * | 2021-09-29 | 2022-09-27 | 展讯半导体(南京)有限公司 | Signal transmission device and electronic equipment |
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| US6904484B1 (en) * | 2000-03-30 | 2005-06-07 | Intel Corporation | Low pin count (LPC) firmware hub recovery |
| US7493467B2 (en) * | 2005-12-16 | 2009-02-17 | Intel Corporation | Address scrambling to simplify memory controller's address output multiplexer |
| CN101452494A (en) * | 2007-11-29 | 2009-06-10 | 中国科学院半导体研究所 | Type automatic allocation method for multi-packaged FPGA chip input-output module |
| US8291147B2 (en) * | 2010-02-08 | 2012-10-16 | Hon Hai Precision Industry Co., Ltd. | Computer motherboard with adjustable connection between central processing unit and peripheral interfaces |
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2012
- 2012-12-11 CN CN201210532216.3A patent/CN103870407B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6904484B1 (en) * | 2000-03-30 | 2005-06-07 | Intel Corporation | Low pin count (LPC) firmware hub recovery |
| US7493467B2 (en) * | 2005-12-16 | 2009-02-17 | Intel Corporation | Address scrambling to simplify memory controller's address output multiplexer |
| CN101452494A (en) * | 2007-11-29 | 2009-06-10 | 中国科学院半导体研究所 | Type automatic allocation method for multi-packaged FPGA chip input-output module |
| US8291147B2 (en) * | 2010-02-08 | 2012-10-16 | Hon Hai Precision Industry Co., Ltd. | Computer motherboard with adjustable connection between central processing unit and peripheral interfaces |
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Effective date of registration: 20170421 Address after: 201206 China (Shanghai) free trade zone, the moon Road, No. 3, building fourth, room B412, level 1258 Patentee after: Shanghai Li Ke Semiconductor Technology Co., Ltd. Address before: 201206 Pudong New Area Mingyue Road, Shanghai, No. 1258 Patentee before: Leadcore Technology Co., Ltd. |
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Address after: 1 / F, 6 / F, 7 / F, building 2, 1761 Zhangdong Road, China (Shanghai) pilot Free Trade Zone, 201203 Patentee after: Shanghai Li Ke Semiconductor Technology Co.,Ltd. Address before: Room b412, 4th floor, building 3, 1258 Mingyue Road, China (Shanghai) pilot Free Trade Zone Patentee before: Shanghai Li Ke Semiconductor Technology Co.,Ltd. |