CN103871857B - The forming method of semiconductor devices - Google Patents
The forming method of semiconductor devices Download PDFInfo
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- CN103871857B CN103871857B CN201210553295.6A CN201210553295A CN103871857B CN 103871857 B CN103871857 B CN 103871857B CN 201210553295 A CN201210553295 A CN 201210553295A CN 103871857 B CN103871857 B CN 103871857B
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- 238000000034 method Methods 0.000 title claims abstract description 58
- 239000004065 semiconductor Substances 0.000 title claims abstract description 50
- 239000010410 layer Substances 0.000 claims abstract description 101
- 239000011229 interlayer Substances 0.000 claims abstract description 37
- 239000000758 substrate Substances 0.000 claims abstract description 29
- 239000004020 conductor Substances 0.000 claims abstract description 23
- 238000001312 dry etching Methods 0.000 claims description 16
- 229920000642 polymer Polymers 0.000 claims description 13
- 230000015572 biosynthetic process Effects 0.000 claims description 11
- 239000000463 material Substances 0.000 claims description 11
- 238000005530 etching Methods 0.000 claims description 9
- 238000001039 wet etching Methods 0.000 claims description 8
- 229910052737 gold Inorganic materials 0.000 claims description 5
- 239000010936 titanium Substances 0.000 claims description 5
- 229910052719 titanium Inorganic materials 0.000 claims description 5
- 229910004200 TaSiN Inorganic materials 0.000 claims description 4
- 229910052802 copper Inorganic materials 0.000 claims description 4
- 229910052759 nickel Inorganic materials 0.000 claims description 4
- 229910052697 platinum Inorganic materials 0.000 claims description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
- 229920005591 polysilicon Polymers 0.000 claims description 4
- 229910052709 silver Inorganic materials 0.000 claims description 4
- 229910052718 tin Inorganic materials 0.000 claims description 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 4
- 229910052721 tungsten Inorganic materials 0.000 claims description 4
- 239000010937 tungsten Substances 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- 229910003481 amorphous carbon Inorganic materials 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 229910004166 TaN Inorganic materials 0.000 claims description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 2
- 229910052782 aluminium Inorganic materials 0.000 claims description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims 1
- 229910052751 metal Inorganic materials 0.000 description 27
- 239000002184 metal Substances 0.000 description 27
- 238000005516 engineering process Methods 0.000 description 10
- 229920002120 photoresistant polymer Polymers 0.000 description 9
- SECXISVLQFMRJM-UHFFFAOYSA-N N-Methylpyrrolidone Chemical group CN1CCCC1=O SECXISVLQFMRJM-UHFFFAOYSA-N 0.000 description 4
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 4
- 239000007789 gas Substances 0.000 description 4
- 239000010931 gold Substances 0.000 description 4
- 238000006243 chemical reaction Methods 0.000 description 3
- 150000001875 compounds Chemical class 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
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- 239000002904 solvent Substances 0.000 description 3
- 150000005846 sugar alcohols Polymers 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
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- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
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- 238000000137 annealing Methods 0.000 description 1
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- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
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- 238000007254 oxidation reaction Methods 0.000 description 1
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- 238000005498 polishing Methods 0.000 description 1
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- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823857—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
Abstract
A kind of forming method of semiconductor devices, including：Semiconductor substrate is provided, along grid line direction, the first dummy grid spaced apart from each other and the second dummy grid are formed with the semiconductor substrate；Interlayer dielectric layer is formed on the semiconductor substrate；Formed after the interlayer dielectric layer, remove first dummy grid, form the first pseudo- gate groove, first grid is formed in the first pseudo- gate groove；Formed after the first grid, remove second dummy grid, form the second pseudo- gate groove, second grid is formed in the second pseudo- gate groove；The part or all of interlayer dielectric layer between the first grid and second grid is removed, the groove of connection first grid and second grid is formed；Conductive materials are filled in the groove, first grid and second grid are electrically connected.Using technical scheme, the transistor AND gate with first grid there is the transistor of second grid can realize cooperate more stable, more sensitively, improve the performance of semiconductor devices.
Description
Technical field
The present invention relates to technical field of semiconductors, more particularly to a kind of forming method of semiconductor devices.
Background technology
In the prior art, " rear grid（Gate last) " technique is the main technique to form metal gates.This skill
The characteristics of art, is re-formed after being completed to silicon chip progress drain source ion implanting operation and subsequent high-temperature annealing step
Metal gates.
In the prior art, that deposits that grid technique after application makes that PMOS transistor and nmos pass transistor cooperate is integrated
Circuit.Wherein, PMOS transistor adjacent in some integrated circuits, nmos pass transistor metal gates are in grid line direction（Vertical source
Pole and drain electrode line direction）Contact with each other, i.e., the mutual of two metal gates is realized by the contact of two adjacent metal grids
Electrical connection.In rear grid technique, the contact quality between the metal gates of PMOS transistor and adjacent NMOS metal gates,
It is to influence one of key factor of performance of semiconductor device.It is brilliant with NMOS that PMOS transistor metal gates are formed in the prior art
Body pipe metal gate processes are：Reference picture 1 is formed with the first metal gate over the semiconductor substrate 10 there is provided Semiconductor substrate 10
Pole 11, the pseudo- grid 12 adjacent with the first metal gates 11, interlayer dielectric layer 13.Reference picture 2, forms patterned photoresist layer
14, exposure puppet grid 12.It is mask with patterned photoresist layer 14 with continued reference to Fig. 3, dry etching removes pseudo- grid 12, formed
Pseudo- gate groove 121, afterwards, wet etching remove the pseudo- side wall of gate groove 121 and the polymer of bottom.Finally, reference picture 4, are removed
Patterned photoresist layer 14, forms the second metal gates 15 in pseudo- gate groove 121.Wherein, the correspondence of the first metal gates 11
The metal gates of PMOS transistor, the metal gates of the second metal gates 15 correspondence nmos pass transistor, or conversely.
But, there are two metal gates that contact with each other on grid line direction using what the rear grid technique of prior art made
Semiconductor devices performance it is not good.
More knowledge on rear grid technique, refer to disclosed in 4 days Mays in 2011, Patent No. CN102044421A
Chinese patent literature.
The content of the invention
The problem of present invention is solved is that the performance of the semiconductor devices of the rear grid technique formation of prior art is not good.
To solve the above problems, the present invention provides a kind of forming method of new semiconductor devices, including：
Semiconductor substrate is provided, along grid line direction, the spaced apart from each other first pseudo- grid are formed with the semiconductor substrate
Pole and the second dummy grid；
Interlayer dielectric layer is formed on the semiconductor substrate；
Formed after the interlayer dielectric layer, remove first dummy grid, form the first pseudo- gate groove, in the first pseudo- grid ditch
First grid is formed in groove；
Formed after the first grid, remove second dummy grid, form the second pseudo- gate groove, in the second pseudo- gate groove
Middle formation second grid；
The part or all of interlayer dielectric layer between the first grid and second grid is removed, connection first grid is formed
With the groove of second grid；
Conductive materials are filled in the groove, first grid and second grid are electrically connected.
Optionally, the method for forming the first dummy grid and the second dummy grid, including：
Dummy gate layer is formed on a semiconductor substrate；
The graphical dummy gate layer, forms dummy grid；
The dummy grid is divided into the first dummy grid spaced apart from each other, the second dummy grid.
Optionally, the method for forming the groove of connection first grid and second grid, including：
Patterned mask layer is formed on the interlayer dielectric layer, first grid and second grid, is defined to be formed
The position of groove；
Using the patterned mask layer as mask, etched portions or whole interlayer dielectric layers form connection first grid
With the groove of second grid；
Remove patterned mask layer.
Optionally, after the first dummy grid and the second dummy grid is formed, formed before interlayer dielectric layer, in addition to：
Ion implanting is carried out in the Semiconductor substrate of the first dummy grid both sides, the first source region and the first drain region is formed；
Ion implanting is carried out in the Semiconductor substrate of the second dummy grid both sides, the second source region and the second drain region is formed, its
In, the first source region and the first drain region are different from the type of the second source region and the second drain region.
Optionally, the ion injected in the first source region and the first drain region is to note in N-type ion, the second source region and the second drain region
The ion entered is p-type ion.
Optionally, the method for removing the first dummy grid, including：
Patterned mask layer is formed, the position of the first dummy grid is defined；
Using the patterned mask layer as mask, the first dummy grid is removed using dry etching；
The polymer formed in the dry etching is removed using wet etching；
Remove patterned mask layer.
Optionally, the method for removing the second dummy grid, including：
Patterned mask layer is formed, the position of the second dummy grid is defined；
Using patterned mask layer as mask, the second dummy grid is removed using dry etching；
The polymer formed in the dry etching is removed using wet etching；
Remove patterned mask layer.
Optionally, before patterned mask layer is formed, form titanium nitride layer, covering interlayer dielectric layer, first grid,
Second dummy grid.
Optionally, the first dummy grid or the second dummy grid are removed using dry etching, the etching gas used include O2。
Optionally, the etching gas used also include NF3, HBr or CF4In one or more.
Optionally, the part or all of interlayer dielectric layer formation groove between the first grid and second grid is removed
When, also remove the first grid, second grid the side wall adjacent with groove.
Optionally, the conductive materials are tungsten.
Optionally, the material of first dummy grid and the second dummy grid includes polysilicon, silicon nitride or amorphous carbon.
Optionally, the material of the first grid and second grid includes：Al、Cu、Ag、Au、Pt、Ni、Ti、TiN、TaN、
Ta, TaC, TaSiN, W, WN, WSi one or more.
Compared with prior art, the present invention has advantages below：
First grid and the process of second grid that the present invention is connected with each other using the formation of rear grid technique on grid line direction
In, it is initially formed the first dummy grid spaced apart from each other and the second dummy grid.Afterwards, interlayer dielectric layer is formed on substrate.Then,
The first dummy grid and the second dummy grid are removed, first grid and second grid is formed.After first grid and second grid is formed,
The part or all of interlayer dielectric layer between first grid and second grid is removed, groove is formed.Then, filling is led in a groove
Isoelectric substance, first grid and second grid are electrically connected.Conductive materials in groove directly connect first grid with second grid
Pick up and, first grid realizes accessible close contact with second grid.So, the signal between first grid and second grid
Transmission is stable, sensitive so that it is more stable, more that there is the transistor AND gate with first grid the transistor of second grid can realize
Sensitively cooperate, improve the performance of semiconductor devices.In addition, in advance separate the first dummy grid and the second dummy grid,
It is not only to be subsequently formed groove to create conditions, causes during the first dummy grid or the second dummy grid is removed yet, will not be right
Adjacent dummy grid or grid is impacted.Such as, during the second dummy grid is removed, especially wet etching removes residual and gathered
During compound, corrosive agent will not produce corrosion to first grid, it is ensured that first grid is complete, also stabilizes the property of transistor
Energy.
Brief description of the drawings
Fig. 1~Fig. 4 is section knot of the method for the rear grid technique formation semiconductor devices of prior art on grid line direction
Structure schematic diagram；
Fig. 5 is the method flow schematic diagram of the formation semiconductor devices of the specific embodiment of the invention；
Fig. 6 a, Fig. 6 b~Figure 11 a, 11b are the method structural representations of the formation semiconductor devices of the specific embodiment of the invention
Figure.
Embodiment
The problem of inventor exists for the rear grid technique of prior art, is studied, and is found：Using dry etching
Remove in dummy grid, polymer can be generated, bottom and the side wall of pseudo- gate groove is attached to.For example in dry etch process, generally
Oxygen is passed through to etching reaction intracavitary, partial oxidation can react with other materials of polysilicon or etching reaction intracavitary, it is raw
Into oxide, oxide can be considered a kind of composition of polymer.Although, it is follow-up to remove polymer using wet etching, it is existing
It is 1-METHYLPYRROLIDONE to have corrosive agent usually used in technology（NMP, N-methyl-2-pyrrolidone）Solvent or EKC
Solvent (a kind of alkaline solution provided by EKC Technology Inc of Du Pont), the ability of the corrosion of the solvent is weaker, most poly-
Compound will not be removed.This can produce following problem：Reference picture 3, in the not removed polymer of the side-walls of pseudo- gate groove 121
It is attached on the first metal gates 11.So, in the interface of the first metal gates 11 and the second metal gates 15, populated with is residual
The polymer stayed, produces negative influence so that adjacent to the electrical connection between the first metal gates 11 and the second metal gates 15
Transmission jitter between transistor, reduces the performance of semiconductor devices.If in the first metal gates 11 and the second gold medal
If the residual polyalcohol of the interface of category grid 15 is thicker, it can make that between adjacent transistor signal can not be transmitted so that partly lead
Body device can not work, and have a strong impact on the performance of semiconductor devices.
Inventor is in view of the above-mentioned problems, by creative work, obtain a kind of forming method of new semiconductor devices.
In order to facilitate the understanding of the purposes, features and advantages of the present invention, below in conjunction with the accompanying drawings to the present invention
Embodiment be described in detail.Many details are elaborated in the following description to fully understand this hair
It is bright.But the present invention can be implemented with being much different from other modes described here, those skilled in the art can be not
Similar popularization is done in the case of running counter to intension of the present invention, therefore the present invention is not limited by following public specific embodiment.
Fig. 6 a, Fig. 6 b~Figure 11 a, Figure 11 b show for the method structure of the formation semiconductor devices of the specific embodiment of the invention
It is intended to, wherein, Fig. 6 a~Figure 11 a are the structure top view of the formation semiconductor devices method of the specific embodiment of the invention, Fig. 6 b
~Figure 11 b are cross-sectional view of the formation semiconductor devices method of the specific embodiment of the invention along grid line direction.
Reference picture 6a, Fig. 6 b, and reference picture 5 is combined, step S51 is performed there is provided Semiconductor substrate 300, along grid line direction
（Vertical source electrode is to drain directions）, the dummy grid of the first dummy grid 311 and second spaced apart from each other is formed in Semiconductor substrate 300
321.That is, there is space in grid line direction between the first dummy grid 311 and the second dummy grid 321, space side wall is used as
The surface of the first dummy grid 311, the second dummy grid 321 surface it is relative.
In a particular embodiment, the material of the Semiconductor substrate 300 can be monocrystalline silicon, monocrystalline germanium or single-crystal silicon Germanium；
It can also be silicon-on-insulator（SOI）；Or other materials, III-V compounds of group such as GaAs can also be included.
Device architecture (not shown) is formed with the Semiconductor substrate 300, the isolation structure such as isolation trench structure is used for phase
Isolation between adjacent transistor.
In a particular embodiment, the pseudo- grid of the first dummy grid 311 and second spaced apart from each other are formed in Semiconductor substrate 300
The method of pole 321, including：Dummy gate layer is formed in Semiconductor substrate 300（It is not shown）, the material of the dummy gate layer can be with
Polysilicon, amorphous carbon or silicon nitride are selected, the method for forming dummy gate layer can be chemical vapor deposition；The graphical puppet
Grid layer, forms dummy grid；The dummy grid is divided into the dummy grid 321 of the first dummy grid 311 and second spaced apart from each other.Its
In, it is by the method that the dummy grid is divided into the dummy grid 321 of the first dummy grid 311 and second spaced apart from each other：Form figure
The photoresist layer of change, the dummy grid part between definition the first dummy grid 311 to be formed and the second dummy grid 321；With described
Patterned photoresist layer is mask, and etching dummy grid to semiconductor substrate surface stops；Remove patterned photoresist layer, shape
Into the dummy grid 321 of the first dummy grid 311 and second spaced apart from each other.
Step S51 is performed, the first dummy grid 311 and the second dummy grid 321 are separated, can make it that follow-up removal second is pseudo-
During grid 321, the polymer produced using dry etching without being adhered on adjacent first grid.Moreover, in rear extended meeting weight
The new opening by between first grid and second grid is filled so that adjacent transistor is connected.
Reference picture 7a and Fig. 7 b, with reference to reference picture 5, performs step S52, inter-level dielectric is formed in Semiconductor substrate 300
Layer 302.If being formed without hard mask layer on the first dummy grid 311 and the second dummy grid 321, interlayer dielectric layer 302 it is upper
Surface and the upper surface of the first dummy grid 311, the second dummy grid 321 maintain an equal level；If the first dummy grid 311 and the second dummy grid 321
Hard mask layer is respectively formed on, then the upper surface of interlayer dielectric layer 302 and the upper surface of hard mask layer maintain an equal level.Because Fig. 7 a are top
View, Semiconductor substrate is not visible, therefore not shown.
In a particular embodiment, the material of interlayer dielectric layer 302 generally selects silica, also has other can selection certainly
Material, can be selected according to actual needs.The step of forming interlayer dielectric layer 302, is usually first to deposit, then planarized
Processing, for example, chemically-mechanicapolish polish or return and carve.
In specific production, after the first dummy grid and the second dummy grid is formed, before interlayer dielectric layer is formed, the
Ion implanting is carried out in the Semiconductor substrate of one dummy grid both sides, the first source region and the firstth drain region is formed；Afterwards, it is pseudo- second
Ion implanting is carried out in the Semiconductor substrate of grid both sides, the second source region and the second drain region is formed.Wherein, the first source region and first
Drain region, it is different from the ionic type injected in the second source region and the second drain region.If injected in the first source region and the first drain region from
Son is N-type ion, the source electrode and drain electrode of the first source region and the first drain region as P-type transistor, then correspondingly, the second source region and the
The ion injected in two drain regions is p-type ion, the source electrode and drain electrode of the second source region and the second drain region as N-type transistor.Conversely,
If the ion injected in the first source region and the first drain region is p-type ion, the ion injected in the second source region and the second drain region is N
Type ion.
Reference picture 8a, Fig. 8 b, and reference picture 5 is combined, step S53 is performed, is formed after interlayer dielectric layer 302, first is removed
Dummy grid 311, forms the first pseudo- gate groove（It is not shown）, first grid 311' is formed in the first pseudo- gate groove.According to first
The selection for the conductive material filled in pseudo- gate groove, such as conductive material are metal, then first grid 311' is metal gates.At this
In embodiment, before forming first grid 311' in the first pseudo- gate groove, high K dielectric is formed in the bottom of the first pseudo- gate groove
Layer, as gate dielectric layer, forms first grid 311' on gate dielectric layer afterwards.Concrete technology is known technology, is repeated no more.
In a particular embodiment, the method for forming the first pseudo- gate groove, including：（1）Patterned mask layer is formed, is defined
The position of first pseudo- gate groove, the second dummy grid 321 is covered.Wherein, patterned mask layer generally selects photoresist.（2）
Using patterned mask as mask layer, the first dummy grid 311 is removed using dry etching, the is formed in interlayer dielectric layer 302
One pseudo- gate groove（It is not shown）.In dry etch process, the gas being passed through in etching reaction intracavitary is O2, but it is not limited to O2, also
It may include NF3, HBr or CF4In one or more.In the present embodiment, the gas being passed through is O2, O2Etching can be replenished
During first dummy grid 311, the first pseudo- gate trench sidewall（That is inter-level dielectric layer segment）In oxygen loss.（3）Use wet method
The polymer produced during the above-mentioned dry etching of erosion removal, side wall and bottom of the polymer residue in the first pseudo- gate groove
Portion.（4）Remove patterned mask layer.
In a particular embodiment, formed after the first pseudo- gate groove, conductive material is filled in the first pseudo- gate groove, form the
One grid 311'.The conductive material used can be metal, including：Al、Cu、Ag、Au、Pt、Ni、Ti、TiN、TaN、Ta、TaC、
TaSiN, W, WN, WSi one or more.The technology that concrete technology is well known to those skilled in the art, will not be repeated here.
Reference picture 9a, Fig. 9 b, and Fig. 5 is combined, step S54 is performed, is formed after first grid 311', the second dummy grid is removed
321, form the second pseudo- gate groove（It is not shown）, second grid 321' is formed in the second pseudo- gate groove.In the present embodiment, exist
Formed in second pseudo- gate groove before second grid 321', form high-K dielectric layer in the bottom of the second pseudo- gate groove, be situated between as grid
Matter layer, afterwards, forms second grid 321' in high-K dielectric layer.
In a particular embodiment, the step of the step of forming the second pseudo- gate groove is with being previously formed the first pseudo- gate groove phase
Together, including photoetching, dry etching, wet etching process step.Optionally, in a photolithographic process, patterned mask layer is formed
Before, titanium nitride layer, covering first grid, the second dummy grid and interlayer dielectric layer are formed.Afterwards, figure is formed on titanium nitride layer
The mask layer of shape, is typically chosen photoresist layer.Titanium nitride layer can play a part of protecting first grid, it is to avoid form figure
During the mask layer of change, especially patterned photoresist layer, to the conductive material of first grid, such as metal causes to damage
Wound.In this step, other concrete technology conditions refer to the explanation for performing step S53.
In a particular embodiment, second grid 321' material include Al, Cu, Ag, Au, Pt, Ni, Ti, TiN, TaN, Ta,
TaC, TaSiN, W, WN, WSi one or more.
Reference picture 10a, Figure 10 b, and reference picture 5 is combined, step S55 is performed, first grid 311' and second grid is removed
Part or all of interlayer dielectric layer between 321', forms connection first grid 311' and second grid 321' groove 303.It is recessed
Groove 303 is used for the interconnection line that is formed between first grid 311' and second grid 321', and then forms first grid 311 ' and the
Two grid 321' electrical connection.
In a particular embodiment, figure is formed first on interlayer dielectric layer 302 and first grid 311', second grid 321'
The mask layer of shape, defines the position of groove 303 to be formed；Then, using patterned mask layer as mask, interlayer is etched
Dielectric layer 302, forms groove 303；Finally, patterned mask layer is removed.To the depth and width of groove 303, however it is not limited to
The inter-level dielectric layer segment between first grid 311' and second grid 321' being removed entirely shown in Figure 10 a, Figure 10 b.
All it is feasible as long as first grid 311' is connected with second grid 321' in other embodiment.For example, removing the
Partial depth between one grid 311 ' and second grid 321', on grid length direction partial width interlayer dielectric layer, and
First grid 311' is connected with second grid 321' on grid line direction.As long as other meet the present invention by first grid and the
The definition of two grids connection, just within protection scope of the present invention.
In a particular embodiment, first grid 311' and second grid can also removed during groove 303 is formed
During part or all of interlayer dielectric layer 302 between 321', the first grid, second grid and groove 303 are also removed adjacent
Side wall so that the residual polyalcohol of the side wall of groove 303 is substantially removed.So, first grid 311' and second grid 321'
The residual polyalcohol of side wall can be removed completely substantially.The conductive materials then formed in successive recesses can be with first grid
311', second grid 321' form accessible contact.
Reference picture 10a, Figure 10 b and 11a, Figure 11 b, and reference picture 5 is combined, step S56 is performed, is filled in groove 303
Conductive materials 304, first grid 311' and second grid 321' is electrically connected.
In a particular embodiment, the method that conductive materials are filled in groove 303, including：Deposit conductive materials, coating
Between dielectric layer 302, first grid 311' and second grid 321', and fill groove 303, the method for deposition conductive materials can make
With physical vapour deposition (PVD), chemical vapor deposition or sputtering technology；The conductive materials for being higher by the surface of interlayer dielectric layer 302 are removed, are remained
Conductive materials 304 in remaining groove 303.In the present embodiment, the conductive materials filled in groove 303 are tungsten（W）, but do not limit
It is also feasible to other conductive materials in tungsten.It is described to remove the conductive materials for being higher by the surface of interlayer dielectric layer 302, use change
Learn mechanical polishing or return carving technology.
Perform after this step, the conductive materials 304 in groove 303 directly connect first grid 311 ' with second grid 321'
Pick up and, first grid 311 ' and second grid 321' realizes accessible close contact.So, first grid 311' and second gate
Signal transmission between the 321' of pole is stable, sensitive so that the transistor AND gate with first grid 311' has second grid 321'
Transistor can realize and cooperate more stable, more sensitively, improve the performance of semiconductor devices.
Although the present invention is disclosed as above with preferred embodiment, it is not for limiting the present invention, any this area
Technical staff without departing from the spirit and scope of the present invention, may be by the methods and techniques content of the disclosure above to this hair
Bright technical scheme makes possible variation and modification, therefore, every content without departing from technical solution of the present invention, according to the present invention
Any simple modifications, equivalents, and modifications made to above example of technical spirit, belong to technical solution of the present invention
Protection domain.
Claims (13)
1. a kind of forming method of semiconductor devices, it is characterised in that including：
There is provided Semiconductor substrate, along grid line direction, be formed with the semiconductor substrate the first dummy grid spaced apart from each other and
Second dummy grid；
Interlayer dielectric layer is formed on the semiconductor substrate；
Formed after the interlayer dielectric layer, remove first dummy grid, form the first pseudo- gate groove, in the first pseudo- gate groove
First grid is formed, wherein, the method for removing the first dummy grid, including：Patterned mask layer is formed, the first dummy grid is defined
Position；Using the patterned mask layer as mask, the first dummy grid is removed using dry etching；Removed using wet etching
The polymer formed in the dry etching；Remove patterned mask layer；
Formed after the first grid, remove second dummy grid, form the second pseudo- gate groove, the shape in the second pseudo- gate groove
Into second grid；
Remove the part or all of interlayer dielectric layer between the first grid and second grid, form connection first grid and the
The groove of two grids；
Conductive materials are filled in the groove, the conductive materials directly contact electrical connection with first grid and second grid.
2. forming method as claimed in claim 1, it is characterised in that the method for forming the first dummy grid and the second dummy grid,
Including：
Dummy gate layer is formed on a semiconductor substrate；
The graphical dummy gate layer, forms dummy grid；
The dummy grid is divided into the first dummy grid spaced apart from each other, the second dummy grid.
3. forming method as claimed in claim 1, it is characterised in that form the groove of connection first grid and second grid
Method, including：
Patterned mask layer is formed on the interlayer dielectric layer, first grid and second grid, groove to be formed is defined
Position；
Using the patterned mask layer as mask, etched portions or whole interlayer dielectric layer form connection first grid and the
The groove of two grids；
Remove patterned mask layer.
4. forming method as claimed in claim 1, it is characterised in that after the first dummy grid and the second dummy grid is formed, shape
Into before interlayer dielectric layer, in addition to：
Ion implanting is carried out in the Semiconductor substrate of the first dummy grid both sides, the first source region and the first drain region is formed；
Ion implanting is carried out in the Semiconductor substrate of the second dummy grid both sides, the second source region and the second drain region is formed, wherein, the
One source region and the first drain region are different from the type of the second source region and the second drain region.
5. forming method as claimed in claim 4, it is characterised in that the ion injected in the first source region and the first drain region is N
The ion injected in type ion, the second source region and the second drain region is p-type ion.
6. forming method as claimed in claim 1, it is characterised in that the method for removing the second dummy grid, including：
Patterned mask layer is formed, the position of the second dummy grid is defined；
Using patterned mask layer as mask, the second dummy grid is removed using dry etching；
The polymer formed in the dry etching is removed using wet etching；
Remove patterned mask layer.
7. forming method as claimed in claim 6, it is characterised in that before patterned mask layer is formed, forms nitridation
Titanium layer, covering interlayer dielectric layer, first grid, the second dummy grid.
8. the forming method as described in claim 5 or 6, it is characterised in that remove the first dummy grid or the using dry etching
Two dummy grids, the etching gas used include O2。
9. forming method as claimed in claim 8, it is characterised in that the etching gas used also include NF3, HBr or CF4In
One or more.
10. forming method as claimed in claim 1, it is characterised in that remove between the first grid and second grid
During part or all of interlayer dielectric layer formation groove, the first grid, second grid the side wall adjacent with groove are also removed.
11. forming method as claimed in claim 1, it is characterised in that the conductive materials are tungsten.
12. forming method as claimed in claim 1, it is characterised in that the material of first dummy grid and the second dummy grid
Including polysilicon, silicon nitride or amorphous carbon.
13. forming method as claimed in claim 1, it is characterised in that the material of the first grid and second grid includes：
Al, Cu, Ag, Au, Pt, Ni, Ti, TiN, TaN, Ta, TaC, TaSiN, W, WN, WSi one or more.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US6171910B1 (en) * | 1999-07-21 | 2001-01-09 | Motorola Inc. | Method for forming a semiconductor device |
| CN102640291A (en) * | 2009-12-30 | 2012-08-15 | 英特尔公司 | Self-aligned contacts |
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| CN102479716B (en) * | 2010-11-29 | 2015-03-11 | 中芯国际集成电路制造(北京)有限公司 | Manufacturing method of transistor |
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| US6171910B1 (en) * | 1999-07-21 | 2001-01-09 | Motorola Inc. | Method for forming a semiconductor device |
| CN102640291A (en) * | 2009-12-30 | 2012-08-15 | 英特尔公司 | Self-aligned contacts |
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