CN103904050A - 封装基板、封装基板制作方法及封装结构 - Google Patents

封装基板、封装基板制作方法及封装结构 Download PDF

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Publication number
CN103904050A
CN103904050A CN201210582244.6A CN201210582244A CN103904050A CN 103904050 A CN103904050 A CN 103904050A CN 201210582244 A CN201210582244 A CN 201210582244A CN 103904050 A CN103904050 A CN 103904050A
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Prior art keywords
conductive
conductive pole
packaging
circuit pattern
electrodeposited coating
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CN201210582244.6A
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CN103904050B (zh
Inventor
禹龙夏
周鄂东
罗文伦
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Liding Semiconductor Technology Qinhuangdao Co ltd
Zhen Ding Technology Co Ltd
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Hongqisheng Precision Electronics Qinhuangdao Co Ltd
Zhending Technology Co Ltd
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Application filed by Hongqisheng Precision Electronics Qinhuangdao Co Ltd, Zhending Technology Co Ltd filed Critical Hongqisheng Precision Electronics Qinhuangdao Co Ltd
Priority to CN201210582244.6A priority Critical patent/CN103904050B/zh
Priority to TW102102540A priority patent/TW201436132A/zh
Priority to US14/097,251 priority patent/US9173298B2/en
Publication of CN103904050A publication Critical patent/CN103904050A/zh
Priority to US14/848,504 priority patent/US20150380391A1/en
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Abstract

一种封装基板，其包括电路基板、多个第一导电柱及多个第二导电柱，所述电路基板具有第一基底及形成于第一基底一个表面的第一导电线路图形，所述第一导电柱及第二导电柱均与第一导电线路图形相互电连接，并自第一导电线路图形向远离第一导电线路图形的方向延伸，所述第二导电柱的高度大于所述第一导电柱的高度。本发明还提供所述封装基板的制作方法及包括所述封装基板的封装结构。

Description

封装基板、封装基板制作方法及封装结构
技术领域
本发明涉及一种半导体封装技术，特别涉及一种封装基板、封装基板制作方法及封装结构。
背景技术
随着半导体器件尺寸的不断减小，具有半导体器件的层叠封装结构也逐渐地备受关注。层叠封装结构一般通过层叠制作方法制成，即在封装基板上中心部位通过较小的焊球封装一个芯片，然后再采用较大的焊球与连接基板相互结合，所述的连接基板上结合有另外的芯片，从而得到层叠封装结构。由于仅采用焊球实现封装基板与芯片及连接基板之间的电连接，容易由于焊球与封装基板、连接基板及芯片的连接处产生裂缝，从而导致得到的层叠封装结构的品质较差。
发明内容
因此，有必要提供一种封装基板及其制作方法、封装结构，以克服上述不足。
一种封装基板，其包括电路基板、多个第一导电柱及多个第二导电柱，所述电路基板具有第一基底及形成于第一基底一个表面的第一导电线路图形，所述第一导电柱及第二导电柱均与第一导电线路图形相互电连接，并自第一导电线路图形向远离第一导电线路图形的方向延伸，所述第二导电柱的高度大于所述第一导电柱的高度。
一种封装基板的制作方法，包括步骤：提供一电路基板，所述电路基板包括第一基底、形成于第一基底一侧表面的第一导电线路图形以及形成于第一导电线路图形表面的第一防焊层，所述第一防焊层具有多个第一开口和第二开口，部分所述第一导电线路图形从所述第一开口和第二开口露出；在第一防焊层的表面形成金属种子层；在所述金属种子层的表面形成第一电镀层；在所述第一电镀层的表面形成第二电镀阻挡图形，所述第二电镀阻挡图形内有与所述第一开口相对应的第一开孔；在从所述第一开孔露出的第一电镀层的表面形成第一蚀刻阻挡图形；去除所述第二电镀阻挡图形；在第一电镀层及蚀刻阻挡图形的表面形成第二电镀层；在第二电镀层的表面形成第二蚀刻阻挡图形，所述第二蚀刻阻挡图形与第二开口相对应；以及对第一电镀层和第二电镀层进行蚀刻，使得被第二蚀刻阻挡图形覆盖的部分第一电镀层和第二电镀层形成与第二开口相对应的第二导电柱，使得被第一阻挡图形覆盖的部分第一电镀铜层形成与第一开口相对应的第一导电柱。
一种封装结构，包括第一封装体和封装于第一封装体的第二封装体，所述第一封装体包括第一芯片和所述的封装基板，所述第一芯片具有与第一导电柱一一对应的多个第一电极垫，所述第一电极垫与第一导电柱通过第一焊球相互电导通，所述第二封装体包括连接基板及封装于连接基板的第二芯片，所述连接基板具有与第二导电柱相对应的电性接触垫，所述第二导电柱与对应的电性接触垫通过第二焊球相互电导通。
本技术方案提供的封装基板及其制作方法，通过在形成第一电镀层之后，设置与欲形成的第一导电柱相对应的第一蚀刻阻挡图形，并在第一电镀层及第一蚀刻阻挡图形表面形成第二电镀层，然后，采用一次性蚀刻即可得到高度不同的第一导电柱和第二导电柱。所述第一导电柱的高度可以通过控制第一电镀层的厚度进行控制，第二导电柱的高度可以通过第一电镀层和第二电镀层的厚度之和进行控制，工艺操作简单。
本技术方案中，由于封装基板的第一导电柱的高度小于第二导电柱的高度，在进行封装时，第一芯片通过第一导电柱封装于封装基板，而第二封装体通过第二导电柱封装于封装基板。由于第一导电柱的高度与第二导电柱的高度不等，可以使得第一芯片厚度与第一导电柱的高度之和与第二导电柱的高度大致相等，从而可以减少封装结构的厚度，进而减小封装结构的体积。并且，由于封装基板与连接基板之间通过第二导电柱与第二焊球相结合的方式进行结合，第一芯片与封装基板之间通过第一导电柱与第一焊球相结合的方式进行结合，相比于现有技术中仅采用焊球进行封装，能够提升封装结构的品质。
附图说明
图1至图12为本技术方案第一实施例提供的封装基板制作过程的剖面示意图。
图13至图16为本技术方案第二实施例提供的封装基板制作过程的剖面示意图。
图17为本技术方案提供的封装结构的剖面示意图。
主要元件符号说明
封装结构 10
封装基板 100a，100b
第一基底 111
第一表面 1111
第二表面 1112
第一导电线路图形 112
第二导电线路图形 113
第一防焊层 114
第一开口 1141
第二开口 1142
第二防焊层 115
第三开口 1151
金属种子层 120
第一电镀阻挡图形 130
第一电镀层 140
第二电镀阻挡图形 150
第一开孔 151
第一蚀刻阻挡图形 160
第二电镀层 170
第二蚀刻阻挡图形 180
第一导电柱 191
第二导电柱 192
焊帽 193
光致抗蚀剂层 171
第二开孔 172
第三开孔 131
保护层 194
第一封装体 11
第二封装体 12
第一芯片 200
第一电极垫 210
第一焊球 101
第一封装胶体 102
第二焊球 103
第二封装胶体 104
第三封装胶体 105
第三焊球 106
连接基板 300
第二基底 310
第一电性接触垫 320
第二电性接触垫 330
第一导电孔 340
第三防焊层 350
第四防焊层 360
第二芯片 400
第二电极垫 410
键合导线 420
如下具体实施方式将结合上述附图进一步说明本发明。
具体实施方式
下面将结合附图及实施例，对本技术方案提供的封装结构及其制作方法作进一步的详细说明。
本技术方案第一实施例提供一种封装基板的制作方法，所述封装基板的制作方法包括步骤:
请参阅图1，第一步，提供一电路基板110。
电路基板110为形成有导电线路并两侧均形成有防焊层的电路基板。电路基板110可以为多层电路板。电路基板110包括第一基底111、第一导电线路图形112、第二导电线路图形113、第一防焊层114及第二防焊层115。
本实施例中，第一基底111为多层基板，包括交替排列的多层树脂层与多层导电线路图形（图未示）。第一基底111包括相对的第一表面1111及第二表面1112，该第一导电线路图形112设置于该第一基底111的第一表面1111上，该第二导电线路图形113设置于该第一基底111的第二表面1112上。该第一基底111的多层导电线路图形之间及该第一基底111的多层导电线路图形与该第一导电线路图形112和第二导电线路图形113分别通过导电孔（图未示）电连接。
该第一防焊层114覆盖部分该第一导电线路图形112及从该第一导电线路图形112露出的第一表面1111，所述第一防焊层114内形成有多个第一开口1141及多个第二开口1142,多个第一开口1141位于第一防焊层114的中心区域，并阵列排布。第二开口1142环绕多个第一开口1141设置。第一开口1141的横截面积小于第二开口1142的横截面积。部分该第一导电线路图形112从该第一防焊层114的第一开口1141和第二开口1142露出。
该第二防焊层115覆盖部分该第二导电线路图形113及从该第二导电线路图形113露出的第二表面1112，所述第二防焊层115内形成有多个第三开口1151,使部分该第二导电线路图形113从该第二防焊层115露出。
第二步，请参阅图2，在第一防焊层114的表面形成金属种子层120。
本实施例中，可以通过溅镀金属铜的方式，在第一防焊层114的表面形成金属种子层120。可以理解的是，在进行溅镀的过程中，从第一防焊层114的空隙露出的第一导电线路图形112的表面也可以形成金属种子层120。
第三步，请参阅图3，在第二防焊层115表面及从第二防焊层115露出的第二导电线路图形113的表面形成第一电镀阻挡图形130。
本步骤中，可以采用印刷可剥胶等方式形成第一电镀阻挡图形130，使得第二防焊层115表面及从第二防焊层115露出的第二导电线路图形113的表面完全被第一电镀阻挡图形130覆盖。
第四步，请参阅图4，在所述金属种子层120的表面及第一导电线路图形112表面形成第一电镀层140。
第一电镀层140覆盖金属种子层120及从所述第一开口1141和第二开口1142露出的第一导电线路图形112的表面。
第五步，请参阅图5，在所述第一电镀层140的表面形成第二电镀阻挡图形150。
所述第二电镀阻挡图形150的中心区域具有多个第一开孔151，第一电镀层140从第一开孔151的底部露出。所述多个第一开孔151可以阵列排布，所述多个第一开孔151开设的位置应与欲形成的封装基板需要封装的芯片的电极垫的分布相互对应。每个第一开孔151均与一个第一开口1141相对应。所述第一开孔151可以在通过贴合干膜形成整片的电镀阻挡层后经过激光烧蚀形成。
第六步，请参阅图6，在从所述第一开孔151露出的第一电镀层140的表面形成第一蚀刻阻挡图形160。
本实施例中，采用电镀锡或镍的方式在从所述第一开孔151露出的第一电镀层140的表面形成第一蚀刻阻挡图形160。所述第一蚀刻阻挡图形160与第一开孔151相对应。因为，当对第一电镀层140进行蚀刻时，蚀刻铜的蚀刻液并不能与锡或镍发生反应，从而使得被锡或镍的第一电镀层140不被蚀刻。可以理解的是, 第一蚀刻阻挡图形160也可以采用其他在蚀刻第一电镀层140时不被蚀刻的金属制成。
第七步，请参阅图7，去除所述第二电镀阻挡图形150。
本步骤中，可以采用剥膜的方式，将所述第二电镀阻挡图形150去除。
第八步，请参阅图8，在第一电镀层140及第一蚀刻阻挡图形160的表面形成第二电镀层170。
本步骤还可以采用电镀铜的方式形成第二电镀层170。第二电镀层170的厚度大于所述第一蚀刻阻挡图形160的厚度，使得第一蚀刻阻挡图形160完全被覆盖。
第九步，请参阅图9，在第二电镀层170的表面形成第二蚀刻阻挡图形180。
所述第二蚀刻阻挡图形180与第二开口1142相对应。所述第二蚀刻阻挡图形180可以采用贴合干膜，然后曝光、显影的方式形成。
第十步，请参阅图10，对第一电镀层140和第二电镀层170进行蚀刻，使得被第二蚀刻阻挡图形180覆盖的部分第一电镀层140和第二电镀层170形成第二导电柱192，使得被第一蚀刻阻挡图形160覆盖的部分第一电镀层140形成第一导电柱191。
在本步骤中，优选采用蚀刻因子大于4的蚀刻液进行蚀刻，以减少蚀刻过程中产生的侧蚀。被第二蚀刻阻挡图形180覆盖的部分第一电镀层140和第二电镀层170没有被蚀刻，形成通过第二开口1142与第一导电线路图形112相互连接的第二导电柱192。所述第二导电柱192的高度等于第一电镀层140和第二电镀层170的厚度之和。位于第一蚀刻阻挡图形160表面的第二电镀层170被蚀刻，而被第一蚀刻阻挡图形160覆盖的部分第一电镀层140未被蚀刻，从而形成通过第一开口1141与第一导电线路图形112相互连接的第一导电柱191。
第十一步，请参阅图11，去除第一电镀阻挡图形130、第一蚀刻阻挡图形160和第二蚀刻阻挡图形180，从而得到封装基板100a。
由于第一电镀阻挡图形130和第二蚀刻阻挡图形180可均采用干膜形成，在去除时，可以采用剥膜的方式同时去除。
可以理解的是，请参阅图12，本步骤中，第一蚀刻阻挡图形160也可以不去除。由于第一蚀刻阻挡图形160采用锡或者镍制成，可以采用红外回流焊（IR-Relow）处理，使得第一蚀刻阻挡图形160熔融后形成覆盖在第一导电柱191端部的焊帽193。
本技术方案第二实施例也提供一种封装基板的制作方法，所述封装基板的制作方法与第一实施例提供的封装基板的制作方法相近，其中，第一步至第八步的操作与第一实施例相同，以下从第九步及之后的制作步骤进行说明。
第九步，请参阅图13，在第二电镀层170的表面形成光致抗蚀剂层171，所述光致抗蚀剂层171中形成有与第二开口1142相对应的第二开孔172，所述第二电镀层170从第二开孔172底部露出。并在第一电镀阻挡图形130中形成多个第三开孔131，使得部分第二导电线路图形113从第三开孔131露出。
第十步，请参阅图14，在从第二开孔172露出的第二电镀层170表面电镀镍金形成第二蚀刻阻挡图形180。
本步骤中，同时在从第三开孔131露出的部分第二导电线路图形113表面进行电镀镍金形成保护层194。
第十一步，请参阅图15，去除光致抗蚀剂层171及第一电镀阻挡图形130，并对第一电镀层140和第二电镀层170进行蚀刻，从而得到第一导电柱191和第二导电柱192，得到封装基板100b。
其中，第二导电柱192远离第一导电线路图形112的一端形成有电镀镍金形成的第二蚀刻阻挡图形180。每个第一导电柱191的一端形成有电镀镍或锡形成的第一蚀刻阻挡图形160。
可以理解的是，请参阅图16，本实施例中也可以进一步包括采用红外回流焊（IR-Relow）处理，使得第一蚀刻阻挡图形160熔融后形成覆盖在第一导电柱191端部的焊帽193。第二蚀刻阻挡图形180可以作为第二导电柱192远离第一导电线路图形112的一端的保护层。
请参阅图12，本技术方案第三实施例提供一种封装基板100a，所述封装基板100a包括电路基板110、多个第一导电柱191及多个第二导电柱192。
所述电路基板包括第一基底111、第一导电线路图形112、第二导电线路图形113、第一防焊层114及第二防焊层115。第一基底111为多层基板，包括交替排列的多层树脂层与多层导电线路图形（图未示）。第一基底111包括相对的第一表面1111及第二表面1112，该第一导电线路图形112设置于该第一基底111的第一表面1111上，该第二导电线路图形113设置于该第一基底111的第二表面1112上。该第一基底111的多层导电线路图形之间及该第一基底111的多层导电线路图形与该第一导电线路图形112和第二导电线路图形113分别通过导电孔（图未示）电连接。
该第一防焊层114覆盖部分该第一导电线路图形112及从该第一导电线路图形112露出的第一表面1111，所述第一防焊层114内形成有多个第一开口1141及多个第二开口1142,多个第一开口1141位于第一防焊层114的中心区域，并阵列排布。第二开口1142环绕多个第一开口1141设置。第一开口1141的横截面积小于第二开口1142的横截面积。部分该第一导电线路图形112从该第一防焊层114的第一开口1141和第二开口1142露出。
该第二防焊层115覆盖部分该第二导电线路图形113及从该第二导电线路图形113露出的第二表面1112，所述第二防焊层115内形成有多个第三开口1151,使部分该第二导电线路图形113从该第二防焊层115露出。
所述第一导电柱191通过第一开口1141与第一导电线路图形112相互电连接。第二导电柱192通过第二开口1142与第二导电线路图形113与第一导电线路图形112相互电连接。第一导电柱191的高度小于第二导电柱192的高度。在所述第一导电柱191远离第一导电线路图形112的一端，还形成有镍锡制成的焊帽193。
可以理解的是，本技术方案提供的封装基板还可以包括形成在第二导电柱192远离第一导电线路图形112一端及从第二防焊层115露出第二导电线路图形113的表面还可以包括由镍金制成的保护层。
本技术方案提供的封装基板及其制作方法，通过在形成第一电镀层之后，设置与欲形成的第一导电柱相对应的第一蚀刻阻挡图形，并在第一电镀层及第一蚀刻阻挡图形表面形成第二电镀层，然后，采用一次性蚀刻即可得到高度不同的第一导电柱和第二导电柱。所述第一导电柱的高度可以通过控制第一电镀层的厚度进行控制，第二导电柱的高度可以通过第一电镀层和第二电镀层的厚度之和进行控制，工艺操作简单。
请参阅图17，本技术方案第四实施例提供一种封装结构10，所述封装结构10包括第一封装体11和封装于第一封装体11的第二封装体12。
其中，第一封装体11包括所述的封装基板100a及第一芯片200。第一芯片200的横截面积小于封装基板100a的横截面积。第一芯片200具有与多个第一导电柱191相对应的多个第一电极垫210。每个第一电极垫210与一个对应的第一导电柱191通过第一焊球101相互电连接。每个第一焊球101环绕对应的第一导电柱191并与第一电极垫210相互接触。为了使得第一芯片200与封装基板100a牢固结合，在第一芯片200与封装基板100a之间，设置有第一封装胶体102。
第二封装体12包括连接基板300及至少一个第二芯片400。连接基板300封装于封装基板100a的第一导电线路图形112的一侧。连接基板300包括第二基底310、多个第一电性接触垫320及多个第二电性接触垫330。第一电性接触垫320及第二电性接触垫330形成于第二基底310的相对两个表面。第二基底310内形成有多个第一导电孔340，每个第一电性接触垫320通过对应的一个第一导电孔340与第二电性接触垫330相互电连接。
所述连接基板300还包括第三防焊层350和第四防焊层360。所述第三防焊层350和第四防焊层360形成于第二基底310的相对两个表面。第三防焊层350内形成有开口，每个第一电性接触垫320从对应的开口露出。第四防焊层360内也形成有开口，每个第二电性接触垫330从对应的开口露出。所述第一电性接触垫320与第二导电柱192一一对应并电连接。本实施例中，每个第一电性接触垫320与第二导电柱192通过第二焊球103相互电导通。每个第二焊球103环绕对应的第二导电柱192并与第一电性接触垫320相互接触。
本实施例中，有两个第二芯片400封装于连接基板300。两个第二芯片400之间通过介电胶片600相互连接。每个第二芯片400具有第二电极垫410，每个第二电极垫410通过键合导线420与一个第二电性接触垫330相互电连接。
为了使得与连接基板300相邻的第二芯片400与连接基板300牢固结合，在第二芯片400与连接基板300之间，设置有第二封装胶体104。
在连接基板300的一侧及两个第二芯片400的周围，还通过模制的方式形成有第三封装胶体105，以包覆第二芯片400、连接基板300的第二电性接触垫330及键合导线420。
本实施例提供的封装结构10还包括第三焊球106，第三焊球106形成于封装基板100a从第三开口1151露出的第二导电线路图形113的表面，用于将封装结构10与其他元件进行连接。
可以理解的是，本实施例中的封装基板也可以采用本技术方案第二实施例提供的封装基板100b。
本技术方案中，由于封装基板100a的第一导电柱191的高度小于第二导电柱192的高度，在进行封装时，第一芯片200通过第一导电柱191封装于封装基板100a，而第二封装体12通过第二导电柱192封装于封装基板100a。由于第一导电柱191的高度与第二导电柱192的高度不等，可以使得第一芯片200厚度与第一导电柱191的高度之和与第二导电柱192的高度大致相等，从而可以减少封装结构的厚度，进而减小封装结构的体积。并且，由于封装基板100a与连接基板300之间通过第二导电柱192与第二焊球103相结合的方式进行结合，第一芯片200与封装基板100a之间通过第一导电柱191与第一焊球相结合的方式进行结合，相比于现有技术中仅采用焊球进行封装，能够提升封装结构的品质。
可以理解的是，对于本领域的普通技术人员来说，可以个据本发明的技术构思做出其它各种相应的改变与变形，而所有这些改变与变形都应属于本发明权利要求的保护范围。

Claims (15)

1.一种封装基板，其包括电路基板、多个第一导电柱及多个第二导电柱，所述电路基板具有第一基底及形成于第一基底一个表面的第一导电线路图形，所述第一导电柱及第二导电柱均与第一导电线路图形相互电连接，并自第一导电线路图形向远离第一导电线路图形的方向延伸，所述第二导电柱的高度大于所述第一导电柱的高度。
2.如权利要求1所述的封装基板，其特征在于，所述第一导电柱远离第一导电线路图形的一端形成有焊帽。
3.如权利要求1所述的封装基板，其特征在于，所述第二导电柱远离第一导电线路图形一端具有镍金制成的保护层。
4.如权利要求3所述的封装基板，其特征在于，所述电路基板还包括形成于第一基底另一表面的第二导电线路图形及第二防焊层，所述第二防焊层内形成有多个第三开口，部分第二导电线路图形第三开口露出，在从第三开口露出的第二导电线路图形表面也形成镍金制成的保护层。
5.如权利要求1所述的封装基板，其特征在于，所述电路基板还包括第一防焊层，所述第一防焊层形成于第一导电线路图形的一侧，所述第一防焊层内形成有多个第一开口和多个第二开口，所述第一导电柱穿过所述第一开口与第一导电线路图形相互电连接，所述第二导电柱穿过第二开口与第一导电线路图形相互电连接。
6.如权利要求1所述的封装基板，其特征在于，所述多个第二导电柱环绕所述多个第一导电柱设置。
7.一种封装基板的制作方法，包括步骤：
提供一电路基板，所述电路基板包括第一基底、形成于第一基底一侧表面的第一导电线路图形以及形成于第一导电线路图形表面的第一防焊层，所述第一防焊层具有多个第一开口和第二开口，部分所述第一导电线路图形从所述第一开口和第二开口露出；
在第一防焊层的表面形成金属种子层；
在所述金属种子层的表面形成第一电镀层；
在所述第一电镀层的表面形成第二电镀阻挡图形，所述第二电镀阻挡图形内有与所述第一开口相对应的第一开孔；
在从所述第一开孔露出的第一电镀层的表面形成第一蚀刻阻挡图形；
去除所述第二电镀阻挡图形；
在第一电镀层及蚀刻阻挡图形的表面形成第二电镀层；
在第二电镀层的表面形成第二蚀刻阻挡图形，所述第二蚀刻阻挡图形与第二开口相对应；以及
对第一电镀层和第二电镀层进行蚀刻，使得被第二蚀刻阻挡图形覆盖的部分第一电镀层和第二电镀层形成与第二开口相对应的第二导电柱，使得被第一阻挡图形覆盖的部分第一电镀铜层形成与第一开口相对应的第一导电柱。
8.如权利要求7所述的封装基板的制作方法，其特征在于，所述第二蚀刻阻挡图形采用贴合干膜，然后曝光及显影的方式形成，在形成第一导电柱和第二导电柱之后，还包括去除第二蚀刻阻挡图形的步骤。
9.如权利要求7所述的封装基板的制作方法，其特征在于，在在第一防焊层的表面形成金属种子层之间，还包括在电路基板的另一侧表面形成第一电镀阻挡图形的步骤，在形成第一导电柱和第二导电柱之后，还包括去除第一电镀阻挡图形的步骤。
10.如权利要求7所述的封装基板的制作方法，其特征在于，所述第一蚀刻阻挡图形采用电镀锡或者电镀镍的方式形成。
11.如权利要求10所述的封装基板的制作方法，其特征在于，在形成第一导电柱和第二导电柱之后，还包括对所述第一蚀刻阻挡图形进行红外回流焊处理，从而在每个第一导电柱表面形成焊帽的步骤。
12.如权利要求7所述的封装基板的制作方法，其特征在于，在形成第一导电柱和第二导电柱之后，还包括去除第一蚀刻阻挡图形的步骤。
13.如权利要求7所述的封装基板的制作方法，其特征在于，在所述第一电镀层及蚀刻阻挡图形的表面形成第二电镀层之后，在第二电镀层的表面形成光致抗蚀剂层，所述光致抗蚀剂层中形成有与第二开口相对应的第二开孔；在从第二开孔露出的第二电镀层表面电镀镍金形成第二蚀刻阻挡层；去除光致抗蚀剂层并对第一电镀层和第二电镀层进行蚀刻，从而得到所述第一导电柱和第二导电柱。
14.一种封装结构，包括第一封装体和封装于第一封装体的第二封装体，所述第一封装体包括第一芯片和如权利要求1至6任一项所述的封装基板，所述第一芯片具有与第一导电柱一一对应的多个第一电极垫，所述第一电极垫与第一导电柱通过第一焊球相互电导通，所述第二封装体包括连接基板及封装于连接基板的第二芯片，所述连接基板具有与第二导电柱相对应的电性接触垫，所述第二导电柱与对应的电性接触垫通过第二焊球相互电导通。
15.如权利要求14所述的封装结构，其特征在于，所述第一芯片的厚度与第一导电柱的高度之和与第二导电柱的高度相等。
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TW201436132A (zh) 2014-09-16

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