CN103914391B - Method for reading data, Memory Controller and memory storage apparatus - Google Patents
Method for reading data, Memory Controller and memory storage apparatus Download PDFInfo
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Abstract
The present invention provides a kind of method for reading data, Memory Controller and memory storage apparatus.This read method is the erasable formula non-volatile memory module for including multiple entity erasing unit, including: configure multiple logical address to map to the entity erasing unit of part；Receiving the multiple reading instructions from host computer system, wherein these read instruction instruction and read multiple first logical addresses in above-mentioned logical address；Perform these and read instruction, and judge whether the first logical address is continuous；And if the first logical address is continuously, from entity erasing unit, pre-read belongs to the data of a logic scope to buffer storage.Thus, it is possible to promote the speed reading data.
Description
Technical field
The invention relates to a kind of method for reading data, and non-volatile for erasable formula in particular to one
The method for reading data of memory module, Memory Controller and memory storage apparatus.
Background technology
Digital camera, mobile phone and MP3 player are the rapidest in growth over the years so that consumer is to storage
The demand of media increases the most rapidly.Owing to erasable formula non-volatile memory module (such as, flash memory) has data
Non-volatile, power saving, volume are little, and the characteristic such as mechanical structure, so being especially suitable for being built in above-mentioned illustrated various
In portable multimedia device.
In general, erasable formula non-volatile memory module can be controlled by a Memory Controller, and deposits
Memory controller can receive the reading instruction coming from host computer system.Memory Controller can be according to received reading instruction
Data are read from erasable formula non-volatile memory module.Memory Controller can set up an instruction array, Qi Zhongcun
Store up the reading instruction coming from host computer system.The execution that Memory Controller can read instruction in discretional orders array is suitable
Sequence.Further, Memory Controller can pre-read (pre-read) some data to one from erasable formula non-volatile memory module
Individual buffer storage, in order to the speed reading data can be increased when host computer system to read multiple continuous print address.But, main
Machine system assigns reading instruction not necessarily can sequentially to Memory Controller, and this can cause the data pre-read from buffer storage
It is eliminated.Therefore, the speed reading data how is increased, for this skilled person subject under discussion of interest.
Summary of the invention
The exemplary embodiment of the present invention proposes a kind of method for reading data, Memory Controller and memorizer storage dress
Put, the speed reading data can be increased.
The present invention one exemplary embodiment proposes a kind of method for reading data, for controlling an erasable formula non-volatile memories
Device module.This erasable formula non-volatile memory module includes that multiple entity wipes unit.Above-mentioned method for reading data bag
Include: configure multiple logical address to map to the entity erasing unit of part；Receive and read from multiple the first of host computer system
Instruction, wherein first reads multiple first logical addresses in the instruction instruction above-mentioned logical address of reading；Perform the first reading to refer to
Order, and judge whether the first logical address is continuous；And if the first logical address is continuously, pre-from entity erasing unit
Read and belong to the data of the first logic scope to buffer storage.
In an exemplary embodiment, above-mentioned method for reading data, also include: receive and come from one of host computer system the
Second reading instruction fetch, wherein second reads instruction instruction one the second logical address of reading；Judge that whether the second logical address is upper
Stating in the preset range in logical address, wherein preset range includes the first logic scope；If the second logical address is predetermined
In the range of, it is judged that whether the second logical address is the initial logical address of the first logic scope；And if the second logical address is
Initial logical address, then transmit and belong to the data of the second logical address to host computer system.
In an exemplary embodiment, above-mentioned method for reading data, also include: if the second logical address is start logical ground
Location, from entity erasing unit, pre-read belongs to the data of second logic scope in buffer storage, wherein second patrols
Volume scope be connected at the first logic scope after.
In an exemplary embodiment, above-mentioned method for reading data also includes: if the second logical address is not for start logical
Address, maintains the data belonging to the first logic scope and to start a timer in buffer storage；And if timer
The numerical value recorded is more than a marginal value, removes the data belonging to the first logic scope in buffer storage.
In an exemplary embodiment, when above-mentioned marginal value is proportional to the reading of erasable formula non-volatile memory module
Between.
In an exemplary embodiment, above-mentioned method for reading data also includes: receives and comes from one of host computer system the
Third reading instruction fetch, wherein the 3rd logical address in logical address is read in third reading instruction fetch instruction；And if the 3rd patrol
Collecting address is initial logical address, resets timer and transmission belongs to the data of the 3rd logical address to host computer system.
In an exemplary embodiment, above-mentioned method for reading data also includes: if the second logical address is not at preset range
In, remove the data belonging to the first logic scope in buffer storage.
In an exemplary embodiment, above-mentioned method for reading data also includes: receives and comes from one of host computer system the
Second reading instruction fetch, wherein second reads second logical address in instruction instruction reading logical address；Judge the second logic
Whether address is in preset range, and wherein preset range includes the first logic scope；If the second logical address is in preset range,
Judge that the second logical address is whether in the first logic scope；If the second logical address is in the first logic scope, transmission belongs to
The data of the second logical address are to host computer system.
In an exemplary embodiment, above-mentioned method for reading data also includes: if the second logical address is not in the first logic
In the range of, maintain the data belonging to the first logic scope and to start a timer in buffer storage；And if timer
The numerical value recorded is more than marginal value, removes the data belonging to the first logic scope in buffer storage.
In an exemplary embodiment, the size of above-mentioned first logic scope is big equal to the storage space of buffer storage
Little.
For another one angle, the present invention one exemplary embodiment proposes a kind of memory storage apparatus, including connecting
Device, erasable formula non-volatile memory module and Memory Controller.Adapter is to be electrically connected to a host computer system.
Erasable formula non-volatile memory module includes that multiple entity wipes unit.Memory Controller is electrically connected to adapter
With erasable formula non-volatile memory module, wipe unit in order to configure multiple logical address with the entity mapping to part,
And receive and read instruction from multiple the first of host computer system.These the first reading instruction instructions are read in above-mentioned logical address
Multiple first logical addresses.Memory Controller is also in order to perform these the first reading instructions, and judges first logically
Whether location is continuous.If the first logical address is continuously, Memory Controller belongs in order to pre-read from entity erasing unit
In above-mentioned logical address, the data of the first logic scope are to a buffer storage.
In an exemplary embodiment, above-mentioned Memory Controller is also in order to receive the second reading coming from host computer system
Instruction, wherein second reads the second logical address in instruction instruction reading logical address.Memory Controller is also in order to judge
In the second logical address whether preset range in logical address, wherein preset range includes the first logic scope.If second
Logical address is in preset range, and Memory Controller is also in order to judge whether the second logical address is rising of the first logic scope
Beginning logical address.If the second logical address is initial logical address, Memory Controller also belongs to second logically in order to transmitting
The data of location are to host computer system.
In an exemplary embodiment, if the second logical address is not initial logical address, Memory Controller is also in order to tie up
Hold the data belonging to the first logic scope and and start timer in buffer storage.If the numerical value that timer is recorded is more than
Marginal value, Memory Controller is also in order to remove the data belonging to the first logic scope in buffer storage.
In an exemplary embodiment, above-mentioned Memory Controller also takes in order to receiving the third reading coming from host computer system
Instruction, wherein the 3rd logical address in logical address is read in third reading instruction fetch instruction.If the 3rd logical address is patrolled for initial
Volume address, Memory Controller also belongs to the data of the 3rd logical address to host computer system in order to resetting timer and transmission.
In an exemplary embodiment, above-mentioned Memory Controller is also in order to receive the second reading coming from host computer system
Instruction, wherein second reads the second logical address in instruction instruction reading logical address.Memory Controller is also in order to judge
In the second logical address whether preset range in logical address.If the second logical address is in preset range, memorizer control
Device processed is also in order to judge that the second logical address is whether in the first logic scope.If the second logical address is at the first logic scope
In, Memory Controller is also in order to transmit the data belonging to the second logical address to host computer system.
In an exemplary embodiment, if the second logical address is not in the first logic scope, Memory Controller also in order to
The data belonging to the first logic scope are maintained and to start timer in buffer storage.If the numerical value that timer is recorded is big
In marginal value, Memory Controller is also in order to remove the data belonging to the first logic scope in buffer storage.
For another one angle, the present invention one exemplary embodiment proposes a kind of Memory Controller, for control one
Erasable formula non-volatile memory module.This Memory Controller includes that HPI, memory interface manage with memorizer
Circuit.HPI is to be electrically connected to a host computer system.Memory interface is that to be electrically connected to erasable formula non-
Volatile, and this erasable formula non-volatile memory module include multiple entity wipe unit.Memorizer
Management circuit is electrically connected to HPI and memory interface, in order to configure multiple logical address to map to the reality of part
Body erasing unit, and receive the multiple first reading instructions from host computer system.Wherein these the first reading instruction instructions are read
Take multiple first logical addresses in above-mentioned logical address.Memory management circuitry also in order to perform first reading instruction, and
Judge whether the first logical address is continuous.If the first logical address is continuously, memory management circuitry is in order to wipe from entity
During in unit, pre-read belongs to above-mentioned logical address, the data of the first logic scope are to a buffer storage.
In an exemplary embodiment, above-mentioned memory management circuitry is also in order to receive the second reading coming from host computer system
Instruction fetch, wherein second reads the second logical address in instruction instruction reading logical address.Memory management circuitry also in order to
In judging second logical address preset range whether in logical address, wherein preset range includes the first logic scope.If
Second logical address is in preset range, and memory management circuitry is also in order to judge whether the second logical address is the first logic model
The initial logical address enclosed.If the second logical address is initial logical address, memory management circuitry also belongs in order to transmitting
The data of two logical addresses are to host computer system.
In an exemplary embodiment, if the second logical address is initial logical address, memory management circuitry also in order to from
In entity erasing unit, pre-read belongs to the data of the second logic scope in buffer storage, and wherein the second logic scope is to connect
Continue after the first logic scope.
In an exemplary embodiment, if the second logical address is not initial logical address, memory management circuitry also in order to
The data belonging to the first logic scope are maintained and to start timer in buffer storage.If the numerical value that timer is recorded is big
In marginal value, memory management circuitry is also in order to remove the data belonging to the first logic scope in buffer storage.
In an exemplary embodiment, above-mentioned memory management circuitry is also in order to receive the third reading coming from host computer system
Instruction fetch, wherein the 3rd logical address in logical address is read in third reading instruction fetch instruction.If the 3rd logical address is initial
Logical address, memory management circuitry also belongs to the data of the 3rd logical address to main frame system in order to resetting timer and transmission
System.
In an exemplary embodiment, if the second logical address is not within the predefined range, memory management circuitry is also in order to clearly
Except the data belonging to the first logic scope in buffer storage.
In an exemplary embodiment, above-mentioned memory management circuitry is also in order to receive the second reading coming from host computer system
Instruction fetch, wherein second reads the second logical address in instruction instruction reading logical address.Memory management circuitry also in order to
In judging second logical address preset range whether in logical address.If the second logical address is in preset range, storage
Device management circuit is also in order to judge that the second logical address is whether in the first logic scope.If the second logical address is in the first logic
In the range of, memory management circuitry is also in order to transmit the data belonging to the second logical address to host computer system.
In an exemplary embodiment, if the second logical address is not in the first logic scope, memory management circuitry is also used
To maintain the data belonging to the first logic scope and to start timer in buffer storage.If the numerical value that timer is recorded
More than marginal value, memory management circuitry is also in order to remove the data belonging to the first logic scope in buffer storage.
Based on above-mentioned, method for reading data, Memory Controller proposed by the invention can roots with memory storage apparatus
Continuous print logical address whether is have read to determine whether to pre-reads data according to the reading instruction being finished.Thus, may be used
To increase the speed reading data.
For the features described above of the present invention and advantage can be become apparent, special embodiment below, and coordinate accompanying drawing to make in detail
Carefully it is described as follows.
Accompanying drawing explanation
Figure 1A is the schematic diagram according to the host computer system shown by an exemplary embodiment Yu memory storage apparatus；
Figure 1B is to show with memory storage apparatus according to the computer shown by an exemplary embodiment, input/output device
It is intended to；
Fig. 1 C is the schematic diagram according to the host computer system shown by an exemplary embodiment Yu memory storage apparatus；
Fig. 2 is the schematic block diagram illustrating the memory storage apparatus shown in Figure 1A；
Fig. 3 is the schematic block diagram according to the Memory Controller shown by an exemplary embodiment；
Fig. 4 is according to the example signal managing erasable formula non-volatile memory module shown by an exemplary embodiment
Figure；
Fig. 5 is the example schematic illustrating record shelves according to an exemplary embodiment；
Fig. 6 A is to illustrate that pre-read belongs to the schematic diagram of the data of a logic scope according to an exemplary embodiment；
Fig. 6 B is to illustrate, according to an exemplary embodiment, the system flow chart judging that pre-reading data is later；
Fig. 7 is the flow chart illustrating method for reading data according to an exemplary embodiment.
Description of reference numerals:
1000: host computer system；
1100: computer；
1102: microprocessor；
1104: random access memory；
1106: input/output device；
1108: system bus；
1110: data transmission interface；
1202: mouse；
1204: keyboard；
1206: display；
1208: printer；
1212:U dish；
1214: storage card；
1216: solid state hard disc；
1310: digital camera；
1312:SD card；
1314:MMC card；
1316: storage card；
1318:CF card；
1320: embedded storage device；
100: memory storage apparatus；
102: adapter；
104: Memory Controller；
106: erasable formula non-volatile memory module；
304 (0)～304 (R): entity erasing unit；
202: memory management circuitry；
204: HPI；
206: memory interface；
252: buffer storage；
254: electric power management circuit；
256: error checking and correcting circuit；
410: data field；
420: idle district；
430: system area；
440: replace district；
450 (0)～450 (E): logical address
510: record shelves；
511～515: read instruction；
610,640: logic scope；
620: logical address；
630: preset range；
The step of S602, S604, S606, S608, S610, S612, S614: system flow chart；
The step of S702, S704, S706, S708: method for reading data.
Detailed description of the invention
[the first exemplary embodiment]
It is said that in general, memory storage apparatus (also referred to as, storage system) includes erasable formula non-volatile memories
Device module and controller (also referred to as, control circuit).Being commonly stored device storage device is to be used together with host computer system, so that main frame
System can write data into memory storage apparatus or read data from memory storage apparatus.
Figure 1A is the schematic diagram according to the host computer system shown by an exemplary embodiment Yu memory storage apparatus.
Refer to Figure 1A, host computer system 1000 generally comprises computer 1100 and input/output (input/output, I/O)
Device 1106.Computer 1100 includes microprocessor 1102, random access memory (random access memory, RAM)
1104, system bus 1108 and data transmission interface 1110.Figure 1B be according to the computer shown by an exemplary embodiment, input/
Output device and the schematic diagram of memory storage apparatus, with reference to Figure 1B, input/output device 1106 includes the mouse such as Figure 1B
1202, keyboard 1204, display 1206 and printer 1208.It will be appreciated that the unrestricted input of device shown in Figure 1B/defeated
Going out device 1106, input/output device 1106 can also include other devices.
In embodiments of the present invention, memory storage apparatus 100 is by data transmission interface 1110 and host computer system
Other elements of 1000 are electrically connected with.By microprocessor 1102, random access memory 1104 and input/output device 1106
Running can write data into memory storage apparatus 100 or from memory storage apparatus 100 read data.Such as, deposit
Reservoir storage device 100 can be USB flash disk 1212 as shown in Figure 1B, storage card 1214 or solid state hard disc (Solid State
Drive, SSD) the erasable formula non-volatile memory storage device of 1216 grades.
It is said that in general, host computer system 1000 is for coordinating with memory storage apparatus 100 substantially to store appointing of data
Meaning system.Although in this exemplary embodiment, host computer system 1000 is to explain with computer system, but, another in the present invention
In one exemplary embodiment, host computer system 1000 can be digital camera, video camera, communicator, audio player or video playback
The systems such as device.Such as, when host computer system is digital camera (video camera) 1310, erasable formula nonvolatile memory storage dress
Put, by its SD card 1312 used, mmc card 1314, memory stick (memory stick) 1316, CF card 1318 or embedded
Storage device 1320 (as shown in Figure 1 C).Embedded storage device 1320 include embedded multi-media card (Embedded MMC,
eMMC).It is noted that embedded multi-media card is directly to be electrically connected on the substrate of host computer system.
Fig. 2 is the schematic block diagram illustrating the memory storage apparatus shown in Figure 1A.
Refer to Fig. 2, memory storage apparatus 100 includes that adapter 102, Memory Controller 104 are non-with erasable formula
Volatile 106.
In this exemplary embodiment, adapter 102 is compatible with sequence advanced person adnexa (Serial
AdvancedTechnology Attachment, SATA) standard.However, it is necessary to be appreciated that, the invention is not restricted to this, connect
Device 102 can also be to meet the most advanced adnexa (Parallel Advanced TechnologyAttachment, PATA) mark
Accurate, Institute of Electrical and Electric Engineers (Institute of Electrical andElectronic Engineers, IEEE)
1394 standards, high-speed peripheral component connecting interface (PeripheralComponent Interconnect Express, PCI
Express) standard, USB (universal serial bus) (UniversalSerial Bus, USB) standard, safety digit (Secure
Digital, SD) interface standard, a ultrahigh speed generation (UltraHigh Speed-I, UHS-I) interface standard, ultrahigh speed be secondary
(Ultra High Speed-II, UHS-II) interface standard, storage card (Memory Stick, MS) interface standard, multimedia are deposited
Card storage (Multi MediaCard, MMC) interface standard, enter formula multimedia storage card (Embedded Multimedia
Card, eMMC) interface standard, general flash memory (Universal Flash Storage, UFS) interface standard, small-sized sudden strain of a muscle
Speed (Compact Flash, CF) interface standard, integrated driving electrical interface (Integrated DeviceElectronics,
DE) standard or other standards being suitable for.
Memory Controller 104 is in order to perform in the form of hardware or multiple gates of solid form implementation or control refer to
Order, and according to the instruction of host computer system 1000 carry out in erasable formula non-volatile memory module 106 data write,
Read and operate with erasing etc..
Erasable formula non-volatile memory module 106 is electrically connected to Memory Controller 104, and in order to store
The data that host computer system 1000 is write.Erasable formula non-volatile memory module 106 has entity erasing unit 304 (0)
～304 (R).Such as, entity erasing unit 304 (0)～304 (R) can belong to same memory crystal grain (die) or belong to not
Same memory crystal grain.Each entity erasing unit is respectively provided with a plurality of entity program unit, and belongs to same reality
The entity program unit of body erasing unit can be written independently and simultaneously be wiped.Such as, each entity erasing unit
It is made up of 128 entity program unit.However, it is necessary to be appreciated that, the invention is not restricted to this, the erasing of each entity is single
Unit is can be by 64 entity program unit, 256 entity program unit or other the most individual entity program unit institute groups
Become.
In more detail, entity erasing unit is the least unit of erasing.That is, each entity erasing unit contains minimum
The unit being wiped free of in the lump of number.Entity program unit is the minimum unit of sequencing.That is, entity program unit is for writing
Enter the minimum unit of data.Each entity program unit generally includes data bit district and redundancy function district.Data bit district comprises many
Individual entity access address is in order to store the data of user, and redundancy function district (such as, controls information in order to the data storing system
With error correcting code).In this exemplary embodiment, the data bit district of each entity program unit can comprise 4 entities
Access address, and the size of an entity access address is 512 bytes (byte, B).But, in other exemplary embodiment, number
According to also comprising 8,16 or number more or less of entity access address in the district of position, the present invention is not limiting as entity access
The size of address and number.Such as, entity erasing unit be physical blocks, and entity program unit be physical page or
Entity is fanned.
In this exemplary embodiment, erasable formula non-volatile memory module 106 is multilevel-cell (MultiLevel
Cell, MLC) NAND flash memory module, i.e. one storage bag can store at least 2 Bit datas.But, the present invention
Being not limited to this, erasable formula non-volatile memory module 106 may also be single layer cell (Single Level Cell, SLC)
NAND flash memory module, plural layer unit (Trinary Level Cell, TLC) NAND flash memory module,
Other flash memory module or other there is the memory module of identical characteristics.
Fig. 3 is the schematic block diagram according to the Memory Controller shown by an exemplary embodiment.
Refer to Fig. 3, Memory Controller 104 includes that memory management circuitry 202, HPI 204 connect with memorizer
Mouth 206.
Memory management circuitry 202 is in order to control the overall operation of Memory Controller 104.Specifically, memorizer pipe
Reason circuit 202 has multiple control instruction, and when memory storage apparatus 100 operates, these a little control instructions can be performed
To carry out the write of data, to read and operate with erasing etc..
In this exemplary embodiment, the control instruction of memory management circuitry 202 is to carry out implementation in solid form.Such as,
Memory management circuitry 202 has microprocessor unit (not shown) and read only memory (not shown), and this controls to refer to a bit
Order is to be programmed so far in read only memory.When memory storage apparatus 100 operates, these a little control instructions can be by microprocessor
Unit performs to carry out the write of data, reads and operate with erasing etc..
In another exemplary embodiment of the present invention, the control instruction of memory management circuitry 202 can also procedure code form
The specific region being stored in erasable formula non-volatile memory module 106 (such as, is exclusively used in storage system in memory module
The system area of data) in.Additionally, memory management circuitry 202 has microprocessor unit (not shown), read only memory (not
Illustrate) and random access memory (not shown).Particularly, this read only memory has driving code, and when memorizer controls
When device 104 is enabled, microprocessor unit can first carry out this and drive code section will be stored in erasable formula nonvolatile memory
Control instruction in module 106 is loaded in the random access memory of memory management circuitry 202.Afterwards, microprocessor list
Unit can run these a little control instructions to carry out the write of data, to read and operate with erasing etc..
Additionally, in another exemplary embodiment of the present invention, the control instruction of memory management circuitry 202 can also a hardware
Form carrys out implementation.Such as, memory management circuitry 202 include microcontroller, MMU, memorizer writing unit,
Memorizer reads unit, memorizer erasing unit and data processing unit.MMU, memorizer writing unit, deposit
Reservoir reads unit, memorizer erasing unit is electrically connected to microcontroller with data processing unit.Wherein, memorizer management
Unit is in order to manage the physical blocks of erasable formula non-volatile memory module 106；Memorizer writing unit is in order to erasable
Write formula non-volatile memory module 106 and assign write instruction to write data into erasable formula non-volatile memory module
In 106；Memorizer reads unit in order to erasable formula non-volatile memory module 106 to be assigned reading instruction with from erasable
Formula non-volatile memory module 106 reads data；Memorizer erasing unit is in order to erasable formula nonvolatile memory
Module 106 assigns erasing instruction data to be wiped from erasable formula non-volatile memory module 106；And data process single
Unit is intended to write to the data of erasable formula non-volatile memory module 106 in order to process and deposits from erasable formula is non-volatile
The data read in memory modules 106.
HPI 204 is electrically connected to memory management circuitry 202 and in order to receive and to identify host computer system
1000 instruction transmitted and data.It is to say, the instruction that host computer system 1000 is transmitted can pass through HPI with data
204 are sent to memory management circuitry 202.In this exemplary embodiment, HPI 204 is compatible with SATA standard.So
And, it should be understood that the invention is not restricted to this, HPI 204 can also be compatible with PATA standard, IEEE 1394 marks
Standard, PCI Express standard, USB standard, SD standard, UHS-I standard, UHS-II standard, MS standard, MMC standard, eMMC mark
Standard, UFS standard, CF standard, IDE standard or other data transmission standards being suitable for.
Memory interface 206 is electrically connected to memory management circuitry 202 and non-volatile in order to access erasable formula
Property memory module 106.It is to say, the data being intended to write to erasable formula non-volatile memory module 106 can be via depositing
Memory interface 206 is converted to the receptible form of erasable formula non-volatile memory module 106.
In the present invention one exemplary embodiment, Memory Controller 104 also includes buffer storage 252, power management electricity
Road 254 and error checking and correcting circuit 256.
Buffer storage 252 is electrically connected to memory management circuitry 202 and is configured to temporarily store and comes from host computer system
The data of 1000 and instruction or come from the data of erasable formula non-volatile memory module 106.
Electric power management circuit 254 is electrically connected to memory management circuitry 202 and in order to control memorizer storage dress
Put the power supply of 100.
Error checking and correcting circuit 256 are electrically connected to memory management circuitry 202 and in order to perform mistake inspection
Look into correction program to guarantee the correctness of data.Specifically, connect from host computer system 1000 when memory management circuitry 202
When receiving write instruction, error checking produces corresponding mistake inspection with the data that correcting circuit 256 can be this write instruction corresponding
Look into and correcting code (Error Checking andCorrecting Code, ECC Code), and memory management circuitry 202
Can be by the data of this write instruction corresponding and corresponding error checking and correcting code write extremely erasable formula nonvolatile memory
In module 106.Afterwards, when memory management circuitry 202 reads data from erasable formula non-volatile memory module 106
Error checking corresponding to these data and correcting code can be read simultaneously, and error checking can be according to this mistake with correcting circuit 256
Check and perform error checking and correction program with the correcting code data to being read.
Fig. 4 is according to the example signal managing erasable formula non-volatile memory module shown by an exemplary embodiment
Figure.
During it will be appreciated that be described herein the running of the physical blocks of erasable formula non-volatile memory module 106,
Carrying out application entity block with the word such as " extraction ", " exchange ", " packet ", " rotating " is concept in logic.It is to say, it is erasable
The physical location of the physical blocks of formula non-volatile memory module is not changed, but non-volatile to erasable formula in logic
The physical blocks of memory module operates.
Refer to Fig. 4, Memory Controller 104 can be by the physical blocks 304 of erasable formula non-volatile memory module
(0)～304 (R) are logically grouped into multiple region, for example, data field 410, idle district 420, system area 430 and replace district
440.In another exemplary embodiment, replace district 440 and also can share, with idle district 420, the physical blocks comprising invalid data.
Data field 410 is the data storing and coming from host computer system 1000 with the physical blocks in idle district 420.Specifically
For, data field 410 is the physical blocks of storage data, and the physical blocks in idle district 420 is in order to replacement data district 410
Physical blocks.Therefore, the physical blocks in idle district 420 is empty or spendable physical blocks, wherein not storage data or
It is to store to be labeled as invalid data the most useless.It is to say, the physical blocks in idle district 420 has been performed erasing fortune
Make, or the physical blocks meeting extracted before data is first be held when the physical blocks in idle district 420 is extracted for storing
Row erasing running.Therefore, the physical blocks in idle district 420 is the physical blocks that can be used.
The physical blocks logically belonging to system area 430 is to record system data, and wherein this system data includes closing
Manufacturer and model, the physical blocks number of memory chips, the physical page number etc. of each physical blocks in memory chips.
Logically belonging to replace the physical blocks in district 440 is to substitute physical blocks.Such as, erasable formula is non-volatile deposits
Memory modules can be reserved the physical blocks of 4% and use as changing when dispatching from the factory.It is to say, when data field 410, idle district
420 with physical blocks damage in system area 430 time, be reserved in the physical blocks replaced in district 440 in order to replacing damaged
Physical blocks (that is, bad physical blocks (badblock)).Therefore, if replace in district 440 still have normal physical blocks and
When there is physical blocks damage, Memory Controller 104 can extract normal physical blocks to change damage from replacing district 440
Physical blocks.If time in replacement district 440 without normal physical blocks and generation physical blocks damage, then Memory Controller
Whole memory storage apparatus 100 can be declared as write protection (writeprotect) state by 104, and cannot write number again
According to.
Particularly, the quantity of the physical blocks in data field 410, idle district 420, system area 430 and replacement district 440 can foundation
Different memorizer specifications and different.Further, it is necessary to be appreciated that, in the running of memory storage apparatus 100, entity
Block associations to data field 410, idle district 420, system area 430 can dynamically change with the packet relation in replacement district 440.Example
As, when the physical blocks in idle district is damaged and is replaced the physical blocks replacement in district, then originally replace the physical blocks in district
Idle district can be associated to.
In this exemplary embodiment, Memory Controller 104 can configure logical address 450 (0)～450 (E) and be beneficial to
The physical blocks of storage data carries out data access.Such as, shelves are passed through when memory storage apparatus 100 by operating system 1110
When case system (such as, FAT 32) formats, logical address 450 (0)～450 (E) maps to the entity of data field 410 respectively
Block 304 (0)～304 (A).Here, memory management circuitry 202 (or Memory Controller 104) can set up logical address-reality
Body erasing unit mapping table (logical address-physical erasing unit mapping table), with record
Mapping relations between logical block addresses and entity erasing unit.In this exemplary embodiment, each logical address 450
(0)～the size of 450 (E) is same as the size of an entity erasing unit, i.e. logical address is also referred to as logical blocks ground
Location (logical block address, LBA).But, in other exemplary embodiment, each logical address 450 (0)～
The size of 450 (E) can also be the size of an entity program unit, the present invention be not limiting as logical address 450 (0)～
The size of 450 (E).
Host computer system 1000 can be assigned multiple reading and instruct to memory management circuitry 202 (or Memory Controller 104),
And these read instruction is one or more logical address that instruction reads in logical address 450 (0)～450 (E).Memorizer pipe
Reason circuit 202 (or Memory Controller 104) can by these reading instructions put into an instruction array (command queue) when
In, and memory management circuitry 202 (or Memory Controller 104) can determine to perform these orders reading instruction.If depositing
Reservoir management circuit 202 (or Memory Controller 104) to perform one and read instruction, then memory management circuitry 202 (or is deposited
Memory controller 104) can be obtained this read instruction logical address to be read, and obtain that this logical address is mapped one
Entity erasing unit, reads data from this entity erasing unit, and sends these data to host computer system 1000.But,
Before performing a reading instruction, memory management circuitry 202 (or Memory Controller 104) can wipe unit from entity
304 (0)～304 (B) pre-read some data to the buffer storage 252 in Memory Controller 104；If it follows that this reads
Instruction fetch data to be read in buffer storage 252, memory management circuitry 202 (or Memory Controller
104) data in buffer storage 252 just can be sent host computer system 1000 to, thus increase the speed reading data.?
In another exemplary embodiment, the data that memory management circuitry 202 (or Memory Controller 104) pre-reads can also be placed on storage
In a buffer storage beyond device controller 104, the present invention is the most not subject to the limits.
Fig. 5 is the example schematic illustrating record shelves according to an exemplary embodiment.
Refer to Fig. 5, memory management circuitry 202 (or Memory Controller 104) receives many from host computer system 1000
Individual read instruction (also referred to as first read instruction) and performed after these read instruction, can be the reading instruction being finished
Exist in record shelves 510.Such as, have recorded and be performed complete reading instruction 511～515 in record shelves 510, it refers to respectively
Show reading logical address 450 (2), 450 (4), 450 (1), 450 (0) and 450 (3) (the also referred to as first logical addresses).Memorizer pipe
Reason circuit 202 (or Memory Controller 104) is first to receive reading instruction 511 from host computer system 1000, receive the most in order
To reading instruction 512～515；In other words, according to receiving the order reading instruction 511～515, memory management circuitry 202
(or Memory Controller 104) can't find host computer system 1000 continuous print to be read logical address.But, real at this example
Executing in example, memory management circuitry 202 (or Memory Controller 104) can judge to read after having performed to read instruction 511～515
Whether instruction fetch 511～515 logical address to be read is continuous.Such as, memory management circuitry 202 (or memorizer control
Device 104 processed) sorted reading instruction 511～515 logical addresses to be read after, it is found that logical address 450 (0)～
450 (4) is continuous.Although this represents that host computer system 1000 is that transmission sequentially reads instruction 511～515 to memorizer management electricity
Road 202 (or Memory Controller 104), but host computer system 1000 is reading continuous print logical address 450 (0)～450 (4).
Owing to logical address 450 (0)～450 (4) is continuously, the logical address that host computer system 1000 is to be read is also likely to be even
Continuous.Therefore, memory management circuitry 202 (or Memory Controller 104) meeting pre-read belongs to the data of a logic scope.
In this exemplary embodiment, record shelves 510 have recorded 5 and read instruction 511～515.But, at other examples
In embodiment, record shelves 5 10 can also more or less of reading of record count instruct.Further, memory management circuitry
202 (or Memory Controllers 104) are to have n to read instruction in judging record shelves 510 to start to pre-read peek after continuously
According to, wherein n is positive integer.But, the present invention is not limiting as the numerical value of n.
Fig. 6 A is to illustrate that pre-read belongs to the schematic diagram of the data of a logic scope according to an exemplary embodiment.
Refer to Fig. 6 A, owing to reading in record shelves 510 instructs the logical address 450 (0)～450 (4) read be
Continuously, therefore memory management circuitry 202 (or Memory Controller 104) pre-read can belong to the data of logic scope 610 extremely
Buffer storage 252.Memory management circuitry 202 (or Memory Controller 104) also can set a preset range 630, and
And preset range 630 can include logic scope 610.But, the present invention is not limiting as logic scope 610 and preset range 630
Size.It follows that memory management circuitry 202 (or Memory Controller 104) can receive from host computer system 1000
Individual reading instructs (also referred to as second reads instruction).Logical address 620 is read in this second reading instruction instruction, and (also referred to as second logically
Location).Whether the first decision logic address 620 of memory management circuitry 202 (or Memory Controller 104) meeting is at preset range 630
In.If logical address 620 is in preset range 630, memory management circuitry 202 (or Memory Controller 104) also can judge
Whether logical address 620 is the initial logical address (that is, logical address 450 (5)) of logic scope 610.If logical address 620 is
Logical address 450 (5), then memory management circuitry 202 (or Memory Controller 104) can read from buffer storage 252
Belong to the data of logical address 620, and send these data to host computer system 1000.
On the other hand, if logical address 620 but is not logical address 450 (5) in preset range 630, then memorizer pipe
Reason circuit 202 (or Memory Controller 104) can maintain the data belonging to logic scope 610 in buffer storage 252 and
Start a timer.The present invention is not limiting as realizing this timer by software or the mode of hardware.Although here, main frame system
System 1000 is currently without logical address 450 (5) to be read, but due to logical address 620 also in preset range 630, therefore leads
Machine system 1000 likely can read logical address 450 (5) within ensuing a period of time again.So, memorizer management electricity
Road 202 (or Memory Controller 104) just can't be removed in buffer storage 252 after obtaining the second reading instruction and be belonged to
The data of logic scope 610.But, if the numerical value that this timer is recorded is more than marginal value, then a memory management circuitry
202 (or Memory Controllers 104) can remove the data belonging to logic scope 610 in buffer storage 252.If additionally, logic
Address 620 is not in preset range 630, then memory management circuitry 202 (or Memory Controller 104) also can be removed buffering and deposits
Reservoir 252 belongs to the data of logic scope 610.
After timer is actuated to, if memory management circuitry 202 (or Memory Controller 104) receives independently
The next of machine system 1000 reads instruction (also referred to as third reading instruction fetch), and the logic that this third reading instruction fetch instruction is read
When address (the also referred to as the 3rd logical address) is logical address 450 (5), then memory management circuitry 202 (or Memory Controller
104) this timer can be reset, and send the data belonging to logical address 450 (5) to host computer system 1000.
In other words, memory management circuitry 202 (or Memory Controller 104) can maintain and belong to logic scope 610
Data are in buffer storage 252, until the logical address beyond host computer system 1000 preset range to be read 630 or one
In Preset Time, host computer system 1000 does not the most read logical address 450 (5) (that is, the numerical value that timer is recorded is more than one
Marginal value).In an exemplary embodiment, this marginal value is proportional to of erasable formula non-volatile memory module 106
The reading time.This reads time representation erasable formula non-volatile memory module 106 and performs required for a reading instruction
Time.If it is the biggest that this reads the time, memory management circuitry 202 (or Memory Controller 104) can increase this marginal value, thus
Increase and belong to the data of logic scope 610 and be stored in the time of buffer storage 252.Such as, memory management circuitry 202 (or
Memory Controller 104) can set this marginal value reading time as twice, but the present invention not subject to the limits.
In an exemplary embodiment, memory management circuitry 202 (or Memory Controller 104) can also once transmit genus
In the data of multiple logical addresses to host computer system 1000.Such as, memory management circuitry 202 (or Memory Controller 104)
It is that the reading instruction first receiving and reading logical address 450 (6) receives the reading instruction reading logical address 450 (5) again, and
And the reading instruction reading logical address 450 (6) can first be stored in the middle of instruction array.When judging that host computer system 1000 to be read
When taking logical address 450 (5), memory management circuitry 202 (or Memory Controller 104) can will belong to logical address 450
(5), the data of 450 (6) send host computer system 1000 to.In an exemplary embodiment, logical address 450 (5), 450 will be belonged to
(6) data send the step of host computer system 1000 to and can also be performed by another circuit (not shown), and the present invention is not
Limit at this.
In this exemplary embodiment, the size of logic scope 610 is big equal to the storage space of buffer storage 252
Little.But in another exemplary embodiment, the size of logic scope 610 might be less that the storage space of buffer storage 252
Size, the present invention is the most not subject to the limits.Further, when logical address 620 is logical address 450 (5), and logical address is belonged to
After the data of 450 (5) have been transmitted to host computer system 1000, memory management circuitry 202 (or Memory Controller 104) is also
Pre-read the number of logic scope 640 (the also referred to as second logic scope) can be belonged to from entity erasing unit 304 (0)～304 (R)
According to buffer storage 252.Logic scope 640 be connected at logic scope 610 after, but the present invention is not limiting as logic scope
The size of 640.Such as, if memory management circuitry 202 (or Memory Controller 104) once will belong to logical address 450
(5), the data of 450 (6) send host computer system 1000 to, then logic scope 640 can include two logical addresses.But,
In another exemplary embodiment, memory management circuitry 202 (or Memory Controller 104) can also read in host computer system 1000
During to logical address 450 (F) or other logical address, pre-read belongs to the data of logic scope 640, and the present invention is not at this
Limit.
In this exemplary embodiment, logic scope 610 be connected at logical address 450 (0)～450 (4) after.But,
In other exemplary embodiment, logic scope 610 can also be before logical address 450 (0)～450 (4).For example, main
Machine system 1000 is to read continuous print logical address from big to small, therefore performed multiple logical address be continuous print read
After instruction, the logic scope 610 of memory management circuitry 202 (or Memory Controller 104) institute pre-read can at these even
Before continuous logical address.Further, logic scope 640 can be before logic scope 610.
Fig. 6 B is to illustrate, according to an exemplary embodiment, the system flow chart judging that pre-reading data is later.
Refer to Fig. 6 B, in step S602, memory management circuitry 202 (or Memory Controller 104) can pre-read
Belong to the data of logic scope 610 to buffer storage 252.
In step s 604, memory management circuitry 202 (or Memory Controller 104) can receive one and read instruction,
And this reads instruction instruction and reads logical address 620.
In step S606, memory management circuitry 202 (or Memory Controller 104) can judge this logical address 620
Whether in preset range 630.
If the result of step S606 is no, in step S608, memory management circuitry 202 (or Memory Controller
104) removing buffer storage 252 belongs to the data of logic scope 610.
If the result of step S606 is yes, in step S610, memory management circuitry 202 (or Memory Controller
104) whether decision logic address 620 is the initial logical address 450 (5) of logic scope 610.
If the result of step S610 is no, in step S612, memory management circuitry 202 (or Memory Controller
104) waiting for a period of time, if exceeding this time, removing the data belonging to logic scope 610 in buffer storage 252.
If the result of step S610 is yes, in step S614, memory management circuitry 202 (or Memory Controller
104) data belonging to logical address 620 can be sent to host computer system 1000.
[the second exemplary embodiment]
Second exemplary embodiment is similar with the first exemplary embodiment, only describes difference at this.Refer to Fig. 6 A,
In one exemplary embodiment, memory management circuitry 202 (or Memory Controller 104) is to be logical address in logical address 620
Host computer system is transferred data to when 450 (5).But in the second exemplary embodiment, memory management circuitry 202 (or memorizer control
Device 104 processed) can just transfer data to main frame when logical address 620 is any one logical address in logic scope 610
System 1000.
Specifically, belong to the data of logic scope 610 in pre-read and receive the reading of reading logical address 620
After instruction, whether memory management circuitry 202 (or Memory Controller 104) meeting decision logic address 620 is at preset range
Within 630.If logical address 620 is not within preset range 630, memory management circuitry 202 (or Memory Controller 104)
The data belonging to logic scope 610 in buffer storage 252 can be removed.If logical address 620 is within logic scope 630,
Whether memory management circuitry 202 (or Memory Controller 104) meeting decision logic address 620 again is in logic scope 610.If
Logical address 620 is in logic scope 610, then memory management circuitry 202 (or Memory Controller 104) can be patrolled belonging to
The data collecting address 620 send host computer system 1000 to.If logical address 620 is within preset range 630 but not at logic model
Within enclosing 610, then memory management circuitry 202 (or Memory Controller 104) can maintain the data belonging to logic scope 610 to exist
In buffer storage 252 and start timer.If the numerical value that this timer is recorded is more than marginal value, memory management circuitry
202 (or Memory Controllers 104) can remove the data belonging to logic scope 610 in buffer storage 252.
Fig. 7 is the flow chart illustrating method for reading data according to an exemplary embodiment.It should be noted that shown in Fig. 7
Flow chart can arrange in pairs or groups the first exemplary embodiment or the second exemplary embodiment is implemented together, or individually implements, and the present invention is not
Limit at this.
Refer to Fig. 7, in step S702, memory management circuitry 202 (or Memory Controller 104) can configure multiple
Logical address is to map to the entity erasing unit of part.
In step S704, memory management circuitry 202 (or Memory Controller 104) can receive from host computer system
Multiple reading instructs and performs these reading instructions.Wherein these read instruction instruction and read multiple first logical addresses.
In step S706, memory management circuitry 202 (or Memory Controller 104) can judge that the first logical address is
No is continuous.If the result of step S706 is no, memory management circuitry 202 (or Memory Controller 104) can return to step
S704, receives the next one and reads instruction and judge that n be finished reading instructs logical address to be read and be
No is continuous.If the result of step S706 is yes, memory management circuitry 202 (or Memory Controller 104) can carry out step
S708。
In step S708, memory management circuitry 202 (or Memory Controller 104) can be pre-from entity erasing unit
Read and belong to the data of a logic scope in a buffer storage.This buffer storage can be only fitted to memorizer control
Within device 104 or outside.
In Fig. 7, each step has described in detail as above, just repeats no more at this.On the other hand, in Fig. 7, each step can be implemented
For multiple procedure codes or circuit, the present invention is not limiting as coming the digital independent shown in implementation Fig. 7 by the mode of software or hardware
Method.
In sum, method for reading data, Memory Controller and the memory storage apparatus that the embodiment of the present invention proposes
May determine that whether host computer system is read out continuous print logical address, thus determine whether to pre-reading data.Further, can root
According to the next logical address to be read of host computer system (or in instruction array one read the logic that instruction is to be read
Address) whether in a preset range, thus determine whether to maintain in buffer storage the data pre-read.So
One, the speed reading data can be increased.
Last it is noted that various embodiments above is only in order to illustrate technical scheme, it is not intended to limit；To the greatest extent
The present invention has been described in detail by pipe with reference to foregoing embodiments, it will be understood by those within the art that: it depends on
So the technical scheme described in foregoing embodiments can be modified, or the most some or all of technical characteristic is entered
Row equivalent；And these amendments or replacement, do not make the essence of appropriate technical solution depart from various embodiments of the present invention technology
The scope of scheme.
Claims (26)
1. a method for reading data, for an erasable formula non-volatile memory module, it is characterised in that this erasable formula
Non-volatile memory module includes that multiple entity wipes unit, and this method for reading data includes:
Configure multiple logical address to map to those entities erasing unit of part；
Receiving and read instruction from multiple the first of a host computer system, wherein those logics are read in those the first reading instruction instructions
Multiple first logical addresses in address；
Perform those the first reading instructions；
Sort those those first logical addresses indicated by the first reading instruction；
Judge whether those first logical addresses are continuous；
If those first logical addresses are continuously, from those entities erasing unit, pre-read belongs in those logical addresses one the
The data of one logic scope are to a buffer storage；And
If those first logical addresses are non-for consecutive hours, reception next one reading instruction.
Method for reading data the most according to claim 1, it is characterised in that also include:
Receiving the one second reading instruction coming from this host computer system, wherein this second reading instruction instruction reads those logically
One second logical address in location；
In judging this second logical address preset range whether in those logical addresses, wherein this preset range includes this
First logic scope；
If this second logical address is in this preset range, it is judged that whether this second logical address is the one of this first logic scope
Initial logical address；And
If this second logical address is this initial logical address, then transmits and belong to the data of this second logical address to this main frame system
System.
Method for reading data the most according to claim 2, it is characterised in that also include:
If this second logical address is this initial logical address, from those entities erasing unit, pre-read belongs to those logically
In location, the data of one second logic scope are in this buffer storage, and wherein this second logic scope is to be connected at this first logic
After scope.
Method for reading data the most according to claim 2, it is characterised in that also include:
If this second logical address is not this initial logical address, the data belonging to this first logic scope are maintained to deposit in this buffering
In reservoir and start a timer；And
If the numerical value that this timer is recorded is more than a marginal value, removes and this buffer storage belongs to this first logic scope
Data.
Method for reading data the most according to claim 4, it is characterised in that this marginal value is proportional to this erasable Shi Feiyi
The one reading time of the property lost memory module.
Method for reading data the most according to claim 4, it is characterised in that also include:
Receiving the third reading instruction fetch coming from this host computer system, wherein this third reading instruction fetch instruction reads those logically
One the 3rd logical address in location；And
If the 3rd logical address is this initial logical address, resets this timer and transmission belongs to the 3rd logical address
Data are to this host computer system.
Method for reading data the most according to claim 2, it is characterised in that also include:
If this second logical address is not in this preset range, remove the number belonging to this first logic scope in this buffer storage
According to.
Method for reading data the most according to claim 1, it is characterised in that also include:
Receiving the one second reading instruction coming from this host computer system, wherein this second reading instruction instruction reads those logically
One second logical address in location；
In judging this second logical address preset range whether in those logical addresses, wherein this preset range includes this
First logic scope；
If this second logical address is in this preset range, it is judged that whether this second logical address is in this first logic scope；
And
If this second logical address is in this first logic scope, transmits and belong to the data of this second logical address to this main frame system
System.
Method for reading data the most according to claim 8, it is characterised in that also include:
If this second logical address is not in this first logic scope, maintains and belong to the data of this first logic scope in this buffering
In memorizer and start a timer；And
If the numerical value that this timer is recorded is more than a marginal value, removes and this buffer storage belongs to this first logic scope
Data.
Method for reading data the most according to claim 1, it is characterised in that the size of this first logic scope is equal to being somebody's turn to do
The size of one storage space of buffer storage.
11. 1 kinds of memory storage apparatus, it is characterised in that including:
A connector, is electrically connected to a host computer system；
One erasable formula non-volatile memory module, wipes unit including multiple entities；And
One Memory Controller, is electrically connected to this adapter and this erasable formula non-volatile memory module, in order to configure
Multiple logical addresses are to map to those entities erasing unit of part, and receive multiple first readings from this host computer system
Instruction fetch, wherein multiple first logical addresses in those logical addresses are read in those the first reading instruction instructions,
Wherein, this Memory Controller is also in order to perform those the first reading instructions, and those the first reading instructions of sorting are indicated
Those first logical addresses, and judge whether those first logical addresses are continuous,
If those first logical addresses are continuously, this Memory Controller also belongs in order to pre-read from those entities erasing unit
In those logical addresses, the data of one first logic scope are to a buffer storage,
If those first logical addresses are non-for consecutive hours, this Memory Controller also next reads instruction in order to receiving.
12. memory storage apparatus according to claim 11, it is characterised in that this Memory Controller is also in order to receive
Coming from one second reading instruction of this host computer system, wherein in those logical addresses is read in this second reading instruction instruction
Second logical address,
In this Memory Controller is also in order to judge this second logical address preset range whether in those logical addresses,
Wherein this preset range includes this first logic scope,
If this second logical address is in this preset range, whether this Memory Controller is also in order to judge this second logical address
For an initial logical address of this first logic scope,
If this second logical address is this initial logical address, this Memory Controller also belongs to this second logically in order to transmitting
The data of location give this host computer system.
13. memory storage apparatus according to claim 12, it is characterised in that if this second logical address is not for this
Beginning logical address, this Memory Controller also in order to maintain the data belonging to this first logic scope in this buffer storage also
And start a timer,
If the numerical value that this timer is recorded is more than a marginal value, this Memory Controller is also in order to remove this buffer storage
In belong to the data of this first logic scope.
14. memory storage apparatus according to claim 13, it is characterised in that this Memory Controller is also in order to receive
Coming from a third reading instruction fetch of this host computer system, wherein in those logical addresses is read in this third reading instruction fetch instruction
3rd logical address,
If the 3rd logical address is this initial logical address, this Memory Controller is also in order to reset this timer and to transmit
Belong to the data of the 3rd logical address to this host computer system.
15. memory storage apparatus according to claim 11, it is characterised in that this Memory Controller is also in order to receive
Coming from one second reading instruction of this host computer system, wherein in those logical addresses is read in this second reading instruction instruction
Second logical address,
In this Memory Controller is also in order to judge this second logical address preset range whether in those logical addresses,
Wherein this preset range includes this first logic scope,
If this second logical address is in this preset range, whether this Memory Controller is also in order to judge this second logical address
In this first logic scope,
If this second logical address is in this first logic scope, this Memory Controller also belongs to this second logic in order to transmitting
The data of address give this host computer system.
16. memory storage apparatus according to claim 15, it is characterised in that if this second logical address not this
In one logic scope, this Memory Controller is also in order to maintain the data belonging to this first logic scope in this buffer storage
And start a timer,
If the numerical value that this timer is recorded is more than a marginal value, this Memory Controller is also in order to remove this buffer storage
In belong to the data of this first logic scope.
17. 1 kinds of Memory Controllers, it is characterised in that for controlling an erasable formula non-volatile memory module, this is deposited
Memory controller includes:
One HPI, is electrically connected to a host computer system；
One memory interface, is electrically connected to this erasable formula non-volatile memory module, and wherein this erasable formula is non-
Volatile includes that multiple entity wipes unit；And
One memory management circuitry, is electrically connected to this HPI and this memory interface, in order to configure multiple logical address
To map to those entities erasing unit of part, and receive the multiple first reading instructions from this host computer system, wherein
Multiple first logical addresses in those logical addresses are read in those the first reading instruction instructions,
Wherein, this memory management circuitry is also in order to perform those the first reading instructions, and sort those the first reading instruction indications
Those first logical addresses shown, and judge whether those first logical addresses are continuous,
If those first logical addresses are continuously, this memory management circuitry is also in order to pre-read from those entities erasing unit
Belong in those logical addresses the data of one first logic scope to a buffer storage,
If those first logical addresses are non-for consecutive hours, this memory management circuitry also next reads instruction in order to receiving.
18. Memory Controllers according to claim 17, it is characterised in that this memory management circuitry is also in order to receive
Coming from one second reading instruction of this host computer system, wherein in those logical addresses is read in this second reading instruction instruction
Second logical address,
This memory management circuitry is also in order to judge this second logical address preset range whether in those logical addresses
In, wherein this preset range includes this first logic scope,
If this second logical address is in this preset range, this memory management circuitry is also in order to judge that this second logical address is
A no initial logical address for this first logic scope,
If this second logical address is this initial logical address, this memory management circuitry also belongs to this second logic in order to transmitting
The data of address give this host computer system.
19. Memory Controllers according to claim 18, it is characterised in that if to be this initial patrols for this second logical address
Volume address, this memory management circuitry also belongs in those logical addresses one the in order to pre-read from those entities erasing unit
The data of two logic scopes in this buffer storage, wherein this second logic scope be connected at this first logic scope it
After.
20. Memory Controllers according to claim 18, it is characterised in that if this second logical address does not initiates for this
Logical address, this memory management circuitry also in order to maintain the data belonging to this first logic scope in this buffer storage also
And start a timer,
If the numerical value that this timer is recorded is more than a marginal value, this memory management circuitry is also in order to remove this buffer-stored
Device belongs to the data of this first logic scope.
21. Memory Controllers according to claim 20, it is characterised in that wherein to be proportional to this erasable for this marginal value
The one reading time of formula non-volatile memory module.
22. Memory Controllers according to claim 20, it is characterised in that this memory management circuitry is also in order to receive
Coming from a third reading instruction fetch of this host computer system, wherein in those logical addresses is read in this third reading instruction fetch instruction
3rd logical address,
If the 3rd logical address is this initial logical address, this memory management circuitry is also in order to reset this timer and to pass
Send the data belonging to the 3rd logical address to this host computer system.
23. Memory Controllers according to claim 18, it is characterised in that if this second logical address does not makes a reservation at this
In the range of, this memory management circuitry is also in order to remove the data belonging to this first logic scope in this buffer storage.
24. Memory Controllers according to claim 17, it is characterised in that this memory management circuitry is also in order to receive
Coming from one second reading instruction of this host computer system, wherein in those logical addresses is read in this second reading instruction instruction
Second logical address,
This memory management circuitry is also in order to judge this second logical address preset range whether in those logical addresses
In, wherein this preset range includes this first logic scope,
If this second logical address is in this preset range, this memory management circuitry is also in order to judge that this second logical address is
It is no in this first logic scope,
If this second logical address is in this first logic scope, this memory management circuitry also belongs to this and second patrols in order to transmitting
Collect the data of address to this host computer system.
25. Memory Controllers according to claim 24, it is characterised in that if this second logical address not this first
In logic scope, this memory management circuitry is also in order to maintain the data belonging to this first logic scope in this buffer storage
And start a timer,
If the numerical value that this timer is recorded is more than a marginal value, this memory management circuitry is also in order to remove this buffer-stored
Device belongs to the data of this first logic scope.
26. Memory Controllers according to claim 25, it is characterised in that the size of this first logic scope is equal to being somebody's turn to do
The size of one storage space of buffer storage.
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| KR20160104387A (en) * | 2015-02-26 | 2016-09-05 | 에스케이하이닉스 주식회사 | Data storage device and operating method thereof |
| US10970226B2 (en) | 2017-10-06 | 2021-04-06 | Silicon Motion, Inc. | Method for performing access management in a memory device, associated memory device and controller thereof, and associated electronic device |
| TWI662410B (en) * | 2017-12-18 | 2019-06-11 | 慧榮科技股份有限公司 | Data storage device and methods for processing data in the data storage device |
| CN110286846B (en) * | 2018-03-19 | 2023-03-14 | 深圳大心电子科技有限公司 | Data moving method and storage controller |
| CN116504293B (en) * | 2023-06-27 | 2023-10-13 | 芯天下技术股份有限公司 | Method and device for reading non flash, memory chip and equipment |
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