CN103928332B - Transistor and forming method thereof - Google Patents
Transistor and forming method thereof Download PDFInfo
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- CN103928332B CN103928332B CN201310011753.8A CN201310011753A CN103928332B CN 103928332 B CN103928332 B CN 103928332B CN 201310011753 A CN201310011753 A CN 201310011753A CN 103928332 B CN103928332 B CN 103928332B
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- 238000000034 method Methods 0.000 title claims abstract description 56
- 239000000758 substrate Substances 0.000 claims abstract description 73
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 50
- 229920005591 polysilicon Polymers 0.000 claims description 41
- 230000003647 oxidation Effects 0.000 claims description 30
- 238000007254 oxidation reaction Methods 0.000 claims description 30
- 239000000463 material Substances 0.000 claims description 25
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 18
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 16
- 229910052710 silicon Inorganic materials 0.000 claims description 16
- 239000010703 silicon Substances 0.000 claims description 13
- 238000005530 etching Methods 0.000 claims description 11
- 239000002210 silicon-based material Substances 0.000 claims description 10
- 239000013078 crystal Substances 0.000 claims description 7
- 239000000377 silicon dioxide Substances 0.000 claims description 7
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 5
- 230000008859 change Effects 0.000 claims description 5
- 239000001301 oxygen Substances 0.000 claims description 5
- 229910052760 oxygen Inorganic materials 0.000 claims description 5
- 230000008569 process Effects 0.000 claims description 5
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 4
- 238000001020 plasma etching Methods 0.000 claims description 3
- 238000001039 wet etching Methods 0.000 claims description 3
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims 2
- 229910052757 nitrogen Inorganic materials 0.000 claims 1
- 239000004065 semiconductor Substances 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 230000008901 benefit Effects 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 125000004430 oxygen atom Chemical group O* 0.000 description 3
- 125000006850 spacer group Chemical group 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 239000000654 additive Substances 0.000 description 1
- 230000000996 additive effect Effects 0.000 description 1
- 230000005465 channeling Effects 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- -1 form groove Substances 0.000 description 1
- 229910052736 halogen Inorganic materials 0.000 description 1
- 150000002367 halogens Chemical class 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000003701 mechanical milling Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000007430 reference method Methods 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Abstract
A kind of transistor and forming method thereof, wherein, transistor includes: the second substrate；The second oxide layer being positioned on the second substrate；It is positioned at the backgate in the second oxide layer, described backgate is formed with opening；Being positioned at the first oxide layer of open bottom, the upper surface of described first oxide layer is less than the upper surface of described opening both sides backgate；It is positioned at the 4th oxide layer in the backgate of described opening both sides；Backgate dielectric layer, active area and the top gate medium layer being positioned in the first oxide layer and set gradually to center by opening sidewalls；Being positioned at backgate dielectric layer, active area and the side wall at top gate medium layer top, the upper surface of described side wall is higher than described 4th oxide layer；Top-gated in the first oxide layer between top gate medium layer and side wall and part the 4th oxide layer.Transistor layout provided by the present invention is compact, and the size of single transistor is less.
Description
Technical field
The present invention relates to field of semiconductor manufacture, particularly relate to a kind of transistor and forming method thereof.
Background technology
In order to catch up with the step of Moore's Law, people have to the spy constantly reducing mosfet transistor
Levy size.Do so can bring the benefits such as increase chip density, the switching speed of raising MOSFET.
But along with the shortening of transistor channel length, the distance with source electrode that drains shortens the most therewith, so grid
Extremely being deteriorated the control ability of raceway groove, the difficulty of grid voltage pinch off (pinch off) raceway groove is the most increasing,
Such Asia threshold values electric leakage (Subthreshold leakage) phenomenon that just makes, the most so-called short-channel effect (SCE:
Short-channel effects) it is easier to occur.
Due to such reason, planar CMOS transistor is gradually to three-dimensional (3D) fin field effect crystal
Pipe (Fin Field Effect Transistor, FinFET) device architecture transition.In FinFET, stand upright on
Fin-shaped channel on silicon-on-insulator (SOI) instead of the planar channeling in traditional cmos, and grid is formed
On fin-shaped channel and around fin-shaped channel, using the teaching of the invention it is possible to provide highly efficient static control ability, and then very
Good suppression short-channel effect.And other device has holding concurrently of more preferable integrated circuit production technology relatively
Capacitive.
Along with the continuous reduction of FinFET size, the control to FinFET threshold voltage vt becomes more difficult,
The especially disturbance of dopant makes the problems referred to above the most prominent.One of result of the above problems be
FinFET is formed back grid structure.But, back grid structure needs to take bigger chip area, is unfavorable for
The control of transistor size, is also unfavorable for the raising of semiconductor devices integrated level.
Therefore, in the case of device density constantly increases in the semiconductor device, how at limited chip
Arrange the back grid structure of FinFET under area, simplify the layout of formed transistor, to reduce single crystal
The size of pipe becomes one of those skilled in the art's problem demanding prompt solution.
The technology of more three-dimensional FinFET refer to the U.S. Patent application of Publication No. US6800885B1.
Summary of the invention
The problem that the present invention solves is to provide a kind of transistor and forming method thereof, simplifies formed transistor
Layout, reduce single transistor size.
For solving the problems referred to above, the invention provides the forming method of a kind of transistor, including:
There is provided substrate, described substrate include the most successively the second substrate, the second oxide layer, more than first
Crystal silicon layer, the first oxide layer and the first substrate；
Described first substrate is formed mask layer, and on the sidewall of described mask layer, forms side wall；
With the side wall on described mask layer and mask layer sidewall as mask, to the first substrate and the first oxygen
Change layer to perform etching, to exposing the first polysilicon layer；
Carry out the first oxidation technology, formed and cover the backgate dielectric layer of the sidewall of the first substrate below side wall；
Side wall both sides the first polysilicon layer forms the second polysilicon layer, described second polysilicon layer upper
Surface is less than the upper surface of described mask layer；
Carry out the second oxidation technology, form the 4th oxide layer on the second polysilicon layer surface, and formation includes
First polysilicon layer and be positioned at the backgate of the second polysilicon layer below the 4th oxide layer；
With the 4th oxide layer and side wall as mask, remove the first lining below described mask layer and mask layer
The end, to exposing described first oxide layer, form groove；
Carry out the 3rd oxidation technology, form top gate medium layer and the position covering the first substrate in recess sidewall
The active area in the first oxide layer between backgate dielectric layer and top gate medium layer；
The first oxide layer, side wall and side wall two side portions the 4th oxidation between described top gate medium layer
Top-gated is formed on Ceng.
Further, present invention also offers a kind of transistor, including:
Second substrate；
The second oxide layer being positioned on the second substrate；
It is positioned at the backgate in the second oxide layer, described backgate is formed with opening；
Being positioned at the first oxide layer of open bottom, the upper surface of described first oxide layer is less than described opening two
The upper surface of side backgate；
It is positioned at the 4th oxide layer in the backgate of described opening both sides；
The backgate dielectric layer that is positioned in the first oxide layer and set gradually to center by opening sidewalls, active area
With top gate medium layer；
It is positioned at backgate dielectric layer, active area and the side wall at top gate medium layer top, the upper surface of described side wall
It is not less than described 4th oxide layer；
Top in the first oxide layer between top gate medium layer and side wall and part the 4th oxide layer
Grid.
Compared with prior art, technical solution of the present invention has the advantage that
Including the second substrate, the second oxide layer, the first polysilicon layer, the first oxidation the most successively
After the substrate of layer and the first substrate is formed, form sidewall on the first substrate and be formed with the mask layer of side wall also
First substrate and the first oxide layer are performed etching with it for mask, to exposing the first polysilicon layer；Connect
, formed and cover the backgate dielectric layer of the sidewall of the first substrate below side wall, and in side wall both sides more than first
Form the second polycrystalline silicon material on crystal silicon layer, and form covering the second polycrystalline by the second oxidation technology
4th oxide layer of silicon surface and include the first polysilicon layer and be positioned at second below the 4th oxide layer
The backgate of polysilicon layer；Followed by, removal mask layer and below the first substrate, form groove, and lead to
Cross the 3rd oxidation technology the first substrate surface in recess sidewall form top gate medium layer and be positioned at backgate
Active area between dielectric layer and top gate medium layer；Last the first oxide layer between top gate medium layer,
Top-gated is formed on side wall and side wall two side portions the 4th oxide layer.By what above-mentioned technique was formed, there is the back of the body
The transistor layout of grid structure is compact, and the size of single transistor is little.
Furthermore, it is possible to control backgate dielectric layer and top respectively by the first oxidation technology and the 3rd oxidation technology
The thickness of gate dielectric layer, and then the threshold voltage of formed transistor can be controlled more flexibly and effectively.
Accompanying drawing explanation
Fig. 1～Figure 11 is the schematic diagram of forming method one embodiment of transistor of the present invention；
Figure 12 is the schematic diagram of transistor one embodiment of the present invention.
Detailed description of the invention
Understandable, below in conjunction with the accompanying drawings for enabling the above-mentioned purpose of the present invention, feature and advantage to become apparent from
The detailed description of the invention of the present invention is described in detail.
Elaborate a lot of detail in the following description so that fully understanding the present invention, but this
Bright other can also be used to be different from alternate manner described here implement, therefore the present invention is not by following
The restriction of disclosed specific embodiment.
Hereinafter, for demonstration purpose, product embodiments reference method embodiment describes.But, it should
Understand that in the present invention, the realization of product and method is independent mutually.It is to say, disclosed product embodiments
Can prepare according to additive method, disclosed embodiment of the method is not limited only to realize product embodiments.
The most as described in the background section, existing technique has the FinFET chip occupying area of backgate relatively
Greatly, the size of transistor is relatively big, is unfavorable for the raising of semiconductor devices integrated level.
For drawbacks described above, the invention provides a kind of transistor and forming method thereof, by two transistors
Share top-gated and make its backgate connect, and the first substrate between backgate dielectric layer and top gate medium layer is made
For the active area of transistor, simplify the layout of formed transistor, and due to backgate dielectric layer and top-gated
Between dielectric layer, the active region area of transistor is less, further reduces the chi of formed single transistor
Very little, the beneficially raising of semiconductor devices integrated level.
It is described in detail below in conjunction with the accompanying drawings.
With reference to Fig. 1～Figure 11, by specific embodiment, the forming method of transistor of the present invention is done furtherly
Bright.
With reference to Fig. 1, it is provided that the first substrate 100a, described first substrate 100a have first surface I and with
Second surface II relative for first surface I.The first surface I of described first substrate 100a is formed the
One oxide layer 102a, and in the first oxide layer 102a, form the first polysilicon layer 104a.
With continued reference to Fig. 1, it is provided that the second substrate 200, and form the second oxygen on described second substrate 200
Change layer 202.
In the present embodiment, the material of described first substrate 100a and the second substrate 200 is silicon.Formed described
The method of the first oxide layer 102a and the second oxide layer 202 can be chemical vapor deposition method or thermal oxide
Technique.
With reference to Fig. 2, the first polysilicon layer 104a in Fig. 1 is bound to the surface of the second oxide layer 202.
In the present embodiment, the method that the first polysilicon layer 104a is bound to the surface of the second oxide layer 202
Can be wafer bonding technique, its concrete technology be well known to those skilled in the art, and does not repeats them here.
With reference to Fig. 3, the second surface II of the first substrate 100a in Fig. 2 is carried out thinning, make thinning after
The thickness of the first substrate 100b reaches predetermined thickness.
In the present embodiment, any wafer thinning technique well-known to those skilled in the art can be used first
The second surface II of substrate 100a carries out thinning, and the present invention is without limitation.The first substrate after thinning
The thickness of 100b is 50nm～500nm.
With continued reference to Fig. 3, the first substrate 100b after thinning forms mask material 106a.
In the present embodiment, the material of described mask material 106a is silicon nitride, forms mask material 106a
Method can be chemical vapor deposition method.
With reference to Fig. 4, mask material 106a described in etching Fig. 3, to exposing part the first substrate 100b,
Form mask layer 106b.
In the present embodiment, described in etching Fig. 3, the method for mask material 106a can comprise the steps:
Formation photoresist layer (not shown) on the most described mask material 106a, and by exposing,
Developing process forms litho pattern in described photoresist layer, described litho pattern be subsequently formed mask layer
Position and shape corresponding；
Be formed with litho pattern photoresist layer as mask, etch described mask material 106a, to expose
Go out part the first substrate 100b, form mask layer 106b；
Remove described photoresist layer.
With continued reference to Fig. 4, form the side wall 108 covering described mask layer 106b sidewall.
In the present embodiment, the material of described side wall 108 can be silica, silicon oxynitride or silicon oxide carbide.
Form described side wall 108 can comprise the steps:
Shape on the first substrate 100b of the top of mask layer 106b and sidewall and mask layer 106b both sides
Become spacer material (not shown)；
By anisotropic dry etch process, described spacer material is performed etching, remove mask layer 106b
Spacer material on top and the first substrate 100b, the side wall 108 on residue mask layer 106b sidewall.
In the present embodiment, described mask layer 106b and side wall 108 are for protecting below in subsequent technique
The first substrate 100b, described side wall 108 is for determining two active areas of transistor.
With reference to Fig. 5, with the side wall 108 on described mask layer 106b and mask layer 106b sidewall as mask,
The first substrate 100b after thinning and the first oxide layer 102a are performed etching, to exposing more than first
Crystal silicon layer 104a, is positioned on mask layer 106b and sidewall thereof the first substrate below side wall 108 with residue
100c and the first oxide layer 102b.
In the present embodiment, the method performing etching the first substrate 100b and the first oxide layer 102a is
Reactive ion etching process, its concrete etching technics is well known to those skilled in the art, the most superfluous at this
State.
With reference to Fig. 6, carry out the first oxidation technology, make in Fig. 5 the first substrate 100c side below side wall 108
On wall, silicon atom is combined with oxygen atom, forms the backgate dielectric layer covering the first substrate 100d sidewall in Fig. 6
110。
In the present embodiment, described first oxidation technology can be thermal oxidation technology, and its concrete technology is this area
Known to technical staff, do not repeat them here.Formed backgate is controlled by controlling the first oxidation technology
The thickness of dielectric layer 110, is beneficial to the control to formed transistor threshold voltage.
It should be noted that formed while backgate dielectric layer 110, side wall 108 both sides the in Fig. 5
The silicon atom on one polysilicon layer 104a surface is also combined with oxygen atom, defines and covers the first polycrystalline in Fig. 6
3rd oxide layer 112 of silicon layer 104b.
With reference to Fig. 7, remove the 3rd oxide layer 112 described in Fig. 6.
In the present embodiment, the method removing the 3rd oxide layer 112 is anisotropic dry etch, and it is concrete
Etching technics is well known to those skilled in the art, and does not repeats them here.
With reference to Fig. 8, the first polysilicon layer 104b surface in side wall 108 both sides forms the second polycrystalline in the figure 7
Silicon layer 114, and form the 4th oxide layer 116, described second polysilicon on the second polysilicon layer 114 surface
The upper surface of layer 114 upper surface less than described mask layer 106b.
In the present embodiment, form described second polysilicon layer 114 and surface the 4th oxide layer 116 can be wrapped
Include following steps:
(figure is not to form polycrystalline silicon material on mask layer 106b, side wall 108 and the first polysilicon layer 104b
Show)；
Planarize described polycrystalline silicon material, to exposing described mask layer 106b, make the polycrystalline after planarization
The upper surface of silicon materials and the upper surface flush of mask layer 106b；
Carry out back carving to the polycrystalline silicon material after planarization, form the second polysilicon layer, described second polycrystalline
The upper surface of the silicon layer upper surface less than mask layer 106b；
Carry out the second oxidation technology, make the silicon atom on the second polysilicon layer surface be combined with oxygen atom, formed
4th oxide layer 116, concurrently form include being positioned at below the 4th oxide layer 116 second polysilicon layer 114 with
And first backgate of polysilicon layer 104b.
Concrete, the method planarizing described polycrystalline silicon material can be chemical mechanical milling tech.To smooth
The method that polycrystalline silicon material after change carries out back carving can be wet-etching technology, carries out described second oxidation work
The method of skill can be thermal oxidation technology.
With reference to Fig. 9, in Fig. 8, the 4th oxide layer 116 and side wall 108 are as mask, remove described mask layer
The first substrate 100d below 106b and mask layer 106b, to exposing described first oxide layer 102b,
Residue is positioned at the first substrate 100e below side wall 108, forms groove 118.
In the present embodiment, the method removing described mask layer 106b can be wet-etching technology.Remove mask
The method of the first substrate 100d below layer 106b can be reactive ion etching process, as used halogen
The first substrate 100d below base chemical method erosion removal mask layer 106b.
With reference to Figure 10, the first substrate 100e on Fig. 9 further groove 118 sidewall is carried out the 3rd oxidation technology,
Form the top gate medium layer 120 covering groove 118 sidewall, formed by ion implanting simultaneously and be positioned at backgate Jie
Active area 100f in first oxide layer 102b between matter layer 110 and top gate medium layer 120.
In the present embodiment, the method carrying out third time oxidation technology can be thermal oxidation technology.By to the 3rd
Secondary oxidation technology is controlled, and controls the thickness of formed top gate medium layer 120, is beneficial to transistor threshold
The control of threshold voltage.
The area occupied due to active area 100f is less, can effectively reduce the size forming transistor.
With reference to Figure 11, the first oxide layer 102b between top gate medium layer 120, side wall 108 in Fig. 10
And in side wall 108 two side portions the 4th oxide layer 116, form top-gated 122.
In the present embodiment, the method forming top-gated 122 can be chemical vapor deposition method, it is possible to for ability
Field technique personnel other techniques known, it is not intended to protection scope of the present invention.
In above example, transistor active area 100f area is less, and the backgate connection of two transistors
And sharing a top-gated 122, the layout making formed transistor is compacter；And, can be by wherein
The top-gated 122 that the backgate of one transistor and two transistors share respectively arranges a connector, simultaneously to
Two transistors applying voltages, and regulate the threshold voltage of two transistors simultaneously, effectively reduce and set
It is placed in the quantity of connector on single transistor, further reduces the size of formed single transistor, profit
Raising in semiconductor devices integrated level.
Accordingly, with reference to Figure 12, present invention also offers a kind of transistor, including:
Second substrate 300；
The second oxide layer 302 being positioned on the second substrate 300；
It is positioned at the backgate 304 in the second oxide layer 302, described backgate 304 is formed with opening；
Be positioned at the first oxide layer 306 of open bottom, described first oxide layer 306 upper surface be less than described in open
The upper surface of mouth both sides backgate 304；
It is positioned at the 4th oxide layer 308 in described opening both sides backgate 304；
The backgate dielectric layer 310 that is positioned in the first oxide layer 306 and set gradually to center by opening sidewalls,
Active area 312 and top gate medium layer 314；
It is positioned at backgate dielectric layer 310, active area 312 and the side wall 316 at top gate medium layer 314 top, institute
State the upper surface of sidewall 316 higher than described 4th oxide layer 308；
The first oxide layer 306 between top gate medium layer 314 and side wall 316 and part the 4th oxygen
Change the top-gated 318 on layer 308.
In the present embodiment, the material of described active area 312 and top-gated 318 is polysilicon, described first oxygen
The material changing layer the 306, second oxide layer 302 and the 4th oxide layer 308 is silica.Described side wall 316
Material be silica, silicon oxynitride or silicon oxide carbide.
Although the present invention is open as above with preferred embodiment, but it is not for limiting the present invention, appoints
What those skilled in the art without departing from the spirit and scope of the present invention, may be by the disclosure above
Technical solution of the present invention is made possible variation and amendment by method and technology contents, therefore, every does not takes off
From the content of technical solution of the present invention, it is any that above example is made by the technical spirit of the foundation present invention
Simple modification, equivalent variations and modification, belong to the protection domain of technical solution of the present invention.
Claims (15)
1. the forming method of a transistor, it is characterised in that including:
There is provided substrate, described substrate include the most successively the second substrate, the second oxide layer, more than first
Crystal silicon layer, the first oxide layer and the first substrate；
Described first substrate is formed mask layer, and on the sidewall of described mask layer, forms side wall；
With the side wall on described mask layer and mask layer sidewall as mask, to the first substrate and the first oxygen
Change layer to perform etching, to exposing the first polysilicon layer；
Carry out the first oxidation technology, formed and cover the backgate dielectric layer of the first substrate sidewall below side wall；
Side wall both sides the first polysilicon layer forms the second polysilicon layer, described second polysilicon layer upper
Surface is less than the upper surface of described mask layer；
Carry out the second oxidation technology, form the 4th oxide layer on the second polysilicon layer surface, and formation includes
First polysilicon layer and be positioned at the backgate of the second polysilicon layer below the 4th oxide layer；
With the 4th oxide layer and side wall as mask, remove the first lining below described mask layer and mask layer
The end, to exposing described first oxide layer, form groove；
Carry out the 3rd oxidation technology, form top gate medium layer and the position covering the first substrate in recess sidewall
The active area in the first oxide layer between backgate dielectric layer and top gate medium layer；
The first oxide layer, side wall and side wall two side portions the 4th oxidation between described top gate medium layer
Top-gated is formed on Ceng.
2. the forming method of transistor as claimed in claim 1, forms described substrate and includes:
The first substrate, described first substrate is provided to have first surface and second surface on the other side；
The first surface of the first substrate is formed the first oxide layer, and in the first oxide layer, forms first
Polysilicon layer；
Second substrate is provided, and forms the second oxide layer on described second substrate；
First polysilicon layer is bound to the surface of the second oxide layer.
3. the forming method of transistor as claimed in claim 2, it is characterised in that by the first polysilicon layer
After being bound to the surface of the second oxide layer, also include: the second surface of the first substrate is carried out thinning.
4. the forming method of transistor as claimed in claim 1, it is characterised in that carry out the first oxidation technology,
Form the backgate dielectric layer of the first substrate sidewall below covering side wall to include:
Carry out the first oxidation technology, formed cover the first substrate sidewall below side wall backgate dielectric layer and
Cover the 3rd oxide layer on the first polysilicon layer surface, side wall both sides；
Remove described 3rd oxide layer.
5. the forming method of transistor as claimed in claim 1, it is characterised in that on described first substrate
Form mask layer, and formation side wall include on the sidewall of described mask layer:
Form the mask material covering described first substrate；
Etch described mask material, expose part the first substrate, form mask layer；
Form the side wall covering described mask layer sidewall.
6. the forming method of transistor as claimed in claim 1, it is characterised in that in side wall both sides more than first
The second polysilicon layer is formed on crystal silicon layer, including:
Mask layer, side wall and the first polysilicon layer are formed polycrystalline silicon material；
Planarize described polycrystalline silicon material, to exposing described mask layer；
Carry out back carving to the polycrystalline silicon material after planarization, form the second polysilicon layer.
7. the forming method of transistor as claimed in claim 1, it is characterised in that the material of described mask layer
For silicon nitride.
8. the forming method of the transistor as described in claim 1 or 7, it is characterised in that remove described mask
The method of layer is wet-etching technology.
9. the forming method of the transistor as described in claim 1 or 7, it is characterised in that the material of described side wall
Material is silica, silicon oxynitride or silicon oxide carbide.
10. the forming method of transistor as claimed in claim 1, it is characterised in that to the first substrate and the
The method that one oxide layer performs etching is reactive ion etching process.
The forming method of 11. transistors as claimed in claim 1, it is characterised in that described first oxidation technology,
Second oxidation technology and/or the 3rd oxidation technology are thermal oxidation technology.
12. 1 kinds of transistors, including:
Second substrate；
The second oxide layer being positioned on the second substrate；
It is positioned at the backgate in the second oxide layer, described backgate is formed with opening；
Being positioned at the first oxide layer of open bottom, the upper surface of described first oxide layer is less than described opening two
The upper surface of side backgate；
It is characterized in that, also include:
It is positioned at the 4th oxide layer in the backgate of described opening both sides；
The backgate dielectric layer that is positioned in the first oxide layer and set gradually to center by opening sidewalls, active area
With top gate medium layer；
It is positioned at backgate dielectric layer, active area and the side wall at top gate medium layer top, the upper surface of described side wall
Higher than described 4th oxide layer；
Top in the first oxide layer between top gate medium layer and side wall and part the 4th oxide layer
Grid.
13. transistors as claimed in claim 12, it is characterised in that described first oxide layer, the second oxide layer
It is silica with the material of the 4th oxide layer.
14. transistors as claimed in claim 12, it is characterised in that the material of described side wall is silica, nitrogen
Silica or silicon oxide carbide.
15. transistors as claimed in claim 12, it is characterised in that the material of described backgate is polysilicon, institute
The material stating top-gated is polysilicon.
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| CN106847913A (en) * | 2015-12-03 | 2017-06-13 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor devices and forming method thereof |
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