CN103943462A - Method for eliminating load effect generated by thin film deposition - Google Patents
Method for eliminating load effect generated by thin film deposition Download PDFInfo
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- CN103943462A CN103943462A CN201410174773.1A CN201410174773A CN103943462A CN 103943462 A CN103943462 A CN 103943462A CN 201410174773 A CN201410174773 A CN 201410174773A CN 103943462 A CN103943462 A CN 103943462A
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- curb wall
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- 238000000034 method Methods 0.000 title claims abstract description 100
- 230000000694 effects Effects 0.000 title claims abstract description 46
- 238000000427 thin-film deposition Methods 0.000 title abstract description 11
- 239000000758 substrate Substances 0.000 claims description 27
- 229920002120 photoresistant polymer Polymers 0.000 claims description 24
- 238000000059 patterning Methods 0.000 claims description 19
- 239000004065 semiconductor Substances 0.000 claims description 19
- 238000005530 etching Methods 0.000 claims description 17
- 238000002513 implantation Methods 0.000 claims description 14
- 230000035484 reaction time Effects 0.000 claims description 9
- 238000006243 chemical reaction Methods 0.000 claims description 7
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 6
- 229910052731 fluorine Inorganic materials 0.000 claims description 6
- 239000011737 fluorine Substances 0.000 claims description 6
- 239000003595 mist Substances 0.000 claims description 6
- 238000001259 photo etching Methods 0.000 claims description 6
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 4
- 238000011946 reduction process Methods 0.000 claims description 3
- 229910021332 silicide Inorganic materials 0.000 claims description 3
- 239000010409 thin film Substances 0.000 abstract description 3
- 238000002347 injection Methods 0.000 abstract description 2
- 239000007924 injection Substances 0.000 abstract description 2
- 238000001312 dry etching Methods 0.000 abstract 1
- 239000010408 film Substances 0.000 description 32
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 230000006378 damage Effects 0.000 description 3
- 238000005137 deposition process Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000012856 packing Methods 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 208000027418 Wounds and injury Diseases 0.000 description 2
- 238000013459 approach Methods 0.000 description 2
- 230000010485 coping Effects 0.000 description 2
- 208000014674 injury Diseases 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000003667 anti-reflective effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 229940090044 injection Drugs 0.000 description 1
- 238000010297 mechanical methods and process Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
Abstract
The invention provides a method for eliminating a load effect generated by thin films deposited after a short-channel effect is lowered. Firstly, ion injection is carried out by adopting a method for increasing the width of grid side walls, so that the short-channel effect is lowered; then the width of the grid side walls is reduced, and the thin film deposition process is then carried out. The method for reducing the width of the grid side walls comprises the steps of protecting grids and the tops of the grid side walls by utilizing an anti-reflecting layer, defining the width which the grid side walls need to be reduced by utilizing the patterned anti-reflecting layer, and then adopting a dry etching process to etch and thin the grid side walls. Obviously, due to the fact that the width of the grid side walls is reduced, the filling space among the grids is increased, thin film filling capacity among the grids is further improved, and the load effect generated after the thin film deposition is carried out after the existing method of lowering the sort-channel effect is adopted is avoided.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly a kind of removing method reducing the film generation load effect depositing after short-channel effect.
Background technology
Along with process constantly dwindles, 65nm and following particularly, because the width of grid self and side wall thereof further reduces, the Implantation of source-drain area approaches raceway groove (channel) more, causes the short-channel effect of device very obvious.In order to reduce short-channel effect, existing main flow technique is to form in the Semiconductor substrate of grid and grid curb wall, by the modes such as kind that regulate dosage, Implantation Energy, implant angle or the change of the Implantation of source-drain area to inject ion, solves short channel effect problem.But, because Implantation is very large on the impact of device, so it is very little to solve the process window of short-channel effect by Implantation.
In addition, also having a kind of method that solves short channel effect problem, is to increase the distance between Implantation and channel by increasing the width of grid curb wall; Refer to Fig. 1-3, Fig. 1 is for forming grid and grid curb wall substrate cross-section structural representation afterwards, Fig. 2 is for increasing lateral wall width substrate cross-section structural representation afterwards, Fig. 3 is the cross section structure schematic diagram after deposit film on the substrate in Fig. 2, wherein, 1 represents substrate, and 2 represent grid, 3 represent grid curb wall, and 4 represent the film depositing.
Although increase grid curb wall width, can increase the distance between Implantation and channel, yet, because grid curb wall broadens, cause the useful space between grid and grid to diminish, thereby approach at follow-up stress the process window that causes film to be filled in technology (SMT) or metal silicide blocking area (SAB) processing procedure, reduce, carry out occurring load effect after thin film deposition.As shown in Figure 3, much larger than the thickness (thickness between dotted line b and b ') at film 4 tops, there is load effect in the thickness (thickness between dotted line a and a ') of film 4 bottoms that deposit; Distance between side wall 3 reduces, and is easy to cause the film 4 between side wall 3 cannot be deposited on the surface of substrate 1 completely, thereby causes film filling capacity to decline.
Therefore, need to improve existing technique, when continuing to use second method reduction short-channel effect, increase space and film filling capacity between grid, avoid follow-up deposited film to produce load effect.
Summary of the invention
In order to overcome the problems referred to above, the present invention seeks to eliminate the method that occurs load effect in thin film deposition processes after reducing short-channel effect, to when solving short channel effect problem, increase the packing space between grid, avoid follow-up deposited film to produce load effect.
The invention provides a kind of removing method reducing the film generation load effect depositing after short-channel effect, it comprises the following steps:
Step S01: form grid and grid curb wall in Semiconductor substrate;
Step S02: increase the width of described grid curb wall, and described Semiconductor substrate is carried out to source-drain area Implantation;
Step S03: cover one deck anti-reflecting layer in described Semiconductor substrate;
Step S04: at described anti-reflecting layer surface-coated photoresist, adopt photoetching process, photoresist described in patterning forms the pattern that described grid curb wall is wanted weakened region in described photoresist;
Step S05: the described photoresist of patterning of take is masterplate, adopts dry etch process, and anti-reflecting layer described in patterning forms the pattern that described grid curb wall is wanted weakened region in described anti-reflecting layer;
Step S06: the described anti-reflecting layer of patterning of take is mask, through dry etch process, grid curb wall described in attenuate;
Step S07: deposit film in described Semiconductor substrate.
Preferably, in described step S04, after grid curb wall described in attenuate, using plasma dry etch process is removed remaining described photoresist and/or described anti-reflecting layer.
Further, in described plasma dry etch process, utilize pure O
2or SO
2as reacting gas.
Further, the reaction pressure that described plasma dry etch process adopts is 5-15mTorr, and upper electrode power is 500-1500 watt, and bottom electrode voltage is zero, and gas flow is 150-250sccm, and the reaction time is 40-80 second.
Preferably, in described step S05, adopt HBr and O
2mist as reacting gas.Further, in described step S05, described HBr and described O
2flow proportional be 1:1 to 15:2.
Preferably, in described step S05, the reaction pressure adopting is 5-10mTorr, and the upper electrode power adopting is 300-500 watt, and the reaction time is 10-80 second.
Preferably, in described step S06, adopting fluorine is grid curb wall described in gas etching.Further, in described step S06, described fluorine is that gas is CH
2f
2and CHF
3mist.Further, in described step S06, described CH
2f
2with described CHF
3flow proportional be 1:1 to 4:1.
Preferably, in described step S06, the reaction pressure adopting is 20-40mTorr, and the upper electrode power adopting is 500-800 watt, and the bottom electrode voltage adopting is 0, and the reaction time is 10-40 second.
Preferably, in described step S07, described film is to form in stress memory technique or silicide block area processing procedure.
Removing method reducing the film generation load effect depositing after short-channel effect of the present invention, first adopts the width method that increases grid curb wall to carry out Implantation, reduces short-channel effect; Then, reduce the width of grid curb wall, then carry out thin film deposition processes.Reduce the method for grid curb wall width: utilize anti-reflecting layer to protect grid and gate electrode side coping, and utilize the anti-reflecting layer of patterning to define the width that grid curb wall will reduce, then adopt dry etch process etching attenuate grid curb wall.Clearly, because the width of grid curb wall has reduced, the packing space between grid has just increased, thereby further promotes the film filling capacity between grid, the load effect of appearance while avoiding adopting existing method to carry out thin film deposition.
Accompanying drawing explanation
Fig. 1 is for forming grid and grid curb wall substrate cross-section structural representation afterwards
Fig. 2 is for increasing lateral wall width substrate cross-section structural representation afterwards
Fig. 3 is the cross section structure schematic diagram after deposit film on the substrate in Fig. 2
Fig. 4 is the schematic flow sheet of removing method of the load effect producing for deposited film of a preferred embodiment of the present invention
The corresponding cross section structure schematic diagram of each step of the removing method of the load effect producing for deposited film that Fig. 5-11 are above-mentioned preferred embodiment of the present invention
Embodiment
For making content of the present invention more clear understandable, below in conjunction with Figure of description, content of the present invention is described further.Certainly the present invention is not limited to this specific embodiment, and the known general replacement of those skilled in the art is also encompassed in protection scope of the present invention.
Below with reference to specific embodiments and the drawings 4-11, to of the present invention, after reducing short-channel effect, in film deposition process, occur that the removing method of load effect is described in further detail.Wherein, Fig. 4 is the schematic flow sheet of removing method of the load effect producing for deposited film of a preferred embodiment of the present invention, the corresponding cross section structure schematic diagram of each step of the removing method of the load effect producing for deposited film that Fig. 5-11 are above-mentioned preferred embodiment of the present invention.
Refer to Fig. 4, the present embodiment after reducing short-channel effect, in film deposition process, there is the removing method of load effect, specifically comprise the following steps:
Step S01: refer to Fig. 5, form grid 102 and grid curb wall 103 in Semiconductor substrate 101;
Here, can adopt existing common process to form grid 102 and grid curb wall 103, can also but be not limited to comprise that the techniques such as formation of silicide form Semiconductor substrate 101 of the present invention.
In the present embodiment, Semiconductor substrate 101 can be, but not limited to as silicon substrate, and the surface of Semiconductor substrate 101 has layer oxide film, and its composition can be the silica material of thermal oxidation generation, grid 102 and grid curb wall 103 are positioned on the surface of this oxide-film, and the present invention repeats no more this.The material of grid curb wall 103 can be silicon nitride, silica etc., preferably, in the present embodiment, adopts silicon nitride as the material of grid curb wall 103.
Step S02: refer to Fig. 6, increase the width of grid curb wall 103, and Semiconductor substrate 101 is carried out to source-drain area Implantation;
Here, increase grid curb wall 103 width, thereby form grid curb wall 103 ", the method that increases grid curb wall 103 width can adopt existing technique to complete, and the present invention is no longer described in detail this; As everyone knows, after grid curb wall 103 width increase, carry out the Implantation of source-drain area, can increase the distance of Implantation region and raceway groove, thereby reduce short-channel effect, this is that those skilled in the art can know, and the present invention repeats no more this.
Step S03: refer to Fig. 7, cover one deck anti-reflecting layer 104 in Semiconductor substrate 101;
Concrete, can adopt Mechanical Method in Semiconductor substrate 101, to apply one deck anti-reflecting layer 104, preferably, anti-reflecting layer 104 can be bottom anti-reflection layer, such as being organic antireflection layer, this is due in follow-up technique, on anti-reflecting layer, apply photoresist and carry out photoetching process, bottom anti-reflection layer can effectively reduce the reflection of photoresist bottom to light in photoresist exposure process, improves exposure quality.Here; anti-reflecting layer 104 wraps grid 102 and grid curb wall 103 "; not only can protect grid 102 and side wall 103 " top is not subject to etching injury in follow-up attenuate etching process; can also guarantee the smooth of Semiconductor substrate 101 surfaces, improve the precision of follow-up photoetching and etching technics.Preferably, in the present embodiment, in coating procedure, guarantee that the top of covered anti-reflecting layer 104 is tending towards smooth.
Step S04: refer to Fig. 8, at anti-reflecting layer 104 surface-coated photoresists 105, adopt photoetching process, patterning photoresist 105 forms grid curb wall 103 in photoresist 105 " want the pattern of weakened region;
Here, can require to select suitable reticle according to actual process, photoresist 105 is exposed, in photoresist 105, form the pattern after exposure, in reticle, the size of critical size can increase as far as possible, thereby makes the width of the photoresist 105 after photoetching larger, is enough to shelter from side wall 103 " top; make like this anti-reflecting layer 104 after follow-up patterning can shelter from side wall 103 " top area, make it can not be subject to the damage of follow-up reduction process.
Step S05: refer to Fig. 9, the photoresist 105 of patterning of take is masterplate, adopts dry etch process, and patterning anti-reflecting layer 104 forms grid curb wall 103 in anti-reflecting layer 104 " want the pattern of weakened region;
Here, can be, but not limited to using plasma dry etch process, the photoresist 105 of above-mentioned patterning of take is mask, etching anti-reflecting layer 104, thereby expose grid curb wall 103 " region of wanting attenuate.Certainly, the concrete width of the anti-reflecting layer 104 after patterning can require to set according to actual process, such as, the anti-reflecting layer after patterning also can cover grid side wall 103 " part at top, as the width between the dotted line a on the grid both sides on the left side in Fig. 7 and a '; Also grid curb wall top all can be covered, as the dotted line b on the grid both sides on the right and the width between b ' in Fig. 7; Also can be by grid curb wall 103 " return to and increase the width of the grid curb wall 103 before width etc.In the present embodiment, adopt grid curb wall 103 " width return to grid curb wall 103 width as covering grid curb wall 103 " anti-reflecting layer 104 width after the patterning at top.
It should be noted that, in the present invention, for the technological parameter adopting in etching process, can require to set according to actual process.Preferably, in the present embodiment, the pressure adopting is 5-10mTorr, and the upper electrode power adopting is 300-500 watt, and the reaction time is 10-80 second, and the bottom electrode voltage matching therewith can be, but not limited to as 100V.In etching process, can adopt HBr and O
2mist as etching gas, HBr and O
2flow proportional be 1:1 to 15:2, preferably ratio is 4:1.In the present embodiment, the flow of HBr is 10-30sccm, O
2flow be 4-10sccm.
Step S06: refer to Figure 10, the anti-reflecting layer 104 of patterning of take is mask, through dry etch process, attenuate grid curb wall 103 ";
Concrete, in this step in the present embodiment, said dry etch process can be, but not limited to as adopting existing SPT technique to carry out grid curb wall 103 " attenuate, thereby obtain the grid curb wall 103 ' of attenuate.Because those of ordinary skill in the art can know the specific embodiment that existing grid curb wall reduction process is SPT technique, the present invention repeats no more this.As previously mentioned, just because of there being anti-reflective film to cover grid 102 and grid curb wall 103 " top, etching gas can not touch grid 102 and grid curb wall 103 " top, thereby avoided grid curb wall 103 " top is subject to etching injury.Meanwhile, due to grid curb wall 103 " top is protected, and can not consider grid curb wall 103 " impact at top, freely control the etching process of side wall horizontal direction, promoted grid curb wall 103 " the effect of attenuate.
It should be noted that, in the present invention, for the technological parameter adopting in etching process, can require to set according to actual process.In the present embodiment, the pressure adopting is 20-40mTorr, and the upper electrode power adopting is 500-800 watt, and the reaction time is 10-40 second, and the bottom electrode voltage adopting is 0.In etching process, the etching gas adopting can be gas for fluorine, and in the present embodiment, the fluorine of employing is that gas is CH
2f
2and CHF
3mist.CH
2f
2with CHF
3flow proportional be 1:1 to 4:1, preferred proportion is 2:1.In the present embodiment, CH
2f
2flow be 60-120sccm, CHF
3flow be 30-60sccm.
In the present embodiment, at grid curb wall described in attenuate 103 " afterwards, also comprise: using plasma dry etch process is removed remaining photoresist 105 and/or anti-reflecting layer 104.This is to require differently due to actual process, at the grid curb wall 103 ' that forms attenuate afterwards, may have the residual of photoresist 105 and anti-reflecting layer 104, or only have the residual of anti-reflecting layer 104, therefore, need to be removed, to guarantee the quality of subsequent thin film depositing operation.The reacting gas adopting can be, but not limited to as pure O
2or SO
2deng, in the present embodiment, adopt pure O
2as reacting gas, but this is not used in and limits the scope of the invention.It should be noted that, the concrete technology parameter of removing the dry etch process process of photoresist 105 and/or anti-reflecting layer 104 can require to set according to actual process, in the present embodiment, preferably, the reaction pressure adopting is 5-15mTorr, and upper electrode power is 500-1500 watt, and bottom electrode voltage is zero, gas flow is 150-250sccm, and the reaction time is 40-80 second.Certainly, the method for removal can also be wet etching, and the concrete technology condition that wet etching adopts can require to set according to actual process, and this is not restricted in the present invention.
Step S07: refer to Figure 11, deposit film 106 in Semiconductor substrate 101.
Concrete, at the grid curb wall 103 ' that forms attenuate afterwards, carry out SMT or SAB processing procedure, deposit film 106 in SMT or SAB processing procedure, as shown in Figure 11, the thickness at film 106 tops is approximate identical with the thickness of film 106 bottoms, has eliminated dexterously the existing load effect occurring in film deposition process after reducing short-channel effect.
In sum, the removing method that occurs load effect after reducing short-channel effect in thin film deposition processes of the present invention, first adopts the width method that increases grid curb wall to carry out Implantation, reduces short-channel effect; Then, reduce the width of grid curb wall, then carry out thin film deposition processes.Reduce the method for grid curb wall width: utilize anti-reflecting layer to protect grid and gate electrode side coping, and utilize the anti-reflecting layer of patterning to define the width that grid curb wall will reduce, then adopt dry etch process etching attenuate grid curb wall.Clearly, because the width of grid curb wall has reduced, the packing space between grid has just increased, thereby further promotes the film filling capacity between grid, the load effect of appearance while avoiding adopting existing method to carry out thin film deposition.
Although the present invention discloses as above with preferred embodiment; right described embodiment only gives an example for convenience of explanation; not in order to limit the present invention; those skilled in the art can do some changes and retouching without departing from the spirit and scope of the present invention, and the protection range that the present invention advocates should be as the criterion with described in claims.
Claims (12)
1. at a removing method that reduces the film generation load effect depositing after short-channel effect, it is characterized in that, comprise the following steps:
Step S01: form grid and grid curb wall in Semiconductor substrate;
Step S02: increase the width of described grid curb wall, and described Semiconductor substrate is carried out to source-drain area Implantation;
Step S03: cover one deck anti-reflecting layer in described Semiconductor substrate;
Step S04: at described anti-reflecting layer surface-coated photoresist, adopt photoetching process, photoresist described in patterning forms the pattern that described grid curb wall is wanted weakened region in described photoresist;
Step S05: the described photoresist of patterning of take is masterplate, adopts dry etch process, and anti-reflecting layer described in patterning forms the pattern that described grid curb wall is wanted weakened region in described anti-reflecting layer;
Step S06: the described anti-reflecting layer of patterning of take is mask, through dry etch process, grid curb wall described in attenuate;
Step S07: deposit film in described Semiconductor substrate.
2. method according to claim 1, is characterized in that, in described step S04, after grid curb wall described in attenuate, using plasma dry etch process is removed remaining described photoresist and/or described anti-reflecting layer.
3. method according to claim 2, is characterized in that, utilizes pure O in described plasma dry etch process
2or SO
2as reacting gas.
4. method according to claim 2, is characterized in that, the reaction pressure that described plasma dry etch process adopts is 5-15mTorr, upper electrode power is 500-1500 watt, bottom electrode voltage is zero, and gas flow is 150-250sccm, and the reaction time is 40-80 second.
5. method according to claim 1, is characterized in that, in described step S05, adopts HBr and O
2mist as reacting gas.
6. method according to claim 5, is characterized in that, in described step S05, and described HBr and described O
2flow proportional be 1:1 to 15:2.
7. method according to claim 1, is characterized in that, in described step S05, the reaction pressure adopting is 5-10mTorr, and the upper electrode power adopting is 300-500 watt, and the reaction time is 10-80 second.
8. method according to claim 1, is characterized in that, in described step S06, adopting fluorine is grid curb wall described in gas etching.
9. method according to claim 8, is characterized in that, in described step S06, described fluorine is that gas is CH
2f
2and CHF
3mist.
10. method according to claim 9, is characterized in that, in described step S06, and described CH
2f
2with described CHF
3flow proportional be 1:1 to 4:1.
11. grid curb wall reduction process according to claim 1, is characterized in that, in described step S06, the reaction pressure adopting is 20-40mTorr, the upper electrode power adopting is 500-800 watt, and the bottom electrode voltage adopting is 0, and the reaction time is 10-40 second.
12. methods according to claim 1, is characterized in that, in described step S07, described film is to form in stress memory technique or silicide block area processing procedure.
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| CN112908859A (en) * | 2021-03-24 | 2021-06-04 | 上海华虹宏力半导体制造有限公司 | Method for manufacturing flash memory |
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| US20030100173A1 (en) * | 2001-11-28 | 2003-05-29 | Mitsubishi Denki Kabushiki Kaisha | Method of manufacturing semiconductor device |
| JP2005101588A (en) * | 2003-09-05 | 2005-04-14 | Toshiba Corp | Field effect transistor and its manufacturing method |
| CN101073143A (en) * | 2004-12-03 | 2007-11-14 | 先进微装置公司 | Method for forming a semiconductor arragement with gate sidewall spacers of specific dimensions |
| US20090218636A1 (en) * | 2008-02-29 | 2009-09-03 | Chartered Semiconductor Manufacturing Ltd. | Integrated circuit system for suppressing short channel effects |
| CN101989576A (en) * | 2009-08-07 | 2011-03-23 | 中芯国际集成电路制造(上海)有限公司 | Manufacture method of semiconductor device |
| CN102194678A (en) * | 2010-03-11 | 2011-09-21 | 中芯国际集成电路制造(上海)有限公司 | Method for etching grid |
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| CN112908859A (en) * | 2021-03-24 | 2021-06-04 | 上海华虹宏力半导体制造有限公司 | Method for manufacturing flash memory |
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