CN104035749A - Method for accelerating chip pipelining processing - Google Patents

Abstract

The invention discloses a method for accelerating chip pipelining processing. After an instruction is transmitted from an IF stage through a renaming mechanism, the instruction enters a renaming module, a register is renamed, an instruction after renaming is conducted enters a transmitting stage, a corresponding operand or the Tag of the operand is taken out from the register, the WAW and WAR data collision problem is solved, the method is applied to the pipelining chip design, and the chip pipelining processing efficiency is greatly improved.

Description

A kind of method of accelerating chip pipeline processes

Technical field

The present invention relates to chip design field, relate in particular to a kind of method of accelerating chip pipeline processes.

Background technology

Dependence between instruction is to hinder instruction scheduling to play a role, and then affects the major obstacle of instruction level parallelism.Instruction scheduling is a very important stage of modern optimization compiler back-end, and it is can be in a fundamental block (basic block, BB) or cross over fundamental block rearrangement instructions, makes the instruction time in calling program critical path short as far as possible.Effectively instruction scheduling can utilize processor resource fully, improves instruction-level parallelism (ILP).Dependence between instruction is to hinder the major obstacle that instruction scheduling plays a role.Dependence between instruction can be divided into 3 classes: data dependence, name rely on and control and rely on.Data dependence claims again stream to rely on, and instruction j data dependence, in instruction i, refers to the result that j has directly or indirectly quoted instruction i definition.Known this is that read-after-write (RAW) relies on.Name relies on to refer between 2 instructions has used identical register or main memory unit, is same name, but data do not flow between 2 instructions along this name, and name relies on and is divided into two kinds: antidependence and output rely on.Instruction j antidependence is to say that j has defined a name in instruction i, and i has quoted this name, and writeafterread (WAR) relies on.It is to say that the two has defined same name that instruction i and instruction j output rely on, and write after write (WAW) relies on.Control to rely on the relation having disclosed between a general instruction and branch instruction, whether whether branch instruction controls metastasis occurs has affected this general instruction and has been performed.

Summary of the invention

The object of the invention is to for the deficiencies in the prior art, a kind of method of accelerating chip pipeline processes is provided.

The object of the invention is to be achieved through the following technical solutions, a kind of method of accelerating chip pipeline processes, comprises the following steps:

(1) during from the instruction fetch of IF level, first Tag label corresponding to source operand register returned to instruction in corresponding from Map Table FIFO (queue), check the item entry in the Map Table FIFO that destination operand register Tag label is corresponding, the label in this is pressed into PTRQ queue;

From Free List fifo queue, extrude a label and cover the item entry in above-mentioned Map Table FIFO;

Register name in the Map Table FIFO middle term entry being replaced is returned to instruction;

(2) instruction executes rear renewal register, and rename module obtains writing back in level after the set of correlating markings position, and label extrudes from PTRQ FIFO, enters Freelist FIFO, again participates in rename and recycles.

Beneficial effect of the present invention: the present invention is by rename mechanism, instruction is after the transmitting of IF level, enter rename module, register is carried out to rename, instruction after rename enters emitting stage, takes out corresponding operand or the Tag of operand from register, has solved the data collision problem of WAW and WAR, be applied to, in pipeline chip design, greatly improve chip stream waterline treatment effeciency.

Accompanying drawing explanation

Fig. 1 is register renaming modular structure figure;

Embodiment

Below in conjunction with accompanying drawing, the present invention is described in further detail.

As shown in Figure 1, whole single-threaded rename module (Rename) is comprised of map table FIFO He Liangge round-robin queue, and Liang Ge round-robin queue is Free list FIFO and Pending target return queue FIFO (PTRQ queue).

A kind of method of accelerating chip pipeline processes of the present invention, comprises the following steps:

(1) during from the instruction fetch of IF level, first Tag label corresponding to source operand register returned to instruction in corresponding from Map Table FIFO, check the item entry in the Map Table FIFO that destination operand register Tag label is corresponding, the label in this is pressed into PTRQ queue;

From Free List fifo queue, extrude a label and cover the item entry in above-mentioned Map Table FIFO;

Register name in the Map Table FIFO middle term entry being replaced is returned to instruction;

Among this process, note the control of Free List FIFO and PTRQ FIFO pointer.Because rename is in order to eliminate WAW, the conflict of WAR, what the write operation that this necessary guarantee of making use of momentum is adjacent was used is not same register, the operation of write-after-read, with neither same register, this just need to read not change the label of register, writes the label that can change register.But true data is relevant, should retain, as RAW conflict, that this that register that just requires read-after-write is write before should being.So, only have the label in the Map Table FIFO item that the destination register label of instruction is corresponding to change at every turn, and be to be first pressed into new label, and then new label is returned to instruction.

(2) instruction executes rear renewal register, and rename module (Rename) obtains writing back after the middle set of correlating markings position of level (WB), and label extrudes from PTRQ FIFO, enters Freelist FIFO, again participates in rename and recycles.

Map table FIFO has 16 items, represent respectively 16 structure register ARF (Architectural Register File), 5bit data of each correspondence, 5bit data are used for representing 24 registers (comprising 16 structure register+8 rename register).

Free list FIFO comprises idle register label, and the indicated register of these labels can carry out rename; When program is initial, due to rename occurring, the 0-15 register in respectively corresponding 24 registers of 16 items in map table FIFO, and corresponding 16-23 register in Free list FIFO.

Pending target return queue FIFO comprises be as rename but need again again by the register of rename, such as:

R1←R2+R3

R1←R4+R5

In this program segment, 1 instruction distributes after R1 when entering rename module, use another rename register R16, when entering rename module, 2 instructions again distribute R17 as rename register, that in the middle of pending target return queue queue, preserve is exactly R16, and that in map table FIFO corresponding to R1, preserve is R17, solved the data collision problem of WAW, the data collision of WAR also can solve with the present invention's invention, the present invention is applied to, in pipeline chip design, can improve chip stream waterline treatment effeciency.

Claims (1)

1. a method of accelerating chip pipeline processes, is characterized in that, comprises the following steps:

(1) during from the instruction fetch of IF level, first Tag label corresponding to source operand register returned to instruction in corresponding from Map Table FIFO, check the item entry in the Map Table FIFO that destination operand register Tag label is corresponding, the label in this is pressed into PTRQ queue;

From Free List fifo queue, extrude a label and cover the item entry in above-mentioned Map Table FIFO;

Register name in the Map Table FIFO middle term entry being replaced is returned to instruction;

(2) instruction executes rear renewal register, and rename module obtains writing back in level after the set of correlating markings position, and label extrudes from PTRQ FIFO, enters Free list FIFO, again participates in rename and recycles.