CN104103317A - Nonvolatile memory and operating method thereof - Google Patents
Nonvolatile memory and operating method thereof Download PDFInfo
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- CN104103317A CN104103317A CN201310126077.9A CN201310126077A CN104103317A CN 104103317 A CN104103317 A CN 104103317A CN 201310126077 A CN201310126077 A CN 201310126077A CN 104103317 A CN104103317 A CN 104103317A
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Abstract
The invention discloses a method for transforming the distribution of a threshold voltage by a nonvolatile memory of a multilayer store unit (MLC) according to a preset coding table before programming. The method comprises the following steps: grouping a plurality of store units, wherein the store units have a same first voltage in advance and are in a same major state; groping the store units in a preselected major state as a same next state when the store units in the preselected major state have a same preset second potential; and improving the first potential of the store units to a voltage, wherein the improved store units have a highest preset second voltage, and the voltage is higher than a preset highest major state voltage.
Description
Technical field
The present invention is about a kind of method of operating nonvolatile memory device; Particularly, be the nonvolatile memory that is applied to Multi-layer Store unit (MLC).
Background technology
The storage capacity of nonvolatile memory has been promoted to and has exceeded per second hundred accesses, thereby causes process progress fast and the technology of development Multi-layer Store unit (MLC).The basic methods of application Multi-layer Store monotechnics is similar to the technology of double-deck storage element (BLC), except Multi-layer Store monotechnics can be by charging to different voltage levels, makes single the multiple position of storage unit stores but not two kinds of positions.Generally speaking, MLC technology can be by utilizing 2
n-1 threshold voltage (Vt) distinguishes 2
nthe state of kind, for storing 2
nthe voltage level of (n > 1).Fig. 1 is presented at a desirable threshold voltage (Vt) of two positions in MLC storage element and distributes.The place value of a storage element is to determine via voltage window, and the threshold voltage of described storage element is positioned at described voltage window place place.
But, in fact, dwindle and when each storage element can store more multidigit along with the size of storage element, be applied to the threshold voltage window of distinguishing each place value and become the threshold voltage window that is less than BLC technology.Because the device of application BLC and MLC can use the voltage window of formed objects, therefore in MLC, the distance between contiguous voltage level is significantly less than the distance in MLC.In addition, other factors, for example fabrication error, program disturb or second disturbing effect all may be offset or interference threshold voltage, and then make the distance of distinguishing different conditions become less.
Fig. 2 shows that the threshold voltage of two known MLC nonvolatile memorys distributes, and wherein the storage element after programming can be divided into four major states 1,2,3 and major state 4 according to primary threshold voltage.Each major state can be by four kinds of different next state n1, n2, and n3 and n4 form, and described next state is to divide into groups according to second threshold voltage.Generally speaking, the first major state 1 has minimum threshold voltage, and is easy to most be interfered and is not easy to restrain its distribution.Therefore a part for the first major state 1 may be overlapped in the second major state 2.Clearly, in MLC storage element, detecting voltage level, follows and in BLC storage element, detects voltage level and compare more complicated.Therefore,, for the detecting of magnitude of voltage that determines storage element, the error that how to reduce detecting becomes more and more important.
Summary of the invention
The nonvolatile memory that the invention provides a kind of Multi-layer Store unit (MLC) before programming according to the method for the conversion threshold voltage distribution of predefined coding schedule (coding table), described method comprises the multiple storage elements of grouping, and be set in advance under identical major state, described storage element has first identical voltage.In addition,, if described method separately comprises described storage element under a preliminary election major state while having identical predefined second voltage, the described storage element dividing into groups under described preliminary election major state is identical next state.Then, described method comprises and improves described first voltage to one voltage of described storage element with the highest predefined second voltage, and described voltage is higher than the described voltage of high major state that presets.
The present invention is open a kind of nonvolatile memory for Multi-layer Store unit (MLC) separately, promotes the method for threshold voltage window.The method comprises and presets coding schedule according to one, obtains the voltage after a programming of each storage element; Then, screen multiple storage elements, wherein said storage element has first identical voltage.The method separately comprises the second voltage according to each storage element, distinguishes the storage element after described screening.In addition, the method comprises described first voltage to one high voltage that promotes the described storage element with the highest second voltage again.Just because of this, described in there is the threshold voltage of the storage element of different first voltage, promote can't be overlapped after first voltage.
Brief description of the drawings
Fig. 1 discloses the schematic diagram of the distribution of threshold voltage (Vt) level of two MLC storage elements in a kind of ideal;
Fig. 2 shows the schematic diagram that the threshold voltage of known two MLC nonvolatile memorys distributes;
Fig. 3 shows the schematic diagram of two non-volatile memory array;
Fig. 4 shows the schematic diagram of the threshold voltage distribution in MLC nonvolatile memory with n kind major state;
Fig. 5 shows the schematic diagram distributing according to the threshold voltage of one embodiment of the invention;
Fig. 6 shows the schematic diagram that threshold voltage according to another embodiment of the present invention distributes;
Fig. 7 shows according to the process flow diagram of one embodiment of the invention;
Fig. 8 shows process flow diagram according to another embodiment of the present invention; And
Fig. 9 A-9C shows the schematic diagram distributing according to the threshold voltage of one embodiment of the invention.
Main element symbol description
1 major state
2 major states
3 major states
4 major states
305 storage elements
Storage area, 305-1 left side
Storage area, 305-2 right side
1i next state
V11_L lower boundary voltage
V1_L lower boundary voltage
The high boundary voltage of V1i_U
The high boundary voltage of V1_U
The high boundary voltage of Vn_U
Δ V2-1 window
H major state
C distributes
C ' distribution
C " distributes
Embodiment
The present invention will be described with reference to the accompanying drawings.
Below describe more comprehensively embodiments of the invention referring to accompanying drawing, the described accompanying drawing that waits forms a part of the present invention, and can put into practice concrete example expressivity embodiment of the present invention with show by way of illustration.But the present invention can be according to many multi-form embodiments, and should not be construed as and be limited to the embodiment that set forth herein; In fact, these embodiment will be comprehensive and complete through providing to make the present invention, and will pass on category of the present invention to those who familiarize themselves with the technology comprehensively.As used herein, term "or" is comprising property inclusive-OR operation, and be equivalent to term " and/or ", unless context separately has clear description.In addition,, in whole instructions, the implication of " " and " described " comprises multiple quoting.
The explanation of embodiments of the invention and method can be with reference to figure 3 to 9.It should be noted that the present invention is not intended to limit the present invention in the embodiment of exposure out of the ordinary, and the present invention also can utilize further feature, element, method and embodiment to implement the present invention.
Fig. 3 shows one or two non-volatile memory array, and it contains multiple storage elements 305.Each storage element 305 comprises storage area, a left side 305-1 and storage area, a right side 305-2, the also accommodating electric charge (trapped charges) of catching in it.Left side storage area 305-1 is considered as first, and storage area, right side 305-2 is considered as second.According to the present invention, the storage element of a unit comprises at least two, but the present invention describes as example using two storage elements, but is not limited to the storage element of two.Each storage element 305 is after programming, because the quantity at storage area IT electric charge is by the different threshold voltages of shining.Generally speaking the storage element system that, has identical first threshold voltage divides into groups in identical major state.Furthermore, the storage element that is positioned at identical major state is to divide into different next states according to second threshold voltage.
Fig. 4 shows that the threshold voltage of a MLC nonvolatile memory distributes, and it has n kind major state according to a predefined coding schedule.The distribution of the first major state 1 comprises a high boundary voltage V
1_Uan and lower boundary voltage V
1_L.Described major state 1 comprises i kind next state, and state represents with code name 1i in the present invention each time.Next state is according to the high boundary voltage of state each time from low to high, and the order with 1 to i is arranged.State (11 or 1[1]) contains minimum lower boundary voltage V for the first time
11_L, this lower boundary voltage V
11_Lalso be the lower boundary voltage V in the first major state
1_L, therefore V
11_L=V
1_L.I next state (for example 1i) has the highest high boundary voltage V in all next states in major state 1
1i_U.The high boundary voltage V of the first major state
1_Ualso be the high boundary voltage V of next state 1i
1i_U.The highest major state n contains a high boundary voltage V
n_U, it is the ceiling voltage state of whole storage elements in original state, original state refers to before programming for the first time.Voltage window is defined as the distance between the lower boundary voltage of the high boundary voltage of each major state and the major state on its right side.For example, Δ V
2-1represent the window between the first major state and the second major state.
Before programming, first screen memory storage unit predetermined for example, by the higher next state being charged under a default major state, next state 1i.At the voltage of the next state 1i of major state 1 via its first voltage of charging to promoting compared with high voltage level, therefore its lower boundary voltage V after promoting
1i_Lhigher than the highest boundary voltage V of high major state
n_U.Fig. 5 is presented at the highest next state 1i that promotes the first major state 1 and distributes to the threshold voltage after higher voltage level.Now, the high boundary voltage V of the first major state 1
1_Uit is the high boundary voltage (signable for 1[i-1]) of i-1 next state.Distance, delta V between the first major state 1 and the second major state 2
2-1(it is V obviously to increase Δ V
1i_Udeduct V
1[i-1] _ U), therefore the distance between the first major state 1 and the second major state 2 is by Δ V
2-1be increased to Δ V+ Δ V
2-1.
For further increasing the distance between the first major state 1 and the second major state 2, except promoting the voltage level of i next state, in major state 1, the storage element of i-1 next state also can be promoted to high voltage by each other first voltage to high-voltage level in charging storage element, and the lower boundary voltage that makes i-1 next state is higher than the highest boundary voltage V of high major state
n_U,, for example V
1[i-1] _ L> V
n_U.Next state after lifting can be divided into groups in forming another major state (being called H major state).I next state and i-1 next state that Fig. 6 is presented at the first major state 1 are moved to the threshold voltage distribution after higher voltage level, to form H major state.The high boundary voltage of the first major state 1 can be determined by the high boundary voltage of i-2 next state, and therefore near distance one step between the first major state 1 and the second major state 2 is increased to Δ V+ Δ V
2-1, wherein Δ V=V
1i_U-V
1[i-2] _ U, and the first major state 1 and the second major state 2 are more easily made a distinction.
According to the present invention, a kind of next state in the first major state can be promoted to one higher than V
n_Uvoltage, wherein 1≤i, based on window can for distinguish its major state adjacent thereto.
Can be adjusted to the major state that is suitable for any x, wherein 1≤x≤n-1 for the method that promotes next state voltage.
Fig. 7 shows process flow diagram according to an embodiment of the invention.In step 200, first obtain the distribution of the threshold voltage by coding of the nonvolatile memory of Multi-layer Store unit (MLC).This distribution can be divided into multiple major states.The different storage elements with identical first voltage are divided into one group.Each major state comprises multiple next state, and the different storage elements with identical first voltage and identical second voltage are divided into same group.In step 300, a major state is screened.In step 400, in the major state of screening, the highest next state is promoted to a higher voltage level, and its voltage level is higher than the highest major state, and forms a H major state.One selects step 500 can be contained in the method for the second the highest next state promoting in described screening major state, and is grouped in major state H.
Fig. 8 shows another embodiment of the present invention.Step 100 can add the method with before programming, removes the electric charge of storage element in non-volatile memory array, and in the each step continuing as shown in Figure 7.
Fig. 9 A shows a major state distribution C, the distribution of its MLC nonvolatile memory before programming.It has n kind major state, comprises i kind next state in major state.Some high level next states, for example 1i, 1[i-1] and 1[i-2] be overlapping with the second major state.One removes the removable any electric charge of catching of being detained in local trapping layer of step, described local trapping layer can be mononitride layer or an ONO (oxide-nitride-oxide) layer, therefore the C that distributes can mould (reshaped) again and become different distribution C ' as shown in Figure 9 B, and wherein the first major state has one compared with long streaking compared to distribution C.Lower boundary voltage V
1_Lbe offset left and have that state (being 1i at this embodiment) and the second major state 2 are overlapping at least one times.Fig. 9 C demonstration, after applying as the step of Fig. 7, the distribution C of the first major state 1 ".Wherein multiple high next states are promoted to one higher than the high voltage of the highest major state n.Near distance one step between the first major state 1 and the second major state 2 is passed through, in promoting next state 1i and 1[i-1] front removal step is increased, and the ability of therefore distinguishing the first major state and the second major state has been raised.
Method of the present invention and feature have fully been described at above-mentioned example and in describing.Should be understood that any amendment or the change that do not depart from spirit of the present invention are intended to be encompassed in protection category of the present invention.
Claims (14)
1. the method that the nonvolatile memory of Multi-layer Store unit (MLC) distributes according to the conversion threshold voltage of predefined coding schedule (coding table) before programming, comprises:
Multiple storage elements that divide into groups, are set in advance under identical major state, and described storage element has first identical voltage;
If when the described storage element under a preliminary election major state has identical predefined second voltage, the described storage element dividing into groups under described preliminary election major state is identical next state; And
Described first voltage to one voltage that improves described storage element, wherein said storage element has the highest predefined second voltage, and described voltage is higher than the described voltage of high major state that presets.
2. method according to claim 1, wherein said major state is one first major state, described the first major state has lowest voltage level between other major state.
3. method according to claim 1, wherein comprises i kind next state in described preliminary election major state, and described i kind next state is, according to the high boundary voltage of state each time, the order with 1 to i is arranged, and wherein said i next state has the highest boundary voltage.
4. method according to claim 3, further comprises a step, and described step promotes a voltage of i-1 next state, described voltage higher than have ceiling voltage described in preset the voltage of major state.
5. method according to claim 4, further comprises a step, and described step forms one second major state, and described the second major state has a lower boundary voltage, and described lower boundary voltage is higher than the described the highest boundary voltage of high major state that presets.
6. method according to claim 5, further comprises a step, described step in described major state, divide into groups i and i-1 next state after described lifting.
7. method according to claim 1, further comprises a step, and described step promotes at least two kinds of next state to voltages, and described voltage is higher than the described the highest boundary voltage of high major state that presets.
8. method according to claim 1, further comprises a step, and described step is in promoting before described first voltage, removes to catch electric charge (trapped charges) in described nonvolatile memory.
9. for the nonvolatile memory of Multi-layer Store unit (MLC), promote the method for threshold voltage window, comprise:
Preset coding schedule according to one, obtain the voltage after a programming of each storage element;
Screen multiple storage elements, wherein said storage element has first identical voltage;
According to the second voltage of each storage element, distinguish the storage element after described screening; And
Lifting has described first voltage to one high voltage of the described storage element of the highest second voltage.
10. method according to claim 9, further comprises a step, and described step promotes described first voltage to one high voltage of the described storage element with the second the highest second voltage.
11. methods according to claim 9, the threshold voltage of a part for the storage element after wherein said screening is overlapped in the voltage without the storage element of screening before lifting step.
12. methods according to claim 9, first voltage of wherein said lifting is higher than the described mxm. that presets described first voltage that coding schedule sets.
13. methods according to claim 9, further comprise a step, and described step is in promoting before described first voltage, remove to catch electric charge (trapped charges) in described nonvolatile memory.
14. methods according to claim 9, the described threshold voltage with different first voltage of wherein said storage element, after promoting described first voltage, does not overlap each other.
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| CN104103317B CN104103317B (en) | 2017-05-03 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107436847A (en) * | 2016-03-25 | 2017-12-05 | 阿里巴巴集团控股有限公司 | Extend system, method and the computer program product of the service life of nonvolatile memory |
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| CN101095197A (en) * | 2004-12-23 | 2007-12-26 | 桑迪士克股份有限公司 | Nand-eeprom with reduction of floating gate to floating gate coupling effect |
| CN101656107A (en) * | 2008-08-21 | 2010-02-24 | 旺宏电子股份有限公司 | Method for reading and programming a memory |
| US20110122690A1 (en) * | 2009-11-20 | 2011-05-26 | Macronix International Co., Ltd. | Method for programming multi-level cell and memory apparatus |
| US20120163085A1 (en) * | 2010-12-23 | 2012-06-28 | Idan Alrod | Non-Volatile Memory And Methods With Soft-Bit Reads While Reading Hard Bits With Compensation For Coupling |
-
2013
- 2013-04-12 CN CN201310126077.9A patent/CN104103317B/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101095197A (en) * | 2004-12-23 | 2007-12-26 | 桑迪士克股份有限公司 | Nand-eeprom with reduction of floating gate to floating gate coupling effect |
| CN101656107A (en) * | 2008-08-21 | 2010-02-24 | 旺宏电子股份有限公司 | Method for reading and programming a memory |
| US20110122690A1 (en) * | 2009-11-20 | 2011-05-26 | Macronix International Co., Ltd. | Method for programming multi-level cell and memory apparatus |
| US20120163085A1 (en) * | 2010-12-23 | 2012-06-28 | Idan Alrod | Non-Volatile Memory And Methods With Soft-Bit Reads While Reading Hard Bits With Compensation For Coupling |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107436847A (en) * | 2016-03-25 | 2017-12-05 | 阿里巴巴集团控股有限公司 | Extend system, method and the computer program product of the service life of nonvolatile memory |
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Granted publication date: 20170503 Termination date: 20190412 |