CN104124180B - Manufacturing method of chip packaging structure - Google Patents

Manufacturing method of chip packaging structure Download PDF

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Publication number
CN104124180B
CN104124180B CN201310487536.6A CN201310487536A CN104124180B CN 104124180 B CN104124180 B CN 104124180B CN 201310487536 A CN201310487536 A CN 201310487536A CN 104124180 B CN104124180 B CN 104124180B
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chip
connection
layer
conductor
preparation
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CN104124180A (en
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王建皓
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Chipmos Technologies Inc
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Chipmos Technologies Inc
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
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    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
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Abstract

The invention provides a manufacturing method of a chip packaging structure, which comprises the following steps. First, a carrier is provided. The carrier has a metal layer. Then, a patterned photoresist layer is formed on the metal layer. The patterned photoresist layer has a plurality of first openings to expose a portion of the metal layer. Then, a plurality of connection terminals are respectively formed in the first openings, and the connection terminals are connected with the metal layer. Then, the chip is disposed on the carrier, and the connection terminals and the first pads of the chip are respectively connected by a plurality of connection conductors. Then, after the chip is arranged on the loader, the patterned photoresistance layer is removed. And finally, forming packaging materials on the carrier. The packaging material wraps the chip, the connecting conductor and the metal layer. Then, the carrier and the metal layer are removed to expose the connection terminal.

Description

The preparation method of chip-packaging structure
Technical field
The invention relates to a kind of preparation method of encapsulating structure, and in particular to a kind of chip-packaging structure Preparation method.
Background technology
In recent years, making rapid progress with electronic technology, and high-tech electronic industry is come out one after another so that more human nature Change, electronic product with better function is constantly weeded out the old and bring forth the new, and strided forward towards light, thin, short, small trend.Under this trend, Because circuit board has the advantages that wiring is fine and closely woven, it is compact and functional to assemble, therefore circuit board is become to carry multiple electronics Element（For example：Chip）And make one of main media that these electronic components are electrically connected to each other.
Flip-over type（flip chip）Encapsulation is a kind of mode of chip and circuit board package.Connect with multiple on circuit board Pad, and circuit board can be electrically connected with the way of reflow by the solder being configured on connection pad with chip.In recent years, due to electricity Subcomponent（Such as chip）Between the signal of required transmission increasingly increase, therefore the connection pad number having needed for circuit board also increasingly increases Plus, however, the space on circuit board is limited, therefore spacing between connection pad is towards micro- spacing（fine pitch）Development.
In known technology, chip-packaging structure includes that chip, substrate, multiple connection pads, welding resisting layer and multiple solders are convex Block.Connection pad is configured on the surface of substrate.Welding resisting layer covers the surface of substrate, and with multiple weldering cover definition type（Solder Mask Defined, SMD）Opening, wherein these openings expose these connection pads respectively.These solder projections are covered each by this Protrude from a little connection pads and respectively these openings outer.Then made in the way of reflow again substrate and chip by be configured at both it Between these solder projections electrically and structural connectivity.
However, the trend in order to meet the micro- spacing of connection pad, the hatch bore diameter of welding resisting layer also reduces therewith, causes the vertical of opening Horizontal to be less useful for printing or being implanted into large-sized solder projection than increasing, the contraposition that also improve between solder projection and connection pad is stranded Difficulty.Meanwhile, when configuring large-sized solder projection on these connection pads and being engaged in the way of reflow with chip, these welderings Material projection can be presented molten condition because reflow is heated, because these connection pads are arranged on the surface of substrate with micro- spacing, because There is bridge joint phenomenon and short circuit problem in this, and cannot provide micro- in being easily caused reflow process in the solder projection of molten condition Away from electric connection structure.
The content of the invention
The present invention provides a kind of preparation method of chip-packaging structure, and the contraposition that it can be improved between solder and connection pad is accurate Degree, and avoid the phenomenon that solder bridge joint short circuit occurs during reflow solder.
The present invention more provides a kind of preparation method of chip-packaging structure, and it can be when connection pad be formed again, while formation is matched somebody with somebody Line layer is put, with Simplified flowsheet, improve production efficiency.
The preparation method of chip-packaging structure of the invention comprises the following steps.First, there is provided carrier.Carrier has Metal level.Then, patterning photoresist layer is formed on metal level.Patterning photoresist layer has multiple first openings with exposed portion Metal level.Then, it is interior in the first opening that multiple connection terminals are formed respectively, and connection terminal connection metal level.Then, by chip It is arranged on carrier, and connects multiple first connection pads of connection terminal and chip respectively by multiple connection conductor.Then, will After chip is arranged on carrier, patterning photoresist layer is removed.Afterwards, encapsulating material is formed on carrier.Encapsulating material bag Cover chip, connection conductor and metal level.Then, carrier and metal level are removed, to expose connection terminal.
The preparation method of chip-packaging structure of the invention comprises the following steps.First, there is provided carrier.Carrier has Metal level.Then, patterning photoresist layer is formed on metal level.Patterning photoresist layer exposed portion metal level.Then, the is formed One reconfiguration line layer is in being patterned on the exposed metal level of photoresist layer.First reconfiguration line layer includes multiple connection terminals And an at least wire pattern.Wire pattern connects corresponding connection terminal.Afterwards, patterning photoresist layer is removed.Then, by core Piece is arranged on carrier, and connects multiple first connection pads of connection terminal and chip respectively by multiple connection conductor.Then, Encapsulating material is formed on carrier.Encapsulating material coating chip, connection conductor, the first reconfiguration line layer and metal level. Then, carrier and metal level are removed, to expose the first reconfiguration line layer.
Based on above-mentioned, chip-packaging structure technique of the invention is by connecting the connection end of conductor and carrier in chip After son engagement, patterning photoresist layer is just removed, be not only beneficial to lifting connection conductor and the contraposition precision of connection terminal, more may be used Reduce connection conductor and connection terminal occurs solder bridging in engaging process and connects the phenomenon in turn resulting in short circuit.Additionally, of the invention Chip-packaging structure technique also can formed connection terminal when, the wire pattern being connected with connection terminal is synchronously formed, with right The electrical contact of connection terminal is reconfigured, thus can reduce the making number of times of follow-up reconfiguration line layer.Therefore, originally Invention can not only save manufacturing cost, more can lifting process yield and efficiency.
It is that features described above of the invention and advantage can be become apparent, special embodiment below, and coordinate appended accompanying drawing Describe in detail as follows.
Brief description of the drawings
Figure 1A to Fig. 1 J is the flow section of the preparation method according to a kind of chip-packaging structure of one embodiment of the invention Schematic diagram.
Fig. 2A to Fig. 2 G is the part stream of the preparation method according to a kind of chip-packaging structure of another embodiment of the present invention Journey generalized section.
Fig. 3 A to Fig. 3 I are the part stream of the preparation method according to a kind of chip-packaging structure of another embodiment of the present invention Journey generalized section.
Fig. 4 A to Fig. 4 I are the part stream of the preparation method according to a kind of chip-packaging structure of another embodiment of the present invention Journey generalized section.
【Symbol description】
100、200、300、400：Chip-packaging structure
110：Carrier
112：Metal level
120、320、420：Patterning photoresist layer
122、322：First opening
130、230、330、432：Connection terminal
140：Chip
142：First connection pad
150、250、350、450：Connection conductor
152：Weld cap
160、460：Encapsulating material
170：Reconfiguration line layer
172、472：First protective layer
174、474：Patterning conductor layer
176、476：Second protective layer
178、478：Weld pad
180：Second soldered ball
332：Wetting layer
430：First reconfiguration line layer
434：Wire pattern
470：Second reconfiguration line layer
Specific embodiment
Figure 1A to Fig. 1 J is the flow section of the preparation method according to a kind of chip-packaging structure of one embodiment of the invention Schematic diagram.Please also refer to Figure 1A and Figure 1B, the preparation method of the chip-packaging structure of the present embodiment comprises the following steps：First, Carrier 110 is provided, wherein, carrier 110 has metal level 112.Then, patterning photoresist layer 120 is formed in metal level 112 On.Patterning photoresist layer has multiple first openings 122 as shown in Figure 1B, with exposed portion metal level 112.Then, refer to Fig. 1 C, form multiple connection terminals 130 in the first opening 122 respectively, and the connection metal level 112 of connection terminal 130.Then, Referring to Fig. 1 D and Fig. 1 E, chip 140 is arranged on carrier 110, and by multiple connection conductors 150 respectively with Multiple first connection pads 142 of connection terminal 130 and chip 140 are connected.In the present embodiment, above-mentioned connection conductor 150 is pre- It is initially formed on the first connection pad 142 of chip 140, the mode of formation connection conductor 150 is, for example, plating or sputter.Afterwards, then It is electrically connected with connection terminal 130, wherein, the electric connection mode of connection conductor 150 and connection terminal 130 is e.g. led to The modes such as reflow, hot pressing or ultrasonic bonding are crossed to be engaged.In the present embodiment, connection terminal 130 is to be arranged at carrying The second connection pad on device 110, and conductor 150 is connected for conductive pole, its material can be gold, silver, copper or other similar conduction materials Matter.In other preferred embodiments, conductive pole top can be pre-formed weld cap 152 or also can on connection terminal 130 in advance Form weld cap（Do not illustrate）, for solder joints.Certainly, the present embodiment is illustrative only and is used, and the present invention is not intended to limit The species of connection conductor and connection terminal.
Additionally, the step that chip 140 is arranged on carrier 110 may include first to provide wafer（Do not illustrate）, and this is brilliant Circle include it is multiple be connected to each other and chip that array is arranged, then again cutting crystal wafer so that above-mentioned multiple chips are separated from one another. Then again by one of chip separated from one another（Namely chip 140）It is arranged on carrier 110.And connect conductor 150 can also be initially formed on the first connection pad of the chip that it is connected to each other and array is arranged before wafer cutting.
The reference picture that please continue 1F, after chip 140 is arranged on carrier 110, removes patterning as referring to figure 1E Photoresist layer 120.Afterwards, then as shown in Figure 1 G encapsulating material 160 is formed on carrier 110.The coating chip of encapsulating material 160 140th, connection conductor 150, connection terminal 130 and metal level 112.Then, then remove carrier 110 as shown in Figure 1 G and Metal level 112, to expose connection terminal 130 as shown in fig. 1H.
The reference picture that please continue 1I, after connection terminal 130 is exposed, forms reconfiguration line layer 170, wherein, reconfigure Line layer 170 covers the subregion of encapsulating material 160, and is electrically connected with the connection terminal 130 for exposing, with to connection Terminal 130 is reconfigured with the connecting point position that exterior electrical components are electrically connected with.In the present embodiment, formed and matched somebody with somebody again The step of putting line layer 170 may include the following steps：First, the first protective layer 172 is formed, wherein the first protective layer 172 is covered The subregion of encapsulating material 160, and expose connection terminal 130.Then, patterning conductor layer 174 is formed in the first protection On layer 172 and connection terminal 130, wherein patterning conductor layer 174 covers the part area of the first protective layer 172 as shown in Figure 1 I Domain is simultaneously connected with connection terminal 130.Then, the second protective layer 176 is re-formed in the first protective layer 172 and patterning conductor layer On 174, wherein the exposed portion of the second protective layer 176 patterning conductor layer 174.Afterwards, multiple weld pads 178 are re-formed in patterning On conductor layer 174, and weld pad 178 connects the patterning conductor layer 174 that the second protective layer 176 exposes respectively.In this way, chip 140 connecting point position can be reconfigured to the position of weld pad 178 by reconfiguration line layer 170 by the position of connection terminal 130 Put, be electrically connected with exterior electrical components.Form that above-mentioned patterning leads XIAN layers 174 and the mode of weld pad 178 is, for example, The mode such as plating or sputter.
Then, then as shown in figure iJ, multiple second soldered balls 180 are formed respectively on weld pad 178.In this way, i.e. preliminary complete The making of chip-packaging structure 100.The chip-packaging structure technique of the present embodiment is arranged on carrier 110 in chip 140 Afterwards, patterning photoresist layer 120 is just removed, is not only beneficial to the contraposition precision of lifting connection conductor 150 and connection terminal 130, Connection conductor 150 can more be reduced and connection terminal 130 occurs solder bridging in engaging process and connects the phenomenon in turn resulting in short circuit.
Fig. 2A to Fig. 2 G is the part stream of the preparation method according to a kind of chip-packaging structure of another embodiment of the present invention Journey generalized section.Herein it should be noted that, the present embodiment continues to use the element numbers and partial content of previous embodiment, wherein adopting Be denoted by the same reference numerals identical or approximate element, and eliminates the explanation of constructed content.On clipped Explanation can refer to previous embodiment, it is no longer repeated for the present embodiment.
The step of preparation method of the chip-packaging structure of the present embodiment continues to use the Figure 1A to Fig. 1 C in previous embodiment, That is, the preparation method of the chip-packaging structure of the present embodiment includes first carrying out as the Figure 1A's to Fig. 1 C in previous embodiment Step, in formation connection terminal 130 as shown in Figure 1 C after in the first opening 122 of patterning photoresist layer 120, then the ginseng that continues According to Fig. 2A and Fig. 2 B, chip 140 is arranged on carrier 110, and by multiple connection conductors 250 respectively with connection terminal 130 and multiple first connection pads 142 of chip 140 connect.In the present embodiment, connection terminal 130 is as previously described in a prior embodiment Second connection pad, and it is then the first soldered ball to connect conductor 250.Connection conductor 250 can for example be previously formed in the first of chip 140 and connect On pad 142, then it is electrically connected with connection terminal 130, and connection conductor 250 and connection terminal 130 and is connected conductor 250 Between the first connection pad 142 engaged by modes such as reflow, hot pressing, ultrasonic bonding.Preferably implement in another In example, connection conductor 250 can use plating, sputter, screen painting or Place（ball drop）Mode be formed at the first connection pad On 142.Significantly, since patterning photoresist layer 120 is not yet removed in this stage, along with the shape of connection terminal 130 Can patterning photoresist layer 120 be relatively low into thickness, therefore when engagement, the patterning photoresist layer 120 has companion chip 140 Connection conductor 250 is positioned at the effect of connection terminal 130.
Then, please continue reference picture 2C, after the setting of chip 140 is formed on carrier 110, remove as shown in Figure 2 B Patterning photoresist layer 120.Afterwards, then as shown in Figure 2 D encapsulating material 160 is formed on carrier 110.Encapsulating material 160 is such as Coating chip 140, connection conductor 250, connection terminal 130 and metal level 112 described in previous embodiment.Then, then remove such as Carrier 110 and metal level 112 shown in Fig. 2 D, to expose connection terminal 130 as shown in Figure 2 E.
Then, Fig. 2 F are refer to, after connection terminal 130 is exposed, reconfiguration line layer 170 is formed, wherein, reconfigure Line layer 170 as previously described in a prior embodiment include the first protective layer 172, patterning conductor layer 174, the second protective layer 176 and Weld pad 178.Detailed configuration mode and manufacturing process as reconfiguration line layer 170 can refer to described in previous embodiment, in This is repeated no more.Then, then as shown in Figure 2 G, multiple second soldered balls 180 are formed respectively on weld pad 178, make connecing for chip 140 Point position can be reconfigured to the position of weld pad 178 by reconfiguration line layer 170 by the position of connection terminal 130, and be passed through Second soldered ball 180 is electrically connected with exterior electrical components.In this way, the i.e. preliminary making for completing chip-packaging structure 200.
Fig. 3 A to Fig. 3 I are the part stream of the preparation method according to a kind of chip-packaging structure of another embodiment of the present invention Journey generalized section.Herein it should be noted that, the present embodiment continues to use the element numbers and partial content of previous embodiment, wherein adopting Be denoted by the same reference numerals identical or approximate element, and eliminates the explanation of constructed content.On clipped Explanation can refer to previous embodiment, it is no longer repeated for the present embodiment.
The step of preparation method of the chip-packaging structure of the present embodiment continues to use the Figure 1A in previous embodiment, that is, Say, the preparation method of the chip-packaging structure of the present embodiment includes first providing the carrier with metal level 112 as shown in Figure 1A After 110, then the reference picture 3A that continues, patterning photoresist layer 320 is formed on metal level 112.Patterning photoresist layer 320 such as Fig. 3 A institutes Show with multiple first openings 322, with exposed portion metal level 112.Then, Fig. 3 B are refer to, multiple connection ends is formed respectively Son 330 in first opening 322 in, and connection terminal 330 connection metal level 112.In the present embodiment, connection terminal 330 is to lead Electric projection, therefore, the thickness for being used to be formed the patterning photoresist layer 320 of connection terminal 330 can be substantially greater than foregoing pattern Change the thickness of photoresist layer 120.The generation type of connection terminal 330 can be plating, sputter or screen painting etc..Then, refer to Fig. 3 C and Fig. 3 D, chip 140 is arranged on carrier 110, and by multiple connection conductors 350 respectively with connection terminal 330 And multiple first connection pads 142 of chip 140 are connected.In the present embodiment, connection conductor 350 is the first soldered ball.Connection conductor 350 Can for example be initially formed on the first connection pad 142 of chip 140, then be electrically connected with connection terminal 330 in flip mode.In In preferred embodiment, connection conductor 350 with one layer is further provided with the composition surface of connection terminal 330 can aid in what is engaged Wetting layer 332（wettable layer）, e.g. nickel, golden or organic scaling powder（organic solderability Preservation, OSP）, and between connection conductor 350 and connection terminal 330 and the connection connection pad 142 of conductor 350 and first It is to be engaged by modes such as reflow, hot pressing or ultrasonic bonding.Significantly, since patterning photoresist layer 320 Not yet removed in this stage, therefore the connection conductor 350 with companion chip 140 is positioned at the effect of connection terminal 330.
Then, please continue reference picture 3E, after chip 140 is arranged on carrier 110, remove figure as shown in Figure 3 D Case photoresist layer 320.Afterwards, then as illustrated in Figure 3 F encapsulating material 160 is formed on carrier 110.Encapsulating material 160 is such as previous Coating chip 140, connection conductor 350, connection terminal 330 and metal level 112 described in embodiment.Then, then remove such as Fig. 3 F Shown carrier 110 and metal level 112, to expose connection terminal 330 as shown in Figure 3 G.
Then, Fig. 3 H are refer to, after connection terminal 330 is exposed, reconfiguration line layer 170 is formed, wherein, reconfigure Line layer 170 as in the foregoing embodiment include the first protective layer 172, patterning conductor layer 174, the second protective layer 176 and Weld pad 178.Detailed configuration mode and manufacturing process as reconfiguration line layer 170 can refer to previous embodiment, in this not Repeat again.Then, then as shown in fig. 31, formed respectively multiple second soldered balls 180 on weld pad 178, make chip 140 contact position The position that can reconfigure to weld pad 178 by the position of connection terminal 330 by reconfiguration line layer 170 is put, and by second Soldered ball 180 is electrically connected with exterior electrical components.In this way, the i.e. preliminary making for completing chip-packaging structure 300.
Fig. 4 A to Fig. 4 I are the part stream of the preparation method according to a kind of chip-packaging structure of another embodiment of the present invention Journey generalized section.Herein it should be noted that, the present embodiment continues to use the element numbers and partial content of previous embodiment, wherein adopting Be denoted by the same reference numerals identical or approximate element, and eliminates the explanation of constructed content.On clipped Explanation can refer to previous embodiment, it is no longer repeated for the present embodiment.
The step of preparation method of the chip-packaging structure of the present embodiment continues to use the Figure 1A in previous embodiment, that is, Say, the preparation method of the chip-packaging structure of the present embodiment includes first providing the carrier with metal level 112 as shown in Figure 1A After 110, then the reference picture 4A that continues, patterning photoresist layer 420 is formed on metal level 112.The patterning exposed portion of photoresist layer 420 Metal level 112.Then, as shown in Figure 4 B, the first reconfiguration line layer 430 is formed in being patterned the exposed gold of photoresist layer 420 On category layer 112.First reconfiguration line layer 430 includes multiple connection terminals 432 and an at least wire pattern 434.Wire figure Case 434 connects corresponding connection terminal 432 as shown in Figure 4 B.In the present embodiment, connection terminal 432 is the second connection pad.Please join According to Fig. 4 C, the patterning photoresist layer 420 shown in Fig. 4 B is removed, and as shown in Fig. 4 D and Fig. 4 E, chip 140 is arranged at carrier On 110, and connect multiple first connection pads 142 of connection terminal 432 and chip 140 respectively by multiple connection conductor 450.At this In embodiment, connection conductor 450 is the first soldered ball, and certainly, the present invention is not limited thereto, and in other embodiments, connection is led Body also can be conductive pole.Connection conductor 450 can be for example initially formed on the first connection pad 142 of chip 140, then with connection terminal 432 are electrically connected, and are between connection conductor 450 and connection terminal 432 and the connection connection pad 142 of conductor 450 and first Engaged by modes such as reflow, hot pressing or ultrasonic bonding.
Additionally, the step that chip 140 is arranged on carrier 110 can include first providing wafer as previously described（Do not paint Show）, and this wafer include multiple be connected to each other and array arrangement chip, then again cutting crystal wafer so that above-mentioned multiple chips It is separated from one another.Then again by one of chip separated from one another（Namely chip 140）It is arranged on carrier 110.And Connection conductor 150 can be also initially formed on the first connection pad of the chip that it is connected to each other and array is arranged before wafer cutting.
The reference picture that please continue 4F, forms encapsulating material 460 on carrier 110.The coating chip 140 of encapsulating material 460, company Connect conductor 450, the first reconfiguration line layer 430 and metal level 112.Then, the carrier 110 and gold shown in Fig. 4 F are removed Category layer 112, to expose the first reconfiguration line layer 430 as shown in Figure 4 G.
The reference picture that please continue 4H, after exposing the first reconfiguration line layer 430, forms the second reconfiguration line layer 470, its In the second reconfiguration line layer 470 cover the subregion of encapsulating material 460, it is and electrical with the first reconfiguration line layer 430 Connection, reconfigures with to the connecting point position that connection terminal 432 and exterior electrical components are electrically connected with.In this implementation Example in, formed the second reconfiguration line layer 470 the step of may include the following steps：First, the first protective layer 472 is formed, wherein First protective layer 472 covers the subregion of encapsulating material 460, and exposes connection terminal 432 and part wire pattern 434.Then, patterning conductor layer 474 is formed on the first protective layer 472 and connection terminal 432, wherein patterning conductor layer The partial area of 474 the first protective layers 472 of covering simultaneously connects connection terminal 432 and part that the first protective layer 472 exposes Wire pattern 434.Afterwards, the second protective layer 476 is formed in the first protective layer 472 and is patterned on conductor layer 474, wherein the The exposed portion of two protective layer 476 patterns conductor layer 474.Then multiple weld pads 478 are re-formed on patterning conductor layer 474. Weld pad 478 connects the patterning conductor layer 474 that the second protective layer 476 exposes respectively.
Then, then as shown in fig. 41, multiple second soldered balls 180 are formed respectively on weld pad 478.In this way, i.e. preliminary complete The making of chip-packaging structure 400.The chip-packaging structure technique of the present embodiment is synchronous to be formed when connection terminal 432 is formed The wire pattern 434 being connected with connection terminal 432, is reconfigured with the electrical contact to connection terminal 432.Therefore can subtract The making number of times of few follow-up reconfiguration line layer and cost-effective, and then lifting process efficiency.
In sum, chip-packaging structure technique of the invention is by connecting the connection end of conductor and carrier in chip After son engagement, patterning photoresist layer is just removed, be not only beneficial to lifting connection conductor and the contraposition precision of connection terminal, more may be used Reduce connection conductor and connection terminal occurs solder bridging in engaging process and connects the phenomenon in turn resulting in short circuit.Additionally, of the invention Chip-packaging structure technique also can formed connection terminal when, the wire pattern being connected with connection terminal is synchronously formed, with right The electrical contact of connection terminal is reconfigured, thus can reduce the making number of times of follow-up reconfiguration line layer.Therefore, originally Invention not only can lifting process yield, more can lifting process efficiency.
Although the present invention is disclosed above with embodiment, so it is not limited to the present invention, any art Middle tool usually intellectual, it is without departing from the spirit and scope of the present invention, therefore of the invention when a little change and retouching can be made Protection domain when being defined depending on as defined in claim.

Claims (19)

1. a kind of preparation method of chip-packaging structure, it is characterised in that including：
Carrier is provided, the carrier has metal level；
Patterning photoresist layer is formed on the metal level, the patterning photoresist layer has multiple first openings with the exposed portion gold Category layer；
It is interior in the plurality of first opening that multiple connection terminals are formed respectively, and the plurality of connection terminal connects the metal level；
Chip is arranged on the carrier, and the plurality of connection terminal is connected with the chip by multiple connection conductor respectively Multiple first connection pads；
After the chip is arranged on the carrier, the patterning photoresist layer is removed；
Encapsulating material is formed on the carrier, the encapsulating material coats the chip, the plurality of connection conductor and the metal level； And
The carrier and the metal level are removed, to expose the plurality of connection terminal；
After the metal level is removed, reconfiguration line layer is formed, the wherein reconfiguration line layer covers the portion of the encapsulating material Subregion, and be electrically connected with the plurality of connection terminal.
2. the preparation method of chip-packaging structure as claimed in claim 1, it is characterised in that the plurality of connection terminal with should Before multiple first connection pads are connected by the plurality of connection conductor, the plurality of connection conductor is initially formed in the plurality of first connection pad On.
3. the preparation method of chip-packaging structure as claimed in claim 1, it is characterised in that the plurality of connection conductor is conduction Post, the plurality of connection terminal is the second connection pad.
4. the preparation method of chip-packaging structure as claimed in claim 1, it is characterised in that the plurality of connection conductor is first Soldered ball, the plurality of connection terminal is the second connection pad.
5. the preparation method of chip-packaging structure as claimed in claim 2, it is characterised in that the plurality of connection conductor is first Soldered ball, the plurality of connection terminal is conductive projection.
6. the preparation method of chip-packaging structure as claimed in claim 5, it is characterised in that the plurality of connection conductor is multiple First soldered ball, the plurality of connection terminal is conductive projection.
7. the preparation method of chip-packaging structure as claimed in claim 1, it is characterised in that the plurality of connection conductor is more with this It is to be engaged by reflow, hot pressing or ultrasonic bonding between individual connection terminal.
8. the preparation method of chip-packaging structure as claimed in claim 1, it is characterised in that the plurality of connection conductor is to utilize Plating, sputter, printing or Place mode are formed on the plurality of first connection pad.
9. the preparation method of chip-packaging structure as claimed in claim 1, it is characterised in that form the reconfiguration line layer Step is further included：
The first protective layer is formed, wherein first protective layer covers the subregion of the encapsulating material, and exposes the plurality of company Connecting terminal；
Patterning conductor layer is formed on first protective layer and the plurality of connection terminal, wherein the patterning conductor layer is covered The partial area of first protective layer simultaneously connects the plurality of connection terminal；And
The second protective layer is formed on first protective layer and the patterning conductor layer, wherein the second protective layer exposed portion The patterning conductor layer；And
Multiple weld pads are formed on the patterning conductor layer, the plurality of weld pad connects the figure that second protective layer exposes respectively Case conductor layer.
10. the preparation method of chip-packaging structure as claimed in claim 9, it is characterised in that further include：
Multiple second soldered balls are formed respectively on the plurality of weld pad.
A kind of 11. preparation methods of chip-packaging structure, it is characterised in that including：
Carrier is provided, the carrier has metal level；
Patterning photoresist layer is formed on the metal level, the patterning photoresist layer exposed portion metal level；
The first reconfiguration line layer is formed on by the exposed metal level of the patterning photoresist layer, first reconfiguration line layer Including multiple connection terminals and an at least wire pattern, an at least wire pattern connects a corresponding at least connection terminal；
Remove the patterning photoresist layer；
Chip is arranged on the carrier, and the plurality of connection terminal is connected with the chip by multiple connection conductor respectively Multiple first connection pads；
Encapsulating material is formed on the carrier, the encapsulating material coats the chip, the plurality of connection conductor, this first reconfigures Line layer and the metal level；
The carrier and the metal level are removed, to expose first reconfiguration line layer.
The preparation method of 12. chip-packaging structures as claimed in claim 11, it is characterised in that the plurality of connection terminal with Before the plurality of first connection pad is connected by the plurality of connection conductor, the plurality of connection conductor is formed at the plurality of first connection pad On.
The preparation method of 13. chip-packaging structures as claimed in claim 11, it is characterised in that the plurality of connection conductor is to lead Electric post, the plurality of connection terminal is the second connection pad.
The preparation method of 14. chip-packaging structures as claimed in claim 11, it is characterised in that the plurality of connection conductor is the One soldered ball, the plurality of connection terminal is the second connection pad.
The preparation method of 15. chip-packaging structures as claimed in claim 11, it is characterised in that the plurality of connection conductor with should It is to be engaged by reflow, hot pressing or ultrasonic bonding between multiple connection terminals.
The preparation method of 16. chip-packaging structures as claimed in claim 11, it is characterised in that the plurality of connection conductor is profit It is formed on the plurality of first connection pad with plating, sputter, printing or Place mode.
The preparation method of 17. chip-packaging structures as claimed in claim 11, it is characterised in that further include：
After removing the metal level, the second reconfiguration line layer is formed, the wherein reconfiguration line layer covers the portion of the encapsulating material Subregion, and be electrically connected with first reconfiguration line layer.
The preparation method of 18. chip-packaging structures as claimed in claim 17, it is characterised in that form this and second reconfigure line The step of road floor, further includes：
The first protective layer is formed, wherein first protective layer covers the subregion of the encapsulating material, and exposes the plurality of company Connecting terminal and the partly wire pattern；
Patterning conductor layer is formed on first protective layer and first reconfiguration line layer, the patterning conductor layer is covered The partial area of first protective layer simultaneously connects the plurality of connection terminal that first protective layer exposes and the part wire Pattern；And
The second protective layer is formed on first protective layer and the patterning conductor layer, the second protective layer exposed portion figure Case conductor layer；And
Multiple weld pads are formed on the patterning conductor layer, the plurality of weld pad connects the figure that second protective layer exposes respectively Case conductor layer.
The preparation method of 19. chip-packaging structures as claimed in claim 18, it is characterised in that further include：
Multiple second soldered balls are formed respectively on the plurality of weld pad.
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