CN104124201B - The forming method of conductive structure - Google Patents
The forming method of conductive structure Download PDFInfo
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- CN104124201B CN104124201B CN201310156920.8A CN201310156920A CN104124201B CN 104124201 B CN104124201 B CN 104124201B CN 201310156920 A CN201310156920 A CN 201310156920A CN 104124201 B CN104124201 B CN 104124201B
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- forming method
- opening
- conductive structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76865—Selective removal of parts of the layer
Abstract
A kind of forming method of conductive structure, including：Substrate is provided, the substrate surface has dielectric layer, has opening in the dielectric layer；Seed Layer is formed in the side wall and lower surface of the opening；Modified ion is injected to the Some seeds layer of the sidewall surfaces close to open top using ion implantation technology；After the ion implantation technology, thermal anneal process is carried out, the Some seeds layer of injection modified ion is formed sacrifice layer, the material of the sacrifice layer is different from the material of Seed Layer；Remove the sacrifice layer；After the sacrifice layer is removed, the conductive layer of the full opening of filling is formed in the opening.Tight, quality are good in the conductive structure formed.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, more particularly to a kind of forming method of conductive structure.
Background technology
In ic manufacturing process, the electricity being used for frequently with conductive plunger between device interconnects.With integrated circuit
The fast development of manufacturing technology, promote the size of semiconductor devices constantly to reduce, make to be formed the technique of conductive plunger also by
Challenge.
Prior art forms the cross-sectional view of the process of conductive plunger as shown in Figures 1 to 4.
Fig. 1 is refer to, the surface of substrate 100 has dielectric layer 101, has in the dielectric layer 101 and is used to form conductive insert
The opening 102 of plug.
Fig. 2 is refer to, barrier layer 105 and kind are deposited in the surface of substrate 100,102 side wall that is open and lower surface
Sublayer 103.
Fig. 3 is refer to, conductive film 104, the conductive film are formed on the surface of Seed Layer 103 using electroplating technology
104 surface is higher than the surface of dielectric layer 101.
Fig. 4 is refer to, the conductive film 104 higher than the surface of dielectric layer 101 is removed using CMP process, in institute
State and conductive plunger 104a is formed in opening.
However, constantly being reduced with the characteristic size of device, the width dimensions of the conductive plunger also accordingly reduce, institute's shape
Into conductive plunger content be also easy to produce space（Void）, the conductive plunger formed is of poor quality, easily influences device performance.
The content of the invention
The present invention is solved the problems, such as to be to provide a kind of forming method of conductive structure, made in formed conductive structure without sky
Gap, quality are good.
To solve the above problems, the present invention provides a kind of forming method of conductive structure, including：Substrate, the base are provided
Basal surface has dielectric layer, has opening in the dielectric layer；Seed Layer is formed in the side wall and lower surface of the opening；Adopt
Modified ion is injected to the Some seeds layer of the sidewall surfaces close to open top with ion implantation technology；In the ion implanting
After technique, thermal anneal process is carried out, the Some seeds layer of injection modified ion is formed sacrifice layer, the material of the sacrifice layer
It is different from the material of Seed Layer；Remove the sacrifice layer；After the sacrifice layer is removed, it is full that filling is formed in the opening
The conductive layer of the opening.
Optionally, the material of the Seed Layer is copper, and the material of the conductive layer is copper.
Optionally, the formation process of the conductive layer is：Using electroplating technology or chemical plating process in the Seed Layer table
Face forms the conductive film of filling full gate mouth；Conductive film higher than dielectric layer surface is removed using CMP process,
And expose dielectric layer surface.
Optionally, the modified ion is oxonium ion, and the sacrifice layer is cupric oxide.
Optionally, the technique for removing sacrifice layer is wet-etching technology, and etching liquid is acetic acid.
Optionally, the ion implantation technology is：Implant angle is 0 degree~30 degree, and injection metering is 1*105~1*107It is former
Son/square centimeter, Implantation Energy are 50KeV~150KeV.
Optionally, during the ion implantation technology, the substrate is rotated horizontally, the angle of the horizontal rotation is
0 degree or 180 degree.
Optionally, the forming method of the opening is：Mask layer is formed in dielectric layer surface, the mask layer exposes portion
Divide dielectric layer surface；Using the mask layer as mask, anisotropic dry etch process is used to etch the dielectric layer to be formed
Opening.
Optionally, the mask layer includes silicon oxide layer and the metal nitride layer positioned at silicon oxide layer surface, described
The material of metal nitride layer includes titanium nitride or tantalum nitride.
Optionally, the Seed Layer is also formed into top and the sidewall surfaces of the mask layer, and the modified ion is also noted
Enter at the top of mask layer and in the Seed Layer of sidewall surfaces.
Optionally, in addition to：Stop-layer is formed in substrate surface, dielectric layer is formed at the stopping layer surface, described to stop
Only the material of layer is different from dielectric layer, and the technique of the etch media layer stops at the stopping layer surface, and in the etching
After the technique of dielectric layer, the stop-layer of open bottom is removed.
Optionally, the formation process of the Seed Layer is atom layer deposition process or physical gas-phase deposition.
Optionally, the thermal anneal process is：Temperature is 150 degrees Celsius~300 degrees Celsius, and the time is 10 minutes~10 points
Clock.
Optionally, in addition to：Before the Seed Layer is formed, in the side wall and bottom of dielectric layer surface and opening
Surface forms barrier layer, and the material on the barrier layer is titanium nitride or tantalum nitride；Seed Layer is formed in the barrier layer surface.
Optionally, the substrate includes：Semiconductor substrate；It is formed at the device of the semiconductor substrate surface；It is formed at
Semiconductor substrate surface and the insulating barrier for being electrically isolated the device.
Optionally, the substrate is Semiconductor substrate.
Optionally, the material of the dielectric layer is low-K material or ultra low-K material.
Optionally, the depth-to-width ratio of the opening is more than 5:1.
Optionally, in addition to：Conductive layer higher than dielectric layer surface is removed using CMP process, until exposure
Untill going out dielectric layer surface, conductive plunger is formed in opening.
Compared with prior art, technical scheme has advantages below：
After the side wall and lower surface of opening form Seed Layer, using ion implantation technology to close to open top
The Some seeds layer injection modified ion of sidewall surfaces, after follow-up thermal annealing, injects the Some seeds layer of modified ion
Form sacrifice layer；Because cambial material is different from the Seed Layer for not being injected into modified ion, therefore the sacrifice layer and kind
Sublayer has higher selection in etching technics, can either remove the sacrifice layer by etching technics, and retain and do not noted
Enter the Seed Layer of modified ion；Because the modified ion is injected in the Seed Layer of open top, i.e., sacrifice layer is located at and leaned on
The sidewall surfaces of nearly open top, after removing sacrifice layer, the width dimensions of open top can be made to become big, after suppressing
It is continuous form conductive layer during, open top close too early and in conductive layer interstitial problem.The conduction formed
It is fine and close in layer, its electric conductivity can be ensured, make formed performance of semiconductor device more stable.
Further, the material of the Seed Layer is copper, and the modified ion is oxonium ion, that is, the material of the sacrifice layer formed
Expect for cupric oxide；Because cupric oxide is basic anhydride, easily with acidulous material react neutralize, and metallic copper will not and weak acid
Property substance reaction, therefore use acetic acid as etching liquid and can remove sacrifice layer of the cupric oxide for material, while will not be right
The remaining Seed Layer using copper as material causes to damage；While open top width dimensions are increased, remaining seed ensure that
The pattern of layer surface is good, is advantageous to be subsequently formed the measured conductive layer of matter.
Further, the modified ion injected tilts relative to dielectric layer surface, model of the angle of inclination at 0 degree to 30 degree
In enclosing, by controlling the angle of the ion implantation technology, the bottom of ion implanted regions can be controlled to arrive dielectric layer surface
Distance, that is, it is controllable to the distance of dielectric layer surface, the size of sacrifice layer to control the sacrifice layer bottom that is subsequently formed；Secondly, lead to
The depth of injection ion can be controlled by crossing control Implantation Energy, so as to the thickness for the sacrifice layer that controling power is subsequently formed；Therefore,
The size and thickness of the sacrifice layer of required removal are controllable, advantageously form the measured conductive layer of matter.
Brief description of the drawings
Fig. 1 to Fig. 4 is the cross-sectional view for the process that prior art forms conductive plunger；
Fig. 5 to Figure 12 is the cross-sectional view of the forming process of the conductive structure described in the embodiment of the present invention.
Embodiment
As stated in the Background Art, the conductive plunger content that prior art is formed is also easy to produce space, and its of poor quality, performance is not
It is stable.
Study and find by the present inventor, please continue to refer to Fig. 1 to Fig. 4, as device feature size constantly contracts
Small, the width at the top of opening 102 also constantly reduces, and causes the depth-to-width ratio of the opening 102（Aspect Ratio）Improve,
The opening depth-to-width ratio for being presently used in forming conductive plunger is more than 5:1.The Seed Layer 103 uses atom layer deposition process or physics
Gas-phase deposition is formed at the side wall and lower surface of opening 102, however, with the depth-to-width ratio increase of opening 102, opening
102 top width size reduction, the material of Seed Layer are more deposited in the sidewall surfaces close to the top of opening 102；Cause shape
Into after Seed Layer, 102 top width sizes of opening are less than bottom width size；It is being subsequently formed the process of conductive film 104
In, when easily causing not to be filled full also in opening 102, the top of the opening 102 has closed, so as to be formed in opening
Space, and then produce space in the conductive plunger 104a formed after glossing.The space easily influences conductive plunger
104a electric conductivity, make formed device performance bad.
Further study by the present inventor, after the side wall and lower surface of opening form Seed Layer, adopt
Modified ion is injected to the Some seeds layer of the sidewall surfaces close to open top with ion implantation technology, in follow-up thermal annealing
Afterwards, the Some seeds layer for injecting modified ion forms sacrifice layer；Material due to sacrifice layer is not with being injected into modified ion
Seed Layer is different, therefore the sacrifice layer has higher selection with Seed Layer in etching technics, can by etching technics
The sacrifice layer is enough removed, and retains the Seed Layer for not being injected into modified ion；Because the modified ion is injected close to opening
In the Seed Layer at top, i.e., sacrifice layer is located at the sidewall surfaces close to open top, after removing sacrifice layer, can make open top
Width dimensions become big, so as to suppress during being subsequently formed conductive layer, open top close too early and in conductive layer
Interior interstitial problem.It is fine and close in the conductive plunger formed, its electric conductivity can be ensured, make formed semiconductor device
Part performance is more stable.
It is understandable to enable the above objects, features and advantages of the present invention to become apparent, below in conjunction with the accompanying drawings to the present invention
Specific embodiment be described in detail.
Fig. 5 to Figure 12 is the cross-sectional view of the forming process of the conductive structure described in the embodiment of the present invention.
It refer to Fig. 5, there is provided substrate 200, the surface of substrate 200 have dielectric layer 201, in the surface shape of dielectric layer 201
Into mask layer 202, the mask layer 202 exposes the surface of certain media layer 201.
The substrate 200 provides workbench for subsequent technique；In the present embodiment, the substrate 200 includes；Semiconductor
Substrate（It is not shown）, be formed at the device of the semiconductor substrate surface（It is not shown）And it is formed at semiconductor substrate surface
And it is electrically isolated the insulating barrier of the device（It is not shown）；The Semiconductor substrate includes silicon substrate, silicon-Germanium substrate, carborundum lining
Bottom, silicon-on-insulator（SOI）Substrate, germanium on insulator（GOI）Substrate, glass substrate or III-V substrate（Such as nitrogen
Change gallium or GaAs etc.）；The device includes transistor, memory, capacitor, inductor, fuse or metal interconnection wire etc.；Institute
The material for stating insulating barrier is silica, silicon nitride or silicon oxynitride.The conductive plunger subsequently formed is used to realize the device
Point connection in integrated circuits.In another embodiment, the substrate is Semiconductor substrate, the conductive plunger subsequently formed
Positioned at semiconductor substrate surface.
The material of the dielectric layer 201 is low-K material or ultra low-K material, can effectively be electrically isolated follow-up formed and lead
Electric plug；The formation process of the dielectric layer 201 is depositing operation, it is preferred that chemical vapor deposition method；The dielectric layer
It is subsequently used for forming conductive plunger in 201.
The mask layer 202 includes silicon oxide layer（It is not shown）And the metal nitride layer positioned at silicon oxide layer surface
（It is not shown）, the material of the metal nitride layer includes titanium nitride or tantalum nitride；The mask layer 202 is used to define follow-up need
Form the position of opening；The formation process of the mask layer is：In dielectric layer surface deposition mask film, in the present embodiment
In, the mask film includes silicon oxide film and the metal nitride film positioned at silicon oxide film surface；Using photoetching
Technique forms photoresist layer in the mask film surface, and the photoresist layer defines the position for needing to form opening；With light
Photoresist layer is mask, etches the mask film untill the surface of dielectric layer 201 is exposed, and forms mask layer 202, goes afterwards
Except photoresist layer.
In one embodiment, stop-layer is formed on the surface of substrate 200（It is not shown）, the dielectric layer 201 is formed at described
Stop layer surface, the material of the stop-layer is different from dielectric layer 201, and the formation process of the stop-layer is depositing operation, example
Such as chemical vapor deposition method；During subsequent etching opening, stop-layer has etching selection relative to dielectric layer 201
Property, the technique that subsequent etching dielectric layer forms opening stops at the stopping layer surface, avoids etching technics to the surface of substrate 200
Cause to damage.After the technique of the etch media layer, wet processing can be used to remove the stop-layer of open bottom.
Fig. 6 is refer to, is mask with the mask layer 202, the medium is etched using anisotropic dry etch process
Layer 201, and form opening 203.
The formation process of the opening 203 is anisotropic dry etch process, such as plasma dry etch work
Skill, the design parameter of the etching technics determine according to the material and thickness of dielectric layer and the size of opening 203.
As the characteristic size of semiconductor devices persistently reduces, the integrated level of integrated circuit improves constantly, cause conductive insert
The needs of width dimensions of plug also constantly reduce, and the conductive plunger needs to meet electricity interconnection in integrated circuit, its length is not
Can accordingly it reduce, so as to cause the depth-to-width ratio of the opening 203 for forming conductive plunger to increase.In the present embodiment, it is described to open
The top width size of mouth 203 is 30nm~50nm, and the depth-to-width ratio of the opening 203 is more than 5:1.
It is follow-up to need to form barrier layer and Seed Layer using side wall and lower surface of the depositing operation in the opening 203,
The conductive film of filling full gate mouth is formed in seed layer surface with electroplating technology again, to form conductive plunger.However, with described
The depth-to-width ratio increase of opening 203, the width dimensions at the top of opening 203 are reduced, and conductive film is subsequently formed in opening 203
During, easily it is closed when opening 203 is also not filled by full, causes to produce space in formed conductive layer.
Fig. 7 is refer to, barrier layer 210 is formed in the side wall and lower surface of the opening 203, in the barrier layer surface
Form Seed Layer 204.
The material on the barrier layer 210 is titanium nitride or tantalum nitride, and the thickness on the barrier layer 210 is 50 angstroms~150 angstroms,
Formation process is atom layer deposition process or physical gas-phase deposition；The barrier layer 210 is used to prevent what is be subsequently formed from leading
The material of electric layer spreads into dielectric layer 201 or substrate 200, ensure that the electric performance stablity of formed conductive plunger.
The material of the Seed Layer 204 is copper, and thickness is 50 angstroms~150 angstroms, and the formation process of the Seed Layer 204 is original
Sublayer depositing operation or physical gas-phase deposition；The Seed Layer 204 is conductive in subsequent electroplating process, and in the seed
204 superficial growth conductive material of layer fill the conductive film of opening 203 to be formed.
In the present embodiment, due to not removing mask layer 202 before barrier layer 210 is formed, the Seed Layer 204 passes through
Depositing operation is also formed into top and the sidewall surfaces of the mask layer 202, the conductive film that the mask layer 202 is subsequently formed
It is also located at the surface of mask layer 202；The mask layer 202 can define stopping during subsequent chemical-mechanical polishing conductive film
Position.
Because the depth-to-width ratio of the opening 203 is larger, more than 5:1, and 203 top width sizes of the opening are smaller, are
30nm~50nm, the Seed Layer 204 and the thinner thickness of barrier layer 210 of 203 bottoms of opening are formed at, meanwhile, pushed up close to opening 203
The Seed Layer 203 of portion's side wall compares thick；It is described when subsequently forming conductive film on the surface of Seed Layer 203 using electroplating technology
The top of opening 203 easily first closes, and is not filled full also in the opening 203 simultaneously, makes in formed conductive plunger
With space, the conductive capability of the conductive plunger is influenceed, the stability of device reduces.
Fig. 8 is refer to, the Some seeds layer 204 using ion implantation technology to the sidewall surfaces close to the top of opening 203
Inject modified ion.
The modified ion is used for the material modification for making the Seed Layer 204 of the sidewall surfaces close to the top of opening 203, so as to
After follow-up thermal anneal process, make the material of the Some seeds layer 204 of injection modified ion, the kind with unimplanted modified ion
The material of sublayer 204 is different, therefore the Seed Layer 204 injected the part and the part of unimplanted modified ion of modified ion
Between there is Etch selectivity, can subsequently use etching technics to remove and the part of modified ion was injected in Seed Layer 204, and
Retain the part of 204 unimplanted modified ion of Seed Layer；Moreover, the part that the Seed Layer 204 injected modified ion is located at
Sidewall surfaces close to the top of opening 203, i.e., can remove the lug boss that Seed Layer 204 is located at the top sidewall surface of opening 203
Point, so as to suppress in subsequent electroplating process, the problem of closure too early at the top of opening 203.
In the present embodiment, the modified ion is oxonium ion, then after follow-up thermal anneal process, by the Seed Layer
The sacrificial layer material that 204 parts for injecting modified ion are formed is cupric oxide, and the cupric oxide can be sent out with acidulous material
Raw reaction, and acidulous material will not cause to damage to the Seed Layer 204 using copper as material, therefore sacrifice layer can removed
Meanwhile retain the remaining Seed Layer 204 of unimplanted modified ion.
The ion implantation technology is：Implant angle be 0 degree~30 degree, injection metering be 1*105~1*107 atoms/put down
Square centimetre, Implantation Energy is 50KeV~150KeV；During the ion implantation technology, the substrate 200 is rotated horizontally,
The angle of the horizontal rotation is 0 degree or 180 degree；Wherein, 0 degree is rotated horizontally i.e. in ion implantation process, not rotating substrate
200；And rotate horizontally 180 degree and refer to：The substrate 200 is set first for initial position and carries out ion implanting, makes institute afterwards
State substrate 200 and rotate 180 degree around its central horizontal, and continue ion implanting；Substrate 200 is set to rotate horizontally 180 degree
Modified ion is entered the sidewall surfaces at any close top of opening 203 of the opening 203, make follow-up opening 203 any close
The sidewall surfaces at top form sacrifice layer.In the present embodiment, the Seed Layer 204 be also formed into mask layer 202 top and
Sidewall surfaces, then the modified ion also inject in the Seed Layer 204 of the top of mask layer 202 and sidewall surfaces.
It should be noted that by being adjusted to the parameter of ion implantation technology, such as strengthen Implantation Energy, it can control
The depth of system injection modified ion, that is, the thickness of formed sacrifice layer is controlled, so as to be gone according to specific process requirements
Except the sacrifice layer of required thickness；Moreover, the angle that ion can be injected by adjusting controls the depth of the modified ion of injection
Degree, i.e., the bottom of the follow-up required sacrifice layer removed can be controlled to the distance at the top of opening 203.
In other embodiments, the modified ion species injected can be adjusted, and only need to meet subsequently to be formed
Sacrifice layer and Seed Layer 204 between there is Etch selectivity.
Fig. 9 is refer to, after the ion implantation technology, thermal anneal process is carried out, makes the part of injection modified ion
Seed Layer 204 forms sacrifice layer 205, and the material of the sacrifice layer 205 is different from the material of Seed Layer 204.
The thermal anneal process is：Temperature is 150 degrees Celsius~300 degrees Celsius, and the time is 1 minute~10 minutes；It is described
Thermal anneal process makes the material of injection modified ion and the ion formation sacrifice layer 205 in Seed Layer 204；Moreover, the heat is moved back
Ignition technique can make the more smooth fine and close, Stability Analysis of Structures of the Seed Layer 204, advantageously form the second best in quality conductive plunger.
In the present embodiment, the material of the Seed Layer 204 is copper, and the modified ion is oxonium ion, then the sacrifice layer 205 formed
Material be cupric oxide.
Because the cupric oxide can react with acidulous material, therefore faintly acid liquid can be used to the sacrifice layer
205 perform etching；Meanwhile the seed using copper as material will not react with acidulous material, therefore in etching sacrificial layer 205,
The Seed Layer 204 of unimplanted modified ion will not be damaged.Therefore, subsequently sacrifice layer 205 can be removed by etching, makes opening
203 width dimensions close to top become big, and during so as to suppress to be subsequently formed conductive film, what the top of opening 203 closed first asks
Topic, avoids producing space in the conductive plunger formed.
Figure 10 is refer to, removes the sacrifice layer 205（As shown in Figure 9）.
The technique for removing sacrifice layer is wet-etching technology.In the present embodiment, because the material of Seed Layer 204 is
Copper, the material of sacrifice layer 205 is cupric oxide, and the silica can be with weakly acidic acetic acid（CH3COOH）Reaction, and the vinegar
Acid will not damage copper；Specifically, the course of reaction of the acetic acid and cupric oxide is：CuO+2CH3COOH→Cu2++2CH3COO-+
H2O；Therefore, the etching liquid of the etching technics is acetic acid, after sacrifice layer 205 is removed, will not damage remaining Seed Layer
204.After sacrifice layer 205 is removed, as shown in Figure 8, projection of the Seed Layer 204 close to the sidewall surfaces at the top of opening 203
Part is removed.
In the present embodiment, remove sacrifice layer 205 and expose barrier layer 210, i.e., close to the top sidewall surface of opening 203
Seed Layer be removed completely, subsequently using electroplating technology growth conductive film 206 when, when the superficial growth copper of Seed Layer 204
During material, the barrier layer surface being exposed close to the top sidewall of opening 203 will not grow copper product simultaneously, and copper product is being filled
, just can be to the grown on top of opening 203 after the full opening 203 covered by Seed Layer 204, therefore avoid opening 203 and close too early
The problem of conjunction, tight, electric conductivity are good in the conductive plunger subsequently formed.
Figure 11 is refer to, after the sacrifice layer 205 is removed, in the opening 203（As shown in Figure 10）Interior seed
204 surface of layer form the conductive film 206 of the full opening 203 of filling.
The material of the conductive film 206 is copper, and the formation process of the conductive film 206 is copper electroplating technology（ECP,
electro-coppering plating）Or chemical plating process.In the copper electroplating technology, conductive material is from Seed Layer 204
Surface starts to grow, until the grown on top of the backward opening 203 of filling full gate mouth 203, until the conductive film 206 formed
Higher than the top of opening 203；In the present embodiment, due to the materials conductive on barrier layer 210, therefore to the surface institute of mask layer 202
The barrier layer exposed applies voltage, to implement copper electroplating technology；Moreover, the time of the copper electroplating technology determines to be formed
Conductive film 206 thickness, therefore can accurately control the conductive film 206 filling full by controlling the process time
Opening 203.
In the present embodiment, by injecting modified ion to the Seed Layer close to the top sidewall surface of opening 203, and pass through
Thermal anneal process makes the part of Seed Layer injection modified ion form sacrifice layer, makes sacrifice layer and 204 unimplanted modification of Seed Layer
The part of ion has Etch selectivity, can remove sacrifice layer by etching technics and retain the seed of unimplanted modified ion
Layer 204, that is, eliminate bossing of the Seed Layer 204 close to the top sidewall surface of opening 203；So as in the copper electroplating technology
In, the opening 203 will not close too early, ensure that the conductive film can be sufficient filling with completely described opening, so that after
Continuous formed conductive layer is fine and close and tight, the electric conductivity of the conductive plunger formed are good.
Figure 12 is refer to, the conductive film 206 higher than the surface of dielectric layer 201, resistance are removed using CMP process
Barrier 210 and mask layer 202（As shown in figure 11）, in opening 203（As shown in Figure 10）Interior formation conductive plunger 207.
It is described due to mask layer 202 and Seed Layer and the material of conductive film 206 in the CMP process
It difference, can be used in defining the stop position of glossing, after the mask layer 202 is polished to, carried out polishing with sudden and violent
Expose the surface of dielectric layer 201.In the present embodiment, after glossing, remaining conductive film 206 and kind in opening 201
Sublayer 204 forms conductive plunger.By fine and close tight in the conductive film 206 that is formed, the matter of the conductive plunger formed
Amount and electric conductivity are good, are advantageous to device stability raising.
In the present embodiment, the seed using copper as material is formed in the side wall and lower surface of mask layer surface and opening
After layer, oxonium ion is injected to the Seed Layer close to open top side wall；After thermal anneal process, Seed Layer injection it is modified from
The part of son forms the sacrifice layer that cupric oxide is material；Because cupric oxide and copper have an Etch selectivity, the cupric oxide is easy
With acetic acid reaction, and acetic acid will not damage copper；Therefore cupric oxide sacrifice layer is removed with acetic acid, and Seed Layer is not damaged；
So as to which Seed Layer is removed close to the bossing of open top sidewall surfaces, and conduction is formed using copper electroplating technology follow-up
During film, the top of open wound will not first close, and avoid and space is formed in conductive film.Therefore, glossing it
Afterwards, fine and close tight in the conductive plunger that the Seed Layer and conductive film polished by process is formed, its electric conductivity are good.
In summary, after the side wall and lower surface of opening form Seed Layer, using ion implantation technology to close
The Some seeds layer injection modified ion of the sidewall surfaces of open top, after follow-up thermal annealing, injects modified ion
Some seeds layer forms sacrifice layer；Because cambial material is different from the Seed Layer for not being injected into modified ion therefore described
Sacrifice layer has higher selection with Seed Layer in etching technics, and the sacrifice layer can either be removed by etching technics, and
Retain the Seed Layer for not being injected into modified ion；It is because the modified ion is injected in the Seed Layer of open top, i.e., sacrificial
Domestic animal layer is located at the sidewall surfaces close to open top, after removing sacrifice layer, the width dimensions of open top can be made to become big, so as to
Can suppress during being subsequently formed conductive layer, open top close too early and in conductive layer interstitial problem.Institute
It is fine and close in the conductive layer of formation, its electric conductivity can be ensured, make formed performance of semiconductor device more stable.
Further, the material of the Seed Layer is copper, and the modified ion is oxonium ion, that is, the material of the sacrifice layer formed
Expect for cupric oxide；Because cupric oxide is basic anhydride, easily with acidulous material react neutralize, and metallic copper will not and weak acid
Property substance reaction, therefore use acetic acid as etching liquid and can remove sacrifice layer of the cupric oxide for material, while will not be right
The remaining Seed Layer using copper as material causes to damage；While open top width dimensions are increased, remaining seed ensure that
The pattern of layer surface is good, is advantageous to be subsequently formed the measured conductive layer of matter.
Further, the modified ion injected tilts relative to dielectric layer surface, and angle of inclination is 0 degree~30 degree, is led to
The angle for controlling the ion implantation technology is crossed, the bottom of ion implanted regions can be controlled to the distance of dielectric layer surface, i.e.,
It is controllable to the distance of dielectric layer surface, the size of sacrifice layer to control the sacrifice layer bottom that is subsequently formed；Secondly, noted by controlling
The depth of injection ion can be controlled by entering energy, so as to the thickness for the sacrifice layer that controling power is subsequently formed；Therefore, required removal
Sacrifice layer size and thickness it is controllable, advantageously form the measured conductive layer of matter.
Although present disclosure is as above, the present invention is not limited to this.Any those skilled in the art, this is not being departed from
In the spirit and scope of invention, it can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
The scope of restriction is defined.
Claims (18)
- A kind of 1. forming method of conductive structure, it is characterised in that including：Substrate is provided, the substrate surface has dielectric layer, has opening in the dielectric layer；Seed Layer is formed in the side wall and lower surface of the opening；Modified ion is injected to the Some seeds layer of the sidewall surfaces close to open top using ion implantation technology；After the ion implantation technology, thermal anneal process is carried out, the Some seeds layer of injection modified ion is formed and sacrifices Layer, the material of the sacrifice layer is different from the material of Seed Layer, and the thermal anneal process is：Temperature is taken the photograph for 150 degrees Celsius~300 Family name's degree, time are 1 minute~10 minutes；Remove the sacrifice layer；After the sacrifice layer is removed, the conductive layer of the full opening of filling is formed in the opening.
- 2. the forming method of conductive structure as claimed in claim 1, it is characterised in that the material of the Seed Layer is copper, institute The material for stating conductive layer is copper.
- 3. the forming method of conductive structure as claimed in claim 2, it is characterised in that the formation process of the conductive layer is： The conductive film of filling full gate mouth is formed in the seed layer surface using electroplating technology or chemical plating process；Using chemical machinery Glossing removes the conductive film higher than dielectric layer surface, and exposes dielectric layer surface.
- 4. the forming method of conductive structure as claimed in claim 2, it is characterised in that the modified ion is oxonium ion, institute It is cupric oxide to state sacrifice layer.
- 5. the forming method of conductive structure as claimed in claim 4, it is characterised in that the technique for removing sacrifice layer is wet Method etching technics, etching liquid are acetic acid.
- 6. the forming method of conductive structure as claimed in claim 1, it is characterised in that the ion implantation technology is：Injection Angle is 0 degree~30 degree, and injection metering is 1*105~1*107Atom/square centimeter, Implantation Energy are 50KeV~150KeV.
- 7. the forming method of conductive structure as claimed in claim 6, it is characterised in that in the ion implantation technology process In, the substrate is rotated horizontally, the angle of the horizontal rotation is 0 degree or 180 degree.
- 8. the forming method of conductive structure as claimed in claim 1, it is characterised in that the forming method of the opening is： Dielectric layer surface forms mask layer, and the mask layer exposes certain media layer surface；Using the mask layer as mask, using each Anisotropy dry etch process etches the dielectric layer to form opening.
- 9. the forming method of conductive structure as claimed in claim 8, it is characterised in that the mask layer include silicon oxide layer, And the metal nitride layer positioned at silicon oxide layer surface, the material of the metal nitride layer include titanium nitride or tantalum nitride.
- 10. the forming method of conductive structure as claimed in claim 8, it is characterised in that the Seed Layer is also formed into described The top of mask layer and sidewall surfaces, the modified ion are also injected at the top of mask layer and in the Seed Layer of sidewall surfaces.
- 11. the forming method of conductive structure as claimed in claim 8, it is characterised in that also include：Formed and stopped in substrate surface Only layer, dielectric layer are formed at the stopping layer surface, and the material of the stop-layer is different from dielectric layer, the etch media layer Technique stops at the stopping layer surface, and after the technique of the etch media layer, removes the stop-layer of open bottom.
- 12. the forming method of conductive structure as claimed in claim 1, it is characterised in that the formation process of the Seed Layer is Atom layer deposition process or physical gas-phase deposition.
- 13. the forming method of conductive structure as claimed in claim 1, it is characterised in that also include：Forming the Seed Layer Before, barrier layer is formed in the side wall and lower surface of dielectric layer surface and opening, the material on the barrier layer is titanium nitride Or tantalum nitride；Seed Layer is formed in the barrier layer surface.
- 14. the forming method of conductive structure as claimed in claim 1, it is characterised in that the substrate includes：Semiconductor serves as a contrast Bottom；It is formed at the device of the semiconductor substrate surface；It is formed at semiconductor substrate surface and is electrically isolated the insulation of the device Layer.
- 15. the forming method of conductive structure as claimed in claim 1, it is characterised in that the substrate is Semiconductor substrate.
- 16. the forming method of conductive structure as claimed in claim 1, it is characterised in that the material of the dielectric layer is low K materials Material or ultra low-K material.
- 17. the forming method of conductive structure as claimed in claim 1, it is characterised in that the depth-to-width ratio of the opening is more than 5: 1。
- 18. the forming method of conductive structure as claimed in claim 1, it is characterised in that also include：Using chemically mechanical polishing Technique removes the conductive layer higher than dielectric layer surface, and untill dielectric layer surface is exposed, conductive plunger is formed in opening.
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| CN107369645B (en) * | 2016-05-13 | 2020-05-08 | 中芯国际集成电路制造(上海)有限公司 | Method for forming semiconductor structure |
| US9881867B1 (en) * | 2017-01-19 | 2018-01-30 | Nanya Technology Corporation | Conductive connection structure having stress buffer layer |
| CN108735797B (en) * | 2017-04-25 | 2022-05-13 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| WO2019023945A1 (en) * | 2017-08-01 | 2019-02-07 | 深圳华大基因研究院 | Fluidic channel structure device and manufacturing method therefor |
| CN110021560A (en) * | 2018-01-10 | 2019-07-16 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor devices and forming method thereof |
| CN111326290B (en) * | 2018-12-14 | 2021-12-10 | 海安科技株式会社 | Method for producing transparent conductive film |
| CN112530856A (en) * | 2019-09-18 | 2021-03-19 | 长鑫存储技术有限公司 | Semiconductor device, semiconductor structure and manufacturing method of interconnection structure |
| CN112736030A (en) * | 2019-10-29 | 2021-04-30 | 长鑫存储技术有限公司 | Semiconductor structure and preparation method thereof |
| CN113506771B (en) * | 2021-07-23 | 2022-12-09 | 长江存储科技有限责任公司 | Manufacturing method of semiconductor structure and semiconductor structure |
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