CN1041254C - 三维结构的半导体器件 - Google Patents

三维结构的半导体器件 Download PDF

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CN1041254C
CN1041254C CN94117079A CN94117079A CN1041254C CN 1041254 C CN1041254 C CN 1041254C CN 94117079 A CN94117079 A CN 94117079A CN 94117079 A CN94117079 A CN 94117079A CN 1041254 C CN1041254 C CN 1041254C
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semiconductor device
printed circuit
circuit board
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权宁信
安升皓
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Samsung Electronics Co Ltd
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Abstract

一种具有至少一个装在印制电路板下表面上的半导体芯片、丝焊到印制电路板端子上的半导体芯片电极端子、以及用密封树脂密封的半导体芯片和焊丝的连接部分的半导体器件，包括三维结构的半导体器件，它具有反向安装的印制电路板、经通孔连到外部端子的印制电路板端子以及至少一个层叠在印制电路板上表面的半导体器件，因而，当通过作为外部端子的引线把待安装的焊球加放入其它印制电路板中时使各个半导体器件互连。

Description

三维结构的半导体器件
本发明涉及一种球形网格阵列(此后称之为＂BGA＂)封装，特别是涉及提供一种通过在半导体衬底上部形成通孔而在半导体衬底下部形成焊球，以便用于高密度组装存储器组件的三维结构的半导体器件。
日本专利申请平2-37761公开了一种混合集成电路器件，包括：无源元件和有源元件，安装在线路板上，外部引线端粘接在线路板上，它们通过薄金属线相互连接；形成电路；和用模制树脂密封该组件。线路板的一面经模制树脂暴露，用于外部连接的电极(突点)形成在该暴露的表面上。一通孔或类似孔用于连接该突点和无源元件或有源元件。
考虑到电子设备的高性能化与多功能化将随着不断趋于小型化与减薄尺寸而提高，就要求各种半导体器件组装方法能在有限的内部空间之中有效地组装大容量存储器件。
作为解决上述问题的一种方法，莫托罗拉公司的＂Over MoldedPad Array Carrier(OMPAC)＂封装方法(已公开在ASIC&EDA，第9-15页，1993年3月号中)可以作为一个例子。
图1是表示一种常规半导体器件实施例的垂直剖面图。
参照图1，该半导体器件包括有由预定间隔隔开的通孔15的辅衬底11，以及在辅衬底11的一定区域形成的导电接触焊盘13。另外，借助于绝缘粘合剂将半导体芯片12固定在辅衬底11上，以金属丝14把半导体芯片12的压焊盘电连接到导电接触焊盘13上，再用环氧树脂模塑混合物(此后称之为＂EMC＂)灌注金属丝14和半导体芯片12，形成封装体10。在辅衬底11的通孔15下部有焊料块电极，亦即焊球16，而多个电极焊盘18则对应于焊块电极16而配置在主衬底17上。
将半导体芯片12安装在辅衬底11上，用诸如金(Au)丝14完成电连接之后，借助于EMC进行传递模塑，而焊球16则固定在具有通孔15的辅衬底11下的相应通孔15上，从而经回流焊获得具有焊块电极16的半导体器件，它被称之为BGA封装。
将上述结构的BGA封装安装在主衬底17上，并使由焊球16构成的焊块电极通过回流焊电连接到在主衬底17上表面形成的电极焊盘18上，于是就完成了半导体器件的组装。
这样的BGA封装与同样脚针数的方形平面封装(QFP)相比较，在主衬底上的安装面积大约节省30％，然而迄今的BGA封装都脱离不了二维结构平面安装的范畴，其中所有的在主衬底与封装之间的连接点都位于同一平面上。
此外，在BGA封装之中，用以保护半导体芯片12免受周围环境影响的树脂密封部分只形成于封装体10与辅衬底的界面的一侧。也就是说，在辅衬底11下形成的焊球16被通过回流焊而固定到结构脆弱的主衬底17的电极焊盘18上，于是会暴露于外界环境之中，因此，这种BGA封装在内部和外部环境特性方面要比常用的那些封装差，从而会使其性能降低。
本发明在于解决上述问题。因而，本发明的目的在于提供一种三维结构的半导体器件，使器件的整个外形完全符合小型输出线J-引线(SOJ)封装的标准，而又能改进可靠性。
本发明的另一个目的在于：利用可被层叠在SOJ封装内部的BGA封装，通过采取实现层间互连的三维安装结构，从而提供可改进组装效率的半导体器件。
为了实现本发明的上述目的，本发明提供了一种三维结构的半导体器件，其中包括：至少一个装在印制电路板下表面上的半导体芯片、金属丝焊到所述印制电路板的端子上的所述半导体芯片电极端子、和处在所述半导体芯片和金属焊丝之间并被密封树脂所密封的连接部分，其特征在于，
所述印制电路板被反向安装，
所述印制电路板的所述端子经过通孔连接到外部端子，以及
在所述印制电路板的上表面层叠有至少一个半导体器件，从而通过加放入焊球使各个半导体器件互连，以便通过作为所述外部端子的引线将其安装在其它印制电路板上。
通过详细地描述各优选的实施例并参照附图，本发明的上述目的和其他优点将变得更加清楚，其中
图1是表示一个常规半导体器件实施例的垂直剖面图；
图2是表示一个按照本发明的半导体器件实施例的垂直剖面图；
图3是表示在主衬底上形成的岛状图形、通孔的及电极连接端子的图2局部平面剖视图；
图4是表示另一个按照本发明的半导体器件实施例的垂直剖面图；
图5是表示在主衬底上形成岛状图形、通孔及电极连接端子的图4局部平面剖视图；
图6是图4一个区域的局部放大剖视图；
图7是表示将依据本发明的半导体器件组装到半导体衬底上部的平面图；
图8是表示将依据本发明的半导体器件组装到半导体衬底下部的平面图；
图9是表示另一个依据本发明的半导体器件实施例的垂直剖面图。
参照图2，下面将详细地描述依据本发明的半导体器件(SOJ封装)的优选实施例。
在图2中，包括通孔(未示出)和电极连接端子23的多个岛状图形(未示出)形成于主衬底21下表面的两端上。多个球形网格阵列25形成于主衬底21的上表面的两端上，而多个焊球26则形成于主衬底21的球形网格阵列25之上。
在加放入粘合剂29的同时，半导体芯片22被固定在主衬底21的下表面中部，再将半导体芯片22的压焊盘(未示出)用金属丝24焊接到电极连接端子23上，并且用EMC模塑成封装件20。
这里，电极连接端子23将通孔与岛状图形电连接，再电连接到金属丝24。
参照作为图2局部剖面图的图3可以更清楚地理解上述结构。
参照图3，由电极连接端子23共同电连接沿主衬底21的长度方向一起形成的岛状图形27和通孔28，而后沿长度方向在电极连接端子23的末端设置封装体20。
图4是表示另一个依本发明半导体器件的实施例垂直剖面图。
参照图4，该半导体器件至少有一个通过加放入粘合剂39而固定在印制电路板(此后称为＂PCB＂)31的下表面上的半导体芯片32，半导体芯片32的压焊盘(未示出)和PCB 31的电极连接端子33则采用金属丝34来焊接。该半导体芯片32的连接部与金属丝34都采用树脂密封，从而形成封装体30。
如上形成的上述半导体器件在其最后的安装工艺过程中，将PCB 31上边朝下颠倒安装，而PCB 31的各端子则经各通孔连接到各个外部端子。此外，该PCB 31的上表面上至少层叠一个半导体器件。然后，各个半导体器件都通过加放入焊球36而连接起来，而且借助于作为外部端子的引线38固定到其他PCB上，结果，所说的半导体器件就具有一种三维结构。
当从反方向来观察时，如图6所示，处在PCB 31上表面的半导体芯片32的块状焊盘部、用来将半导体芯片32连接到封装端子的金属丝压焊焊盘部、以及由焊球36构成的焊块焊盘部都采用铜箔为基底并镀以镍(Ni)和金(Au)(其厚度各为5μm和0.5μm)，从而改善器件的金属丝焊接可靠性。
参照作为图4局部剖面图的图5就能更清楚地理解上述结构。
参照图5，沿PCB 31的长度方向形成岛状图形47与通孔48，且由电极连接端子33将其共同电连接起来。经过通孔48连接作为外部端子的引线38，而封装体30就设置在沿长度方向上的电极连接端子33的末端。该引线38(即PCB 31的外部端子)镀以铜或其合金。
同时，参照作为图4区域A局部放大剖面图的图6，安装着焊球36的球形网格阵列35即是通过在PCB 31上顺序镀以铜层42、镍层43和金层44之后而得到的金属镀层，而盘形焊球安置部分37就制作在该金属镀层的上部。
该PCB31由热稳定材料，诸如双马来酰亚胺三嗪(BT)树脂和热稳定环氧树脂形成。其镀镍的表面再覆以厚0.5μm的金(Au)。
图7和8是分别说明在形成岛状图形之前，应用于本发明半导体器件的半导体衬底的上、下部的平面图。
参照图7，盘形端部55设置在一个PCB 51的上部，以允许借助焊球而安装另一个PCB。
参照图8，与盘形端部55一一对应地形成环形通孔52，其中，PCB 51中部虚线区53指示出模塑区。
因此，由焊球连接的PCB 51的上/下表面借助于通孔或通过孔变为导电的，而且PCB 51下表面的层间连接端子(未示出)也被连接到通孔。此外，除在后继工艺中将借助焊球来连接的那些部分之外，导电部分和通孔部分都分别覆盖以阻焊层。
上述的SOJ封装可以按下列工艺来制造，其制造工艺将参照图4至8加以说明。
如图7和8所示，在主衬底51上表面和下表面两端的中部形成通孔52后，其中下表面中的通孔52形成环状，从而允许将作为外部连接引线的引线连接到该通孔52，而连到通孔52的上表面被设置成盘形。
该岛状部包括通孔，当按层叠式组装BGA封装时，通过除掉岛状部的中部的导电材料而形成环状以便对准，然而岛状部的反面则呈盘状，以防止在固定焊球后进行回流焊时熔化了的焊料流向岛状部的反面。
然后，如图6所示，依次镀铜(Cu)、镍(Ni)和金(Au)，即以通孔52为中心，在其周围通过电镀工艺形成金属镀层。
此后，如图4所示，通过图形形成工艺，在主衬底31的上、下面形成围绕金属镀层的预定图形结构，提供岛状图形、电极连接端子和球形网格阵列，并且涂覆阻焊层。再通过加放入粘合剂39，使半导体芯片32固定在主衬底31的中部，再使用金属丝34将其焊接到电极连接端子33上，从而形成封装体30。
这时，借助为固定半导体芯片32用的块状焊盘部之上的导电粘合剂39使该半导体芯片32附着在主衬底31的中部，并再使其在约150℃的温度下硬化。随后，在约170℃温度下在加热器台座上将半导体芯片32的焊盘以细金丝连接到主衬底31的引线38上。
当完成细金属丝的连接后，采用EMC材料进行模塑并进行焊球安装，其中，经过焊球的层间连接是通过岛状图形来完成的。
于是，通过把预定形状的焊球36固定到具有通孔的球形网格阵列35上就完成了BGA封装的制造。
图9是表示另一个依据本发明的半导体器件的实施例剖面图，它描述了用三维结构的BGA封装组装成SOJ封装的一个优选实施例。
可是，这种BGA封装的缺点在于：由于PCB上下表面之间的岛状图形结构不同，如图5所示，因此是经由通孔来连接主衬底两侧的各个端子。此外，通过在模塑后使主衬底的下表面转向朝上，从而焊剂涂满岛状部并将焊球固定到岛状部上。然后，施行回流焊以形成各凸块，各相应的封装被分割成单个产品而提供使用。
就半导体器件来说，参照图9，在加放入粘合剂的同时，把半导体芯片安装到含有通孔、电极连接端子与岛状图形的主衬底61中部表面，且金属丝焊到电极连接端子，以便按反方向进行由EMC模塑的主封装体60的安装。
此后，在加放入粘合剂的同时，把第一半导体芯片安装到处在上述岛状图形上的包含有第一通孔、第一电极连接端子与第一岛状图形的第一衬底71下表面中部，并且金属丝焊到第一电极连接端子上，以便以第一焊球76为媒介体，按相反方向安装由EMC模塑的第一封装体70。
随后，在加放入粘合剂的同时，把第二半导体芯片安装到处在上述第一岛状图形上的包含有外部引线88、第二通孔、第二电极连接端子与第二岛状图形的第二衬底81下表面中部，并且金属丝焊到第二电极连接端子上，以便用第二焊球86为媒介体，按相反方向安装由EMC模塑的第二封装体80。
在加放入粘合剂的同时，把第三半导体芯片安装到盖在第三岛状图形上的包含有第三通孔、第三电极连接端子与第三岛状图形的第三衬底91下表面中部，并且金属丝焊到第三电极连接端上，以便用第三焊球96为媒介体，按相反方向安装由EMC模塑的第三封装体90。
最终，完成了三维结构的半导体器件。
对于如上构成的三维结构半导体器件而言，它所具有的引线88(即外部端子)被弯曲成如＂J形引线＂或＂鸥翼＂的形状，以便在主衬底(未示出)上进行表面安装。
三维结构高密度组装封装的外形就是SOJ封装，就其内部而言，使BGA封装层叠起来以便实行层间连接。
另外，将带引线的衬底和不带引线的衬底分别组装以便允许已模塑好的上表面面朝上，并将要与焊块连接的各岛状部涂覆以焊剂。以带引线的衬底为中心层叠各衬底，通过回流焊以便获得层间连接，此时，在被应用于存储器件的情况下，按这样的方式来设计信号线路以便执行其制造工艺，即：使公共端子共同连接在一起，而借助各单独的信号端子去连接单独构成的各端子。
所以，在经过回流焊之后，以带引线的衬底为中心用密封树脂来模塑该存储器件，使其在温度约175℃下大致经5小时的硬化，再经切割和弯曲加工，使之具有安装所要求的合适引线形状，于是完成全部工艺过程。
本发明根据如上所述的半导体器件及其制造方法可有益地应用于能实现三维表面安装的SOJ封装，这是常规二维平面安装的BGA封装所达不到的。
而且，本发明完全与通用的、安装到主衬底上的安装工艺过程兼容，还改善了半导体器件的可靠性。
此外，因为利用能层叠在SOJ封装内的BGA封装来实行层间连接的三维安装结构，改进了制造半导体器件时的安装效率，使得降低制造成本和能够实施大规模生产。
通过利用能层叠在SOJ封装内的BGA封装的三维安装结构，实现了本发明提供的半导体器件，本领域的技术人员都应理解，对其所作的形式上和细节上的各种改变都不会偏离本发明的构思范围和如所附权利要求书限定的范围。

Claims (8)

1.一种三维结构半导体器件，包括：至少一个装在印制电路板下表面上的半导体芯片、金属丝焊到所述印制电路板的端子上的所述半导体芯片电极端子、和处在所述半导体芯片和金属焊丝之间并被密封树脂所密封的连接部分，其特征在于，
所述印制电路板被反向安装，
所述印制电路板的所述端子经过通孔连接到外部端子，以及
在所述印制电路板的上表面层叠有至少一个半导体器件，从而通过加放入焊球使各个半导体器件互连，以便通过作为所述外部端子的引线将其安装在其它印制电路板上。
2.按照权利要求1的三维结构半导体器件，其特征在于，其中，所述印制电路板是由热稳定衬底，诸如双马来酰亚胺三嗪(BT)树脂和热稳定环氧树脂形成，且镀金(Au)至厚度大约0.5μm。
3.按照权利要求1的三维结构半导体器件，其特征在于，其中，采用所述焊球作为媒介体而进行连接的所述印制电路板的端部，是被构制成环形或盘形。
4.按照权利要求1的三维结构半导体器件，其特征在于，其中，通过采用所述焊球互连的所述印制电路板的上、下表面是与所述通孔之间导通的或通过孔而导通的。
5.按照权利要求1的三维结构半导体器件，其特征在于，其中，所述印制电路板下表面的层间连接端子是连接到所述通孔的，并且除用所述焊球连接的部分外，导电部分和通孔部分都涂覆以阻焊层。
6.按照权利要求1的三维结构半导体器件，其特征在于，其中，作为印制电路板外部端子的所述引线镀以铜(Cu)或其合金。
7.按照权利要求1的三维结构半导体器件，其特征在于：
所述半导体芯片是通过将粘合剂加放到包括通孔、电极连接端子和岛状图形的主衬底的下表面中部、金属丝焊到所述电极连接端子上、以及模塑以环氧树脂模塑混合物以便反向安装主封装体，从而组装成的；还包括：
第一半导体芯片，通过将粘合剂加放到位处于所述岛状图形之上的包含有第一通孔、第一电极连接端子和第一岛状图形的第一衬底下表面的中部，金属丝焊到所述第一电极连接端子上，以及模塑以环氧树脂模塑混合物以便利用第一焊球作为媒介体反向安装第一封装体，从而组装成；
第二半导体芯片，通过将粘合剂加放到位处于所述第一岛状图形之上的包含有外部引线、第二通孔、第二电极连接端子和第二岛状图形的第二衬底下表面中部，金属丝焊到所述第二电极连接端子上，以及模塑以环氧树脂模塑混合物以便利用第二焊球作为媒介体反向安装第二封装体，从而组装成；
第三半导体芯片，通过将粘合剂加放到位处于所述第二岛状图形之上的包含有第三通孔、第三电极连接端子和第三岛状图形的第三衬底下表面中部，金属丝焊到所述第三电极连接端子，以及模塑以环氧树脂模塑混合物以便利用第三焊球作为媒介体反向安装第三封装体，从而组装成。
8.按照权利要求7的三维结构半导体器件，其特征在于，其中，作为外部端子的所述外部引线被弯曲成＂J＂或＂鸥翼＂形。
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