CN104135269A - High-speed clock signal transmission system and method - Google Patents

Abstract

The invention relates to a high-speed clock signal transmission system and method. The high-speed clock signal transmission system comprises a clock driving circuit (1), a clock transmission cable (2), a clock receiving circuit (3) and an N-end matching circuit (4), wherein the clock driving circuit (1) is an LVPECL (Low Voltage Positive Emitter-Coupled Logic) circuit; the P output end of the clock driving circuit (1) is taken as a normal clock output end, and is connected with the clock receiving circuit (3) through the clock transmission cable (2); the N output end of the clock driving circuit (1) is connected with the N-end matching circuit (4); and direct current coupling or alternating current coupling is adopted at the output of the LVPECL circuit. Through the design of the N-end matching circuit, single-end output of the LVPECL circuit can be realized. Only the P output end is connected with the receiving circuit through a coaxial cable, so that the problem of the need of using a special radiofrequency differential cable in the LVPECL circuit in the prior art is solved. Clock transmission can be realized by using an ordinary coaxial cable, so that the cost is greatly reduced. Moreover, the high-speed clock signal transmission system is simple in circuit structure, and is easy to implement.

Description

A kind of high-speed clock signal transmission system and method

Technical field

The present invention relates to clock signal transmission field, relate in particular to a kind of high-speed clock signal transmission system and method.

Background technology

Signals collecting and playback are the important component parts of radar, sonar and electronic warfare system, and clock is the benchmark of signals collecting and playback.The clock of frequency stabilization, low jitter can make signals collecting obtain high s/n ratio, signal playback obtains higher Spurious Free Dynamic Range.

In traditional clock generating and distribution system, mainly use a series of analog elements such as power splitter, frequency mixer, filter, amplifier, by analog sine level form, realize.In high-frequency clock system, use analogue device to carry out clock generating and need to use of a great variety, bulky device to realize with distribution.Amplitude coincidence and phase equalization are along with the increase of clock frequency, gradually step-down simultaneously.Along with increasing of clock frequency, the shortcoming of using traditional analog device to carry out clock generating and distribution method very flexible displays gradually.

In order to improve above-mentioned shortcoming, proposed at present to carry out with digital level form the mode of high-frequency clock transmission.It is representative that digital level form be take LVPECL (Low Voltage Positive Emitter-Coupled Logic), LVDS (Low Voltage Differential Signals), these 3 kinds of level forms of CML (Current Mode Logic).Wherein LVPECL is a kind of Digital Logical Circuits of unsaturation type, in circuit, transistor is operated in linear zone or cut-off region, speed is not subject to the restriction of the memory time of minority carrier, is that existing various digital circuit medium velocity is a kind of faster, can meet the requirement up to 10GHz operating rate.In distributed system, LVPECL is a kind of differential level form, can not use traditional coaxial cable to transmit, need to use special-purpose radio-frequency differential cable to transmit, and special-purpose radio-frequency differential cable exists the shortcoming of making difficulty, involving great expense, be not suitable for using in the product of producing in enormous quantities.

Summary of the invention

Technical problem to be solved by this invention is to provide a kind of high-speed clock signal transmission system and method, solving traditional sinusoidal simulated clock simulation clock produces and distributes and need realize by of a great variety, the bulky device of use, and difference LVPECL level transmissions clock must be used the problem of special-purpose radio-frequency difference cable, the present invention can be widely used in clock generating, distribution platform, forms high-frequency clock transmission system.

The invention discloses a kind of high-frequency clock transmission system and method based on single-ended LVPECL circuit, it produces circuit based on LVPECL level, by the design of P output, N output match circuit, system interconnect design, realizes single-ended LVPECL level in the application of high-frequency clock transmission system.

The technical scheme that the present invention solves the problems of the technologies described above is as follows: a kind of high-speed clock signal transmission system, comprises clock driver circuit, clock transfer cable, clock receiving circuit and N end match circuit;

Described clock driver circuit adopts LVPECL circuit, and its P output, as normal output terminal of clock, is connected with clock receiving circuit by clock transfer cable; Its N output is connected with N end match circuit;

When LVPECL circuit adopts AC coupled, the P output of described LVPECL circuit is connected with clock transfer cable by capacitance C10, between described P output and capacitance C10, is connected biasing resistor R10 over the ground; Described match circuit comprises capacitance C20, resistance R 20 and biasing resistor R30 over the ground, and the N output of described LVPECL circuit is by capacitance C20, resistance R 20 ground connection, between described N output and capacitance C20, is connected biasing resistor R30 over the ground;

Described receiving circuit comprises resistance R 40, and described clock transfer cable is by resistance R 40 ground connection.

The invention has the beneficial effects as follows: clock driver circuit of the present invention adopts LVPECL circuit, avoided traditional analog sine wave transmissions to realize complicated, amplitude coincidence and phase equalization are difficult to ensure the shortcoming of card, it is very suitable for high-frequency clock output system, and utilize the P output of LVPECL to carry out clock transfer, N output carries out matched termination, realize the application of single-ended LVPECL, single-ended LVPECL form can be transmitted by common coaxial cable, without custom fabricated difficulty, the special-purpose radio-frequency difference cable that involves great expense.

On the basis of technique scheme, the present invention can also do following improvement.

Further, described clock transfer cable 2 adopts coaxial cable, and its characteristic impedance is 50 Ω.

Further, the resistance of described resistance R 10 and R30 is Rt, and the resistance of described resistance R 20 and R40 is 50 Ω, and wherein the computing formula of Rt is as follows:

$\mathrm{Rt}=\frac{\mathrm{Vcco}-1.3V}{14\mathrm{mA}}$

Wherein, the voltage that Vcco provides for LVPECL circuit, its value is 2.5V or 3.3V.

Further, described capacitor C 10 and C20 are 0.1uF.

Another technical scheme that the present invention solves the problems of the technologies described above is as follows: a kind of high-speed clock signal transmission system, comprises clock driver circuit, clock transfer cable, clock receiving circuit and N end match circuit;

Described clock driver circuit adopts LVPECL circuit, and its P output, as normal output terminal of clock, is connected with clock receiving circuit by clock transfer cable; Its N output is connected with N end match circuit;

When LVPECL circuit adopts direct-current coupling, described match circuit comprises resistance R 50 and cut-off level, and the N output of described LVPECL circuit is connected to cut-off level Vtt by resistance R 50;

Described receiving circuit comprises resistance R 60, and described clock transfer cable is received cut-off level Vtt by resistance R 60.

Further, described clock transfer cable adopts coaxial cable, and its resistance is 50 Ω.

Further, the resistance of described resistance R 50 and R60 is 50 Ω.

Further, described cut-off level Vtt=Vcco-2V, wherein, the voltage that Vcco provides for LVPECL circuit.

Another technical scheme that the present invention solves the problems of the technologies described above is as follows: a kind of high-speed clock signal transmission method, comprises the steps:

Step 1: clock signal input LVPECL circuit;

Step 2: clock signal is from the P output output of LVPECL circuit, by direct-current coupling or be ac-coupled to clock transfer cable, by clock transfer cable transmission to clock receiving circuit; The N output of LVPECL circuit is held match circuit by direct-current coupling or AC coupled to N.

On the basis of technique scheme, the present invention can also do following improvement.

Further, when LVPECL circuit adopts AC coupled, clock signal is passed through biasing resistor R10 ground connection over the ground from the P output of LVPECL circuit, by capacitance C10, transfers to clock transfer cable, resistance R 40 by clock transfer cable transmission to receiving circuit, resistance R 40 ground connection; Biasing resistor R30 ground connection is over the ground passed through in the N end output of LVPECL circuit, by capacitance C20 and resistance R 20 ground connection;

When LVPECL circuit adopts direct-current coupling, clock signal transfers to clock transfer cable from the P output of LVPECL circuit, the resistance R 60 by clock transfer cable transmission to receiving circuit, and resistance R 60 is received cut-off level Vtt; The N output of LVPECL circuit is connected to cut-off level Vtt by resistance R 50.

Accompanying drawing explanation

Fig. 1 is the high-frequency clock transmission system figure that the present invention is based on the single-ended LVPECL output circuit of direct-current coupling;

Fig. 2 is the N end of Fig. 1 circuit and the circuit diagram that receiving circuit adopts Dai Weinan to replace;

Fig. 3 is the high-frequency clock transmission system figure that the present invention is based on the single-ended LVPECL output circuit of AC coupled;

Fig. 4 is LVPECL circuit diagram of the present invention.

In accompanying drawing, the list of parts of each label representative is as follows:

1, clock driver circuit, 2, clock transfer cable, 3, clock receiving circuit, 4, N holds match circuit.

Embodiment

Below in conjunction with accompanying drawing, principle of the present invention and feature are described, example, only for explaining the present invention, is not intended to limit scope of the present invention.

As shown in Figure 1, 2, a kind of high-speed clock signal transmission system, comprises clock driver circuit 1, clock transfer cable 2, clock receiving circuit 3 and N end match circuit 4; Described clock driver circuit 1 adopts LVPECL circuit, and its P output, as normal output terminal of clock, is connected with clock receiving circuit 3 by clock transfer cable 2; Its N output is connected with N end match circuit 4.

Single-ended LVPECL level clock output is divided into AC coupled and two kinds of working methods of direct-current coupling.Output adopts AC coupled or direct-current coupling, to the form of laod network, will propose different demands.As shown in Figure 3, LVPECL output interface is the emitter of emitter follower, at chip internal, does not connect load, at output, must connect suitable load resistance, otherwise has abnormal output signal.

Fig. 1 is the high-frequency clock transmission system based on the single-ended LVPECL output circuit of direct-current coupling, comprises clock driver circuit 1, clock transfer cable 2, clock receiving circuit 3 and N end match circuit 4; Described clock driver circuit 1 adopts LVPECL circuit, and its P output, as normal output terminal of clock, is connected with clock receiving circuit 3 by clock transfer cable 2; Its N output is connected with N end match circuit 4; When LVPECL circuit adopts direct-current coupling, described match circuit comprises resistance R 50 and cut-off level, and the N output of described LVPECL circuit is connected to cut-off level Vtt by resistance R 50; Described receiving circuit 4 comprises resistance R 60, and described clock transfer cable 2 is received cut-off level Vtt by resistance R 60.

Described clock transfer cable adopts coaxial cable, and its characteristic impedance is 50 Ω; The resistance of described resistance R 50 and R60 is 50 Ω; Described cut-off level Vtt=Vcco-2V, wherein, the voltage that Vcco provides for LVPECL circuit.

P output in LVPECL output circuit is as normal output terminal of clock, and N end is received on cut-off level by 50 Ω resistance R 50 ends, so that the emitter resistance of emitter follower to be provided, circuit is normally worked.While adopting direct-current coupling mode to transmit single-ended LVPECL clock, receiving terminal need to design special circuit.By the build-out resistor R60 of 50 Ω, for receiving terminal provides corresponding cut-off level, can realize high performance clock and receive.In actual applications, can use and wear the dimension south and connect mode providing of cut-off level is provided, as shown in Figure 2.

As Fig. 2, to wear the P end that the dimension south connects mode LVPECL drive circuit and remain unchanged, N end is received cut-off level by 50 Ω resistance terminal and is changed into and on N end resistance R pu, move Vcco, resistance R pd to and pull down to ground, and meets:

$\mathrm{Rpd}=Z_0\left(\frac{\mathrm{Vcco}}{\mathrm{Vcco}-\mathrm{Vtt}}\right)---\left(1\right)$

$\mathrm{Rpu}=\mathrm{Rpd}\left(\frac{\mathrm{Vcco}-\mathrm{Vtt}}{\mathrm{Vtt}}\right)---\left(2\right)$

Z wherein ₀for transmission line impedance, Vcco is LVPECL circuit supply voltage, Vtt=Vcco-2V.

In receiving circuit, can use equally and wear the dimension south and connect mode and substitute 50 Ω resistance terminal and receive cut-off level mode.

In transmission line impedance, be under 50 Ω conditions, LVPECL circuit N end build-out resistor or receiving terminal build-out resistor are as mistake! Do not find Reference source.Shown in.

Table 1

?	Vcco＝5V	Vcco＝3.3V	Vcco＝2.5V
				Rpu(Ω)	83	127	250
Rpd(Ω)	125	83	62.5

While adopting the single-ended LVPECL level transmissions of direct-current coupling, receiving circuit has the shortcoming of very flexible.For great majority, do not need in the clock system of DC component, can use the single-ended LVPECL level form transfer clock of AC coupled.

A high-speed clock signal transmission method, comprises the steps:

Step 1: clock signal input LVPECL circuit;

Step 2: clock signal is from the P output output of LVPECL circuit, by direct-current coupling or be ac-coupled to clock transfer cable, by clock transfer cable transmission to clock receiving circuit; The N output of LVPECL circuit is held match circuit by direct-current coupling or AC coupled to N.

When LVPECL circuit adopts AC coupled, clock signal is passed through biasing resistor R10 ground connection over the ground from the P output of LVPECL circuit, by capacitance C10, transfer to clock transfer cable, the resistance R 40 by clock transfer cable transmission to receiving circuit, resistance R 40 ground connection; Biasing resistor R30 ground connection is over the ground passed through in the N end output of LVPECL circuit, by capacitance C20 and resistance R 20 ground connection;

When LVPECL circuit adopts direct-current coupling, clock signal transfers to clock transfer cable from the P output of LVPECL circuit, the resistance R 60 by clock transfer cable transmission to receiving circuit, and resistance R 60 is received cut-off level Vtt; The N output of LVPECL circuit is connected to cut-off level Vtt by resistance R 50.

Fig. 3 is the high-frequency clock transmission system based on the single-ended LVPECL output circuit of AC coupled, comprises clock driver circuit 1, clock transfer cable 2, clock receiving circuit 3 and N end match circuit (4); Described clock driver circuit 1 adopts LVPECL circuit, and its P output, as normal output terminal of clock, is connected with clock receiving circuit 3 by clock transfer cable 2; Its N output is connected with N end match circuit 4; When LVPECL circuit adopts AC coupled, the P output of described LVPECL circuit is connected with clock transfer cable 2 by capacitance C10, between described P output and capacitance C10, is connected biasing resistor R10 over the ground; Described match circuit 4 comprises capacitance C20, resistance R 20 and biasing resistor R30 over the ground, and the N output of described LVPECL circuit is by capacitance C20, resistance R 20 ground connection, between described N output and capacitance C20, is connected biasing resistor R30 over the ground; Described receiving circuit 3 comprises resistance R 40, and described clock transfer cable 2 is by resistance R 40 ground connection.

For the P output of LVPECL, in circuit, the emitter of emitter follower needs load resistance, designs biasing resistor R10 over the ground before capacitance C10, so that emitter DC path to be over the ground provided.At receiving terminal, because DC component is isolated by capacitor C 10, therefore adopt 50 traditional Ω load receiving circuits can complete the reception of high-frequency clock.Output for LVPECL N, is not used in actual applications, needs suitable direct current and AC terminal.As shown in Figure 2, before the N output capacitance C20 of LVPECL, design a biasing resistor R30 over the ground, so that emitter DC path to be over the ground provided.After capacitance C20, design 50 Ω terminal resistance R20, to absorb the alternating current component of N output transmission, prevent that it from reflecting to affect P end clock performance.

Described clock transfer cable 2 adopts coaxial cable, and its characteristic impedance is 50 Ω; The resistance of described resistance R 10 and R30 is Rt, and the resistance of described resistance R 20 and R40 is 50 Ω; Described capacitor C 10 and C20 are 0.1uF.

While using AC coupled to drive the terminate load of 50 Ω, consider to add a direct current biasing resistor at the emitter follower of LVPECL output.The output common mode voltage of LVPECL need be fixed on Vcco-1.3V, only needs this resistance can provide 14mA to arrive the path on ground when selecting direct current biasing resistance.Therefore resistance R 10 and R30 need meet:

R10＝R30＝Rt， $\mathrm{Rt}=\frac{\mathrm{Vcco}-1.3V}{14\mathrm{mA}}---\left(3\right)$

Can realize the single-ended LVPECL level clock transfer of AC coupled.

Below the each several part of the high-frequency clock transmission system based on single-ended LVPECL of the present invention is introduced as follows.

1, clock driver circuit

Fig. 4 is LVPECL circuit, and LVPECL, by ECL standard evolution, has saved negative supply in LVPECL circuit, compared with ECL circuit, is more convenient for using.

1, Q1, Q2 are emitter follower output circuits, and its effect is: a. level shift, matches the common mode electrical level of output and the input common mode electrical level (Vcc-1.3V) of next stage circuit; B. as output, driving is buffer stage, provides electric current to amplify and low output impedance.

2, transistor Q3, Q4, Q5 form differential amplifier, and differential amplifier can only be operated in linear amplification region and cut-off region, just can obtain the performance of two-forty.Wherein Q5 forms constant-current source, and it has very large AC equivalent resistance, much larger than collector electrode R10, R7, therefore has very strong direct current negative feedback, plays " emitter-coupled " effect simultaneously.

3, Q6, Q7 and diode D1, D2 form the bias supply (reference source) with temperature-compensating, and it makes differential amplifier be operated in reliably linear amplification region.

The relative ECL of the amplitude of oscillation of LVPECL signal is little, and this makes this logic be more suitable for transmitting in high-frequency clock.In traditional LVPECL level, its transmission form will adopt differential mode, by differential mode voltage value decision level.This transmission means can suppress common mode disturbances, reduces and externally crosstalks and reduce the degree that is subject to external interference.But the shortcoming of differential transfer clearly in distributed system, maximum shortcoming is that it can not use traditional coaxial cable to transmit, and the shortcoming that special-purpose radio-frequency differential cable has the difficulty of making, involves great expense, be not suitable for using in a large amount of batches of products that produce, and this kind of cable is unfavorable for that the test of all purpose instrument and long line transmit.

By Fig. 4, can find, when transistor is worked in real work, not enter saturation condition, only be operated in linear zone and cut-off region, there is no the memory phenomenon of minority carrier.In this operating state, shorten dramatically switching time, collector junction capacitance reduces greatly, RC time constant is corresponding reducing also, the propagation delay time of circuit is very short, the logic level amplitude of oscillation is little, in dynamic translation process, each change in voltage of tying is very short to the time that discharges and recharges of junction capacitance, so LVPECL level is suitable for high-frequency clock output system.Simultaneously output stage difference channel two arm alternations, power supply total current substantially constant, current spike, voltage swing are very little, can realize the output of low noise clock.Do not change above-mentioned LVPECL output state, the N output of LVPECL level is done to suitable coupling, realize single-ended LVPECL clock output.In the inventive method, adopt P output in LVPECL to carry out clock transfer, N output carries out matched termination, realizes the application of single-ended LVPECL.

2, clock transfer cable

Coaxial cable has two concentric conductors, and conductor and screen share the cable in same axle center.Single-ended LVPECL level application method, is used 50 traditional Ω coaxial cables can realize the transmission of high-frequency clock between drive circuit and receiving circuit, solved the problem that must use the radio-frequency differential cable of customization in difference LVPECL transmission.

3, clock receiving circuit

Single-ended LVPECL adopts AC coupled or direct-current coupling, to the form of clock receiving circuit, will propose different demands.For the single-ended LVPECL level of direct-current coupling, receiving terminal designs as shown in Figure 1.For remote situation about transmitting, receiving terminal provides the load of coupling on cut-off level by 50 Ω resistance R 60.With this understanding, when the emitter follower for output interface provides load resistance, also reduced the power consumption of output circuit.The matched load that designs 50 Ω mates with characteristic impedance to guarantee the termination impedance of transmission line, prevents signal reflex.In actual applications, can use and wear the dimension south and connect mode providing of cut-off level is provided.At receiving terminal, the Vcco, the resistance R pd that on use resistance R pu, draw pull down to ground.Resistance value can be calculated according to formula (1), (2).Receiving terminal circuit need guarantee to support Vcco-1.3V common mode electrical level form simultaneously.

For the single-ended LVPECL level of AC coupled, receiving terminal designs as shown in Figure 2.At receiving terminal, because DC component is by Capacitor apart, its actual electrical characteristic is consistent with the sinusoidal wave clock level of simulation, adopts 50 traditional Ω load receiving circuits can complete the reception of high-frequency clock.

So far, the single-ended LVPECL level application system building in high-frequency clock system is complete.Under this application process, can realize the low-jitter clock transmission of maximum clock frequency 2.4GHz.

The foregoing is only preferred embodiment of the present invention, in order to limit the present invention, within the spirit and principles in the present invention not all, any modification of doing, be equal to replacement, improvement etc., within all should being included in protection scope of the present invention.

Claims (10)

1. a high-speed clock signal transmission system, is characterized in that, comprises clock driver circuit (1), clock transfer cable (2), clock receiving circuit (3) and N end match circuit (4);

Described clock driver circuit (1) adopts LVPECL circuit, and its P output, as normal output terminal of clock, is connected with clock receiving circuit (3) by clock transfer cable (2); Its N output is connected with N end match circuit (4);

When LVPECL circuit adopts AC coupled, the P output of described LVPECL circuit is connected with clock transfer cable (2) by capacitance C10, between described P output and capacitance C10, is connected biasing resistor R10 over the ground; Described match circuit (4) comprises capacitance C20, resistance R 20 and biasing resistor R30 over the ground, the N output of described LVPECL circuit is by capacitance C20, resistance R 20 ground connection, between described N output and capacitance C20, is connected biasing resistor R30 over the ground;

Described receiving circuit (3) comprises resistance R 40, and described clock transfer cable (2) is by resistance R 40 ground connection.

2. a kind of high-speed clock signal transmission system according to claim 1, is characterized in that, described clock transfer cable (2) adopts coaxial cable, and its characteristic impedance is 50 Ω.

3. a kind of high-speed clock signal transmission system according to claim 1, is characterized in that, the resistance of described resistance R 10 and R30 is Rt, and the resistance of described resistance R 20 and R40 is 50 Ω, and wherein the computing formula of Rt is as follows:

$\mathrm{Rt}=\frac{\mathrm{Vcco}-1.3V}{14\mathrm{mA}}$

Wherein, the voltage that Vcco provides for LVPECL circuit, its value is 2.5V or 3.3V.

4. a kind of high-speed clock signal transmission system according to claim 1, is characterized in that, described capacitor C 10 and C20 are 0.1uF.

5. a high-speed clock signal transmission system, is characterized in that, comprises clock driver circuit (1), clock transfer cable (2), clock receiving circuit (3) and N end match circuit (4);

Described clock driver circuit (1) adopts LVPECL circuit, and its P output, as normal output terminal of clock, is connected with clock receiving circuit (3) by clock transfer cable (2); Its N output is connected with N end match circuit (4);

When LVPECL circuit adopts direct-current coupling, described match circuit (4) comprises resistance R 50 and cut-off level, and the N output of described LVPECL circuit is connected to cut-off level Vtt by resistance R 50;

Described receiving circuit (3) comprises resistance R 60, and described clock transfer cable (2) is received cut-off level Vtt by resistance R 60.

6. a kind of high-speed clock signal transmission system according to claim 5, is characterized in that, described clock transfer cable (2) adopts coaxial cable, and its characteristic impedance is 50 Ω.

7. a kind of high-speed clock signal transmission system according to claim 5, is characterized in that, the resistance of described resistance R 50 and R60 is 50 Ω.

8. a kind of high-speed clock signal transmission system according to claim 5, is characterized in that, described cut-off level Vtt=Vcco-2V, wherein, the voltage that Vcco provides for LVPECL circuit.

9. a high-speed clock signal transmission method, is characterized in that, comprises the steps:

Step 1: clock signal input LVPECL circuit;

Step 2: clock signal is from the P output output of LVPECL circuit, by direct-current coupling or be ac-coupled to clock transfer cable, by clock transfer cable transmission to clock receiving circuit; The N output of LVPECL circuit is held match circuit by direct-current coupling or AC coupled to N.

10. a kind of high-speed clock signal transmission method according to claim 9, is characterized in that,

When LVPECL circuit adopts AC coupled, clock signal is passed through biasing resistor R10 ground connection over the ground from the P output of LVPECL circuit, by capacitance C10, transfer to clock transfer cable, the resistance R 40 by clock transfer cable transmission to receiving circuit, resistance R 40 ground connection; Biasing resistor R30 ground connection is over the ground passed through in the N end output of LVPECL circuit, by capacitance C20 and resistance R 20 ground connection;

When LVPECL circuit adopts direct-current coupling, clock signal transfers to clock transfer cable from the P output of LVPECL circuit, the resistance R 60 by clock transfer cable transmission to receiving circuit, and resistance R 60 is received cut-off level Vtt; The N output of LVPECL circuit is connected to cut-off level Vtt by resistance R 50.