CN104143544B - A kind of wafer through-silicon via structure and preparation method thereof - Google Patents
A kind of wafer through-silicon via structure and preparation method thereof Download PDFInfo
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- CN104143544B CN104143544B CN201410232738.0A CN201410232738A CN104143544B CN 104143544 B CN104143544 B CN 104143544B CN 201410232738 A CN201410232738 A CN 201410232738A CN 104143544 B CN104143544 B CN 104143544B
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Abstract
The invention belongs to microelectronics technology, disclose a kind of wafer through-silicon via structure, described wafer through-silicon via structure includes: the cavity that through hole, front passivation layer, through hole passivation layer, backside passivation layer and through hole passivation layer are peripheral；Described through hole is opened on the silicon substrate of described wafer；On described through hole medial wall, through hole passivation layer is set；Described front passivation layer and described backside passivation layer are arranged on described silicon substrate front and back；Described front passivation layer and described backside passivation layer are connected with described through hole passivation layer respectively；In described silicon substrate, described through hole passivation layer periphery arranges cavity.The present invention is empty chamber by the through hole peripheral hardware on wafer silicon substrate, reduces the thermal stress effects caused greatly due to via metal and silicon materials thermal expansion coefficient difference；The most significantly weaken the electric field density around through hole, thus reduce the high-frequency loss of through hole.
Description
Technical field
The present invention relates to microelectronics technology, particularly to a kind of wafer through-silicon via structure and preparation thereof
Method.
Background technology
Along with electronic product small size, multi-functional, low-power consumption, high performance demand are strengthened by consumption market,
Planar integrated circuit faces huge challenge, and the characteristic size of CMOS gradually approaches physics limit." super mole ",
2.5 peacekeeping 3-dimensional integrated technologies based on silicon through hole (Throuth-silicon-Via TSV) are expected to become promotion
The new power of electronics integrated technology development.The structure design of silicon through hole, preparation technology, physical parameter are extracted
Study hotspot is all become with aspects such as modelings.
Owing to silicon is semi-conducting material, energy gap only 1.12eV, even if intrinsic silicon the most also has one
Fixed electric conductivity, and in actual use, can be the most also silicon material by mixing alms giver or acceptor impurity
Material presents more preferable electric conductivity.The resistivity of silicon chip more typically is zero point several ohm to tens ohm.Institute
With, different, in the structure of silicon through hole from the conductive through hole (such as pcb board and LTCC plate) in dielectric-slab
In, also having the insulating barrier of one layer of electrification buffer action between silicon materials and conductive through hole filler metal, this is exhausted
Edge layer material is typically silicon dioxide, and thickness is in hundreds of nanometer to micron；This insulating layer material can also
Selecting organic polymer material, thickness can be to tens microns；Silicon and conductive through hole filler metal are (typically
Copper) between thermal expansion coefficient difference relatively big, cause having around silicon through hole bigger stress；Silicon is as one half
Conductor material, electromagnetic field existing dielectric polorization in silicon materials is lost, has again conduction loss, at sinusoidal electricity
Under magnetic field conditions, for low-resistance silicon materials, conduction loss is very serious, causes on low-resistance silicon materials
Silicon through hole high speed signal is had bigger Insertion Loss, affect its frequency applications.
Chip clock and I/O speed break through GHz, and the raising that keeps, and the high frequency performance of silicon through hole becomes
For restricting one of factor of its application.The openest and report solution has employing High Resistivity Si and thickens
Insulating barrier.High Resistivity Si is expensive, is only applicable to the silicon keyset of 2.5D simultaneously, is not suitable for 3D's
The silicon through hole of active chip.The thickness of silicon dioxide insulating layer increases limited space, for thermal oxide dioxy
SiClx, thickness more than after 1 micron, oxidation rate the most slowly, the silicon dioxide of PECVD growth,
Thickness increase can cause stress and be full of cracks problem.
Owing to the difference of thermal expansion coefficients of copper and silicon is relatively big, produced thermal stress can cause around silicon through hole
Strain on silicon materials, even causes delamination and the cracking of surrounding silicon materials at silicon through hole interface.
Summary of the invention
The technical problem to be solved is to provide one can reduce silicon through hole high-frequency loss, heat
The through-silicon via structure of stress effect.
For solving above-mentioned technical problem, the invention provides a kind of wafer through-silicon via structure, described wafer
Through-silicon via structure includes: through hole, front passivation layer, through hole passivation layer, backside passivation layer and through hole
The cavity that passivation layer is peripheral；Described through hole is opened on the silicon substrate of described wafer；Inside described through hole
Through hole passivation layer is set on wall；Described front passivation layer and described backside passivation layer are arranged on described silicon lining
End front and back；Described front passivation layer and described backside passivation layer are passivated with described through hole respectively
Layer linking；In described silicon substrate, described through hole passivation layer periphery arranges cavity.
Further, described cavity top is with front passivation layer as cutoff layer, and described cavity bottom is with the back of the body
Face passivation layer is cutoff layer.
Further, described backside passivation layer offers through hole；Described through hole connects described cavity.
Further, described through hole is multiple independent holes, is looped around the through hole week of described silicon substrate
Enclose.
Further, described through hole is that annulus hole shape structure ring is wound on around the through hole of described silicon substrate.
Further, described through hole is the through hole week that semicircle annular distance shape structure ring is wound on described silicon substrate
Enclose.
Further, the cavity wall thickness range of described cavity is 1um～100um；Leading to of described silicon substrate
Hole pore diameter range is 1um～100um；Hole depth 20um of described through hole～300um.
Further, described cavity is formed by etching the peripheral silicon substrate material of described through hole passivation layer；
Including: it is fully etched the peripheral silicon substrate material of described through hole passivation layer and is formed entirely around described silicon logical
The cavity in hole or part etch the peripheral silicon substrate material forming part of described through hole passivation layer around institute
State the cavity of silicon through hole.
Further, described front passivation layer, described through hole passivation layer, described backside passivation layer are by one
Layer or multilayer material are constituted.
The preparation method of a kind of wafer silicon through hole, comprises the following steps:
The wafer rear painting with the processing of wafer rear micro convex point is connected up again being complete wafer rear metal
Photoresist, makes opening figure on a photoresist by lithography；
The backside passivation layer of wafer etches the figure of opening；
By the opening in backside passivation layer, use anisotropic etch process, formed in silicon substrate
Deep trouth；
Use isotropic etching technique, in silicon substrate, form cavity by deep trouth.
The wafer through-silicon via structure that the present invention provides is by formation cavity structure around silicon through hole, greatly
Weaken greatly the electric field density around through hole, thus reduce high-frequency loss；Simultaneously because greatly reduce
Silicon through hole effectively contact with silicon substrate so that due to hot swollen between the filling perforation metal of through hole and silicon substrate
The inconsistent thermal stress effects caused of swollen coefficient is greatly lowered, and then reduces stress, it is to avoid silicon through hole
The delamination at interface and the cracking of surrounding silicon materials.
Accompanying drawing explanation
The profile of the silicon through hole being released on the silicon keyset that Fig. 1 provides for the embodiment of the present invention one；
The profile of the silicon through hole being released on the body silicon that Fig. 2 provides for the embodiment of the present invention two；
The profile of the silicon through hole being released on the soi chip that Fig. 3 provides for the embodiment of the present invention three；
Silicon through hole release is optionally carried out on the silicon keyset that Fig. 4 provides for the embodiment of the present invention four
Profile；
The back of the body of the through hole that Fig. 5 (a), Fig. 5 (b), Fig. 6 (a) and Fig. 6 (b) provide for the embodiment of the present invention
Face top view；
The preparation technology stream of the silicon through hole release that Fig. 7 (a) to Fig. 7 (g) provides for the embodiment of the present invention
Journey schematic diagram；
The profile that the sets of wafers of Fig. 8: band release silicon through hole is contained on substrate；
Wherein, 1-silicon substrate, 201-front passivation layer, 202-through hole passivation layer, 203-backside passivation layer；
3-wafer frontside metal wiring layer again, 401-wafer frontside micro convex point, 402-wafer rear micro convex point, 501-
Through hole, 6-cavity, 7-opening, 8-active area, insulating barrier on 9-SOI sheet, 10-SOI sheet pushes up silicon layer,
11-substrate, the top-level metallic of 12-substrate 11,13-underfill, 14-slide glass, 15-photoresist.
Detailed description of the invention
The wafer mentioned in the present embodiment refer to the silicon wafer used by silicon semiconductor production of integrated circuits and
The various components that manufacture on silicon wafer and become the IC device that there is certain electric sexual function.At silicon
In the case of keyset, silicon substrate 1 and the passive element such as single chip integrated electric capacity, inductance, resistance on it
May make up wafer；Particularly, when silicon substrate 1 does not has integrated any components and parts, simple silicon substrate 1,
In this patent, it is possible to be considered as a wafer.In the case of active chip, silicon substrate 1 and monolithic collection on it
The active area 8 become constitutes wafer；When using SOI (Silicon-on-Isolator) sheet, on SOI sheet
Active area 8 structure on insulating barrier 9, top silicon layer 10 and top silicon layer 10 on silicon substrate 1, SOI sheet
Become wafer.
Embodiment one
As shown in Figure 1, wafer through-silicon via structure includes: through hole 501, front passivation layer 201, through hole
The cavity 6 that passivation layer 202, backside passivation layer 203 and through hole passivation layer are peripheral；Through hole 501 is opened in
On the silicon substrate 1 of wafer；Through hole 501 arranges through hole passivation layer 202 on medial wall；Front passivation layer 201
With the front and back that backside passivation layer 203 is arranged on silicon substrate 1；Front passivation layer 201 and the back side
Passivation layer 203 is connected with through hole passivation layer 202 respectively, by silicon substrate 1 and extraneous wiring layer isolation；?
Silicon substrate 1 is internal, and through hole passivation layer 202 periphery arranges cavity 6, thus by certain for the periphery of through hole 501
In the range of silicon substrate material hollow out, formed cavity structure；On the one hand greatly reduce in through hole 501
Filler metal and the contact area of silicon substrate material, thus significantly reduce the thermal coefficient of expansion due to both
The inconsistent thermal stress effects caused, it is to avoid the delamination at silicon through hole interface or the problem of silicon substrate cracking；
On the other hand, owing to the electric field density near through hole is very big, thus high-frequency loss is relatively big, peripheral cavity knot
Structure can greatly weaken electric field density near silicon through hole, is substantially reduced high-frequency loss.
Silicon substrate 1 is conventional silicon wafers, and silicon substrate 1 can be that n-type doping, p-type doping or intrinsic are mixed
Miscellaneous；The preferred monocrystal silicon of silicon substrate 1；Can also be polysilicon or non-crystalline silicon.Silicon substrate 1 in the present embodiment
Front and back have the passivation layer 201 of wafer frontside and the passivation layer 203 of wafer rear respectively；Cavity 6
Top with front passivation layer 201 as cutoff layer, the bottom of cavity 6 with backside passivation layer 203 for cut-off
Layer.There are wafer frontside metal wiring layer 3 again above face passivation layer 201, below backside passivation layer 203, have crystalline substance
Circle back metal wiring layer again, wafer frontside metal wiring layer 3 again and wafer rear metal wiring layer again are all
It can be multilamellar.
For simplicity's sake, the wafer rear metal wiring layer again in accompanying drawing 1 has only drawn one layer, i.e. accompanying drawing 1
In wafer rear metal wiring layer again in metal line 303.Wafer frontside metal wiring layer 3 again is by crystalline substance
Metal line 301 in circle front metal wiring layer again and the insulating barrier in wafer frontside metal wiring layer again
302 compositions；Silicon substrate 1 surface passivation is played at the front passivation layer 201 of silicon substrate 1 and the back side 203, with
And silicon substrate 1 and the metal line 301 in wafer frontside metal wiring layer again and wafer rear metal cloth again
The effect of metal line 303 electric isolution in line layer.
The through hole 501 through-silicon substrate 1 of silicon substrate 1 realizes the metal in wafer frontside metal wiring layer again
Conducting, on silicon through-hole wall of metal line 303 in wiring 301 and wafer rear metal wiring layer again
Through hole passivation layer 202 be positioned on the hole wall of silicon through hole 501, through hole passivation layer 202 is at through hole 501
Preparation technology flow process in complete, in the preparation technology flow process of through hole 501, through hole passivation layer 202
Play the hole wall of passivation silicon through hole 501, and the landfill metal of silicon through hole 501 electrically insulates with silicon substrate 1
Effect.
Front passivation layer 201, through hole passivation layer 202 and backside passivation layer 203 can be one or more layers
Inorganic material is constituted, and such as silicon dioxide, silicon nitride, silicon oxynitride, but is not limited to this；Can also be
One or more layers organic material is constituted, and such as polyimides PI, BCB, but is not limited to this.Front is passivated
Layer 201 and through hole passivation layer 202 can be formed at same processing step, it is also possible in different process step
Being formed, backside passivation layer 203 is formed in wafer rear passivation technology step.
In metal line 301 in wafer frontside metal wiring layer again and wafer rear metal wiring layer again
The material of metal line 303 is typically copper, and the insulating barrier 302 in wafer frontside metal wiring layer again is permissible
It is that inorganic material is constituted, such as silicon dioxide, silicon nitride, silicon oxynitride, and other low-k
Material, but it is not limited to this；Can also be that organic material is constituted, such as polyimides PI, BCB, but not
It is limited to this.
Wafer frontside micro convex point 401 metal line 301 in wafer frontside metal wiring layer again with put
Electrical connection between chip thereon or substrate or support plate, wafer rear micro convex point 402 is for wafer rear
Electrical connection between metal line 303 in metal wiring layer again and chip placed under or substrate or support plate；
Wafer frontside micro convex point 401 and wafer rear micro convex point 402 can be copper bumps, it is also possible to be that copper/stannum is convex
Point, it is also possible to be made up of other metal material, metal alloy, metal organic composite conductive material；Wafer
The size dimension of front micro convex point 401 and being smaller than or equal to wafer rear micro convex point 402.According to reality
Applicable cases, wafer frontside micro convex point 401 can not have.Wafer rear micro convex point under normal circumstances
402 is requisite.
The silicon through hole 501 of through-silicon material, generally, its preparation flow includes: the etching of silicon through hole；
The passivation of hole wall, is used for forming through hole passivation layer 202；Deposition plating seed layer；Through hole is filled in plating；Table
Face chemically mechanical polishing CMP.Fill the preferred copper of metal material of through hole, tungsten, but be not limited to this.Plating
Seed Layer preferred Ta/Cu, TiW/Cu, Ti/Cu, but it is not limited to this.
The aperture of silicon through hole 501 is generally at 1um to 100um, and the hole depth of silicon through hole 501 is generally at 20um
To 300um.Cavity 6 around silicon through hole 501 is formation during silicon through hole release process.Silicon leads to
The cavity wall thickness of the cavity 6 around hole is in 1um to 100um scope.Silicon through hole release process includes: get rid of
Glue, photoetching, the passivation layer of etching wafer rear, anisotropy dry etching silicon, isotropism dry etching silicon, go
Glue.If wafer rear metal wiring layer again is multilamellar, before the passivation layer of etching wafer rear, need
Etch away the insulating barrier in corresponding wafer rear metal wiring layer again and metal level.
Seeing Fig. 4, the cavity 6 cavity top around silicon through hole is with front passivation layer 201 as cutoff layer, empty
Bottom, chamber 6 is with backside passivation layer 203 as cutoff layer, and the through hole passivation layer 202 on silicon through-hole wall is cut-off
Layer；Can optionally carry out silicon through hole release, i.e. can the silicon through hole of only releasing bearing high speed signal,
And connecing power supply, ground connection, the silicon through hole of carrying direct current signal and low speed signal can not discharge；Silicon through hole 501
Upper carrying high speed signal, silicon through hole 502 and 503 can connect power supply, ground connection, carrying direct current signal and low
Speed signal, the frequency of usual described low speed signal is less than 100MHz.
See Fig. 5 (a), backside passivation layer 203 is offered through hole 7；Through hole 7 connects cavity 6
With free surrounding space.Through hole 7 is positioned at wafer rear, is formed during silicon through hole release process.
Cavity 6 around silicon through hole is connected with outside air by through hole 7.Cavity 6 around silicon through hole is
Unsealed, through hole 7 can be annular hole shape structure.
Seeing Fig. 5 (b), through hole 7 can also be that semicircle annular distance shape structure ring is wound on described silicon substrate
Around through hole.The back side micro convex point 402 of discharged silicon through hole not in the underface of discharged silicon through hole time,
One section of metal line is needed to connect discharged silicon through hole and corresponding back side micro convex point 402,
Seeing Fig. 6 (a) and Fig. 6 (b), through hole can be multiple independent holes, is looped around described silicon
Around the through hole of substrate.
Cavity 6 can be entirely around silicon through hole 501, it is also possible to partially surround silicon through hole 501.
Embodiment two
Seeing Fig. 2, the present embodiment, on the basis of embodiment one, increases active area 8, is positioned at silicon substrate 1
Upper strata, active area 8 includes: the electronics such as cmos circuit, BiCMOS circuit or HBT circuit electricity
Road；Light path, opto-electronic device or the photoelectricity of photonic device composition that photonic device forms can also be included
Road, but it is not limited to this.The silicon through hole 501 of through-silicon material runs through active area 8.Cavity around silicon through hole
6 run through active area 8, and now cavity 6 is with the through hole passivation layer 202 on silicon through-hole wall and silicon substrate 1 just
Face passivation layer 201 is cutoff layer；Cavity 6 can also be not through active area 8.Now need to control cavity 6
The degree of depth, to ensure that cavity 6 does not affect the performance of active area 8.Silicon through hole on body silicon equally may be used
Optionally to carry out silicon through hole release.
Embodiment three
Seeing Fig. 3, the present embodiment supplementary features on the basis of embodiment two are, silicon substrate 1, absolutely
Edge layer 9 and top silicon layer 10 constitute SOI (Silicon-on-Isolation) structure, and active area 8 is positioned at
On the silicon layer 10 of top, silicon through hole 501 through-silicon substrate 1, insulating barrier 9 and top silicon layer 10.Around silicon through hole
Cavity 6 through-silicon substrate 1, cavity 6 is with the top silicon on the passivation layer 202 and SOI sheet on silicon through-hole wall
Layer 10 is cutoff layer.Silicon through hole on SOI sheet the most optionally carries out silicon through hole release.
Embodiment four
The preparation method of wafer silicon through hole, comprises the following steps:
The wafer rear painting light with the processing of wafer rear micro convex point is connected up again being complete wafer rear metal
Photoresist, makes opening figure on a photoresist by lithography；
The backside passivation layer of wafer etches the figure of opening；
By the opening in backside passivation layer, use anisotropic etch process, formed deep in silicon substrate
Groove；
Use isotropic etching technique, in silicon substrate, form cavity by deep trouth.
See Fig. 7 (a), wafer frontside is complete wafer frontside metal and connects up micro-with wafer frontside again
Salient point, is complete silicon through hole, and wafer rear is complete wafer rear metal and connects up and wafer again
The wafer frontside of the wafer of back side micro convex point is bonded with slide glass 14.
See Fig. 7 (b), connect up again and the crystalline substance of wafer rear micro convex point being complete wafer rear metal
Circle back side resist coating 15.
See 7 (c), photoresist 15 makes by lithography the figure of opening 7, thus is backside passivation layer
203 offer through hole 7 prepares.
See Fig. 7 (d), wafer rear passivation layer 203 etches through hole 7, by silicon substrate 1
Exposed out；Lithographic method can be dry etching, can also be wet etching.
See Fig. 7 (e), with the through hole 7 on photoresist 15 and wafer rear passivation layer 203 as mask,
Use anisotropic etch process, etch silicon substrate 1 to certain depth, form deep trouth；Lithographic method is excellent
Select dry etching.
See Fig. 7 (f) and Fig. 7 (g), use isotropic etching technique, at the deep trouth base of silicon substrate
Cavity 6 is formed on plinth；Lithographic method can be dry etching, can also be wet etching, and cavity 6 is with silicon
Through hole passivation layer 202 and the front passivation layer 201 of silicon substrate 1 on through-hole wall are cutoff layer.
Wafer frontside is separated with slide glass 14, completes through-silicon via structure and prepare.
Seeing Fig. 8, the sets of wafers of band release silicon through hole is contained on substrate 11, the front gold of described wafer
Belong to again the metal line in wiring layer, wafer frontside micro convex point, silicon through hole and wafer rear metal again
The physical contact of the top-level metallic 12 being routed through wafer rear micro convex point and substrate 11 realizes electrical connection,
Electrical connection can be copper copper bonding, copper and tin bonding, but is not limited to this；Substrate 11 can be organic substrate,
Silicon substrate, ceramic substrate, glass substrate, it is also possible to be that wafer or chip, wafer or chip can band silicon
Through hole can also be without silicon through hole.The wafer of underfill 13 filling tape release silicon through hole and substrate 11
Between gap, underfill 13 by band release silicon through hole wafer on opening be full of around silicon through hole
Cavity, improve the reliability being released silicon through hole in actual applications；The filling of underfill 13
Method can be capillary fill, can also be vacuum aided fill but be not limited to this.
High speed low-stress silicon through-hole structure and preparation method disclosed in this patent are applicable to multiple different silicon and lead to
Hole preparation method and preparation flow, including first preparing silicon through hole (Via First), preparing silicon through hole (Via halfway
Middle) silicon through hole (Via Middle) and silicon keyset (Si Interposer) preparation side are prepared after,
Method and preparation flow, it is only necessary in former flow process, increase by one " release of silicon through hole " technique, do not affect in former flow process
Other techniques all and method；It is applicable to the size and dimension of different silicon through holes；It is applicable to different
Silicon through hole embedding material and burying method, including copper filling, tungsten filling, fill solder, conductive paste,
And hole wall metal and organic polymer mix filling, but it is not limited to this.
The wafer through-silicon via structure that the present invention provides is by formation cavity structure around silicon through hole, significantly
Weaken the electric field density around through hole, thus reduce high-frequency loss；Simultaneously because greatly reduce silicon
Through hole effectively contacts with silicon substrate so that due to thermal coefficient of expansion between the filling perforation metal of through hole and silicon substrate
The inconsistent thermal stress effects caused is greatly lowered, and then reduces stress, it is to avoid taking off of silicon through hole interface
Layer and the cracking of surrounding silicon materials.
It should be noted last that, above detailed description of the invention is only in order to illustrate technical scheme
And unrestricted, although the present invention being described in detail with reference to example, the ordinary skill people of this area
Member should be appreciated that and can modify technical scheme or equivalent, without deviating from
The spirit and scope of technical solution of the present invention, it all should be contained in the middle of scope of the presently claimed invention.
Claims (10)
1. a wafer through-silicon via structure, it is characterised in that described wafer through-silicon via structure includes: logical
The cavity that hole, front passivation layer, through hole passivation layer, backside passivation layer and through hole passivation layer are peripheral；
Described through hole is opened on the silicon substrate of described wafer；Described through hole passivation layer is through-hole wall；Described just
Face passivation layer and described backside passivation layer are arranged on described silicon substrate front and back；Described front is passivated
Layer and described backside passivation layer are connected with described through hole passivation layer respectively；In described silicon substrate, in institute
State through hole passivation layer periphery and cavity is set.
2. wafer through-silicon via structure as claimed in claim 1, it is characterised in that: described cavity top
With front passivation layer as cutoff layer, described cavity bottom is with backside passivation layer as cutoff layer.
3. wafer through-silicon via structure as claimed in claim 1, it is characterised in that: described passivating back
Through hole is offered on Ceng；Described through hole connects described cavity.
4. wafer through-silicon via structure as claimed in claim 3, it is characterised in that: described through hole is
Multiple independent holes, are looped around around the through hole of described silicon substrate.
5. wafer through-silicon via structure as claimed in claim 3, it is characterised in that: described through hole is
Annulus hole shape structure ring is wound on around the through hole of described silicon substrate.
6. wafer through-silicon via structure as claimed in claim 3, it is characterised in that: described through hole is
Semicircle annular distance shape structure ring is wound on around the through hole of described silicon substrate.
7. the wafer through-silicon via structure as described in any one of claim 1～6, it is characterised in that: institute
The cavity wall thickness range stating cavity is 1um～100um；The through-hole aperture scope of described silicon substrate is
1um～100um；Hole depth 20um of described through hole～300um.
8. wafer through-silicon via structure as claimed in claim 7, it is characterised in that: described cavity passes through
Etch the peripheral silicon substrate material of described through hole passivation layer to be formed；Including: it is fully etched described through hole blunt
Change the peripheral silicon substrate material of layer form the cavity entirely around described silicon through hole or partly etch described
The silicon substrate material forming part of through hole passivation layer periphery is around the cavity of described silicon through hole.
9. wafer through-silicon via structure as claimed in claim 7, it is characterised in that described front is passivated
Layer, described through hole passivation layer, described backside passivation layer are made up of one layer or multilayer material.
10. the preparation method of a wafer silicon through hole, it is characterised in that comprise the following steps:
The wafer rear painting with the processing of wafer rear micro convex point is connected up again being complete wafer rear metal
Photoresist, makes opening figure on a photoresist by lithography；
The backside passivation layer of wafer etches the figure of opening；
By the opening in backside passivation layer, use anisotropic etch process, formed in silicon substrate
Deep trouth；
Use isotropic etching technique, in silicon substrate, form cavity by deep trouth.
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| CN113035810B (en) * | 2021-03-04 | 2022-11-25 | 复旦大学 | Through silicon via structure, packaging structure and manufacturing method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5828101A (en) * | 1995-03-30 | 1998-10-27 | Kabushiki Kaisha Toshiba | Three-terminal semiconductor device and related semiconductor devices |
| CN202924718U (en) * | 2012-09-29 | 2013-05-08 | 姜利军 | Double-material micro-cantilever and electromagnetic radiation detector |
| CN103178023A (en) * | 2013-02-28 | 2013-06-26 | 格科微电子（上海）有限公司 | Mixed substrate encapsulation method and mixed substrate encapsulation structure for semiconductor device |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5828101A (en) * | 1995-03-30 | 1998-10-27 | Kabushiki Kaisha Toshiba | Three-terminal semiconductor device and related semiconductor devices |
| CN202924718U (en) * | 2012-09-29 | 2013-05-08 | 姜利军 | Double-material micro-cantilever and electromagnetic radiation detector |
| CN103178023A (en) * | 2013-02-28 | 2013-06-26 | 格科微电子（上海）有限公司 | Mixed substrate encapsulation method and mixed substrate encapsulation structure for semiconductor device |
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Effective date of registration: 20190430 Address after: 214135 China Sensor Network International Innovation Park D1, 200 Linghu Avenue, Wuxi New District, Jiangsu Province Patentee after: National Center for Advanced Packaging Co., Ltd. Address before: No. 3, North Tu Cheng West Road, Chaoyang District, Beijing Co-patentee before: National Center for Advanced Packaging Co., Ltd. Patentee before: Institute of Microelectronics, Chinese Academy of Sciences |