CN104143552A - Electron capturing storage unit - Google Patents
Electron capturing storage unit Download PDFInfo
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- CN104143552A CN104143552A CN201310164838.XA CN201310164838A CN104143552A CN 104143552 A CN104143552 A CN 104143552A CN 201310164838 A CN201310164838 A CN 201310164838A CN 104143552 A CN104143552 A CN 104143552A
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- raceway groove
- memory cell
- storage
- control gate
- electron capture
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Abstract
The invention discloses an electron capturing storage unit. The electron capturing storage unit comprises channels (26) and insulating layers (25) between every two adjacent channels, and further comprises channel control gates (27) located in the insulating layers (25), and the channel control gates are good conductors of electricity. The channel control gates are added, so that the two sides, near each channel control gate, of the corresponding physical channel, namely a first storage unit and a second storage unit are controlled to be opened and closed. In this way, an existing storage unit can store two digits of information, the storage density is higher, and the unit storage cost is lowered.
Description
Technical field
The present invention relates to memory cell field, relate in particular to a kind of electron capture memory cell.
Background technology
In electron capture (Charge Trap) memory technology, especially, in SONOS memory technology, can store two information with a physical memory cell, as follows.
Fig. 1 a is the structural representation of the electron capture memory cell of prior art; Fig. 1 b is the cutaway view along the A-A ' line of Fig. 1 a; Fig. 1 c is the cutaway view along the B-B ' line of Fig. 1 a; Fig. 1 d is the cutaway view along the C-C ' line of Fig. 1 b, and wherein, Fig. 1 d is the overall cutaway view of memory cell along C-C ' line.
As shown in Fig. 1 a to Fig. 1 d, prior art electron capture memory cell comprises the insulating barrier 15 between insulation dielectric 12, tunnel insulation dielectric 14, raceway groove 16 and adjacent two raceway grooves between control gate 11, memory cell 13, control gate 11 and memory cell 13.Can find out from Fig. 1 c and Fig. 1 d, prior art has a raceway groove 16, has two virtual memory cells 131 and 132 13 li of memory cell.
This memory technology is used hot electron injecting principle, because electronics cannot freely move freely in the material of memory cell 13, by converting the source electrode of memory cell and the position of drain electrode in process writing, the principle of injecting by hot electron, can respectively electronic selection be deposited in to a physical memory cell 13 and be divided into two virtual memory cells 131 and 132 that are arranged in control gate 11 both sides, each virtual memory cell can be used for storing an information, and such physical memory cell 13 just can be used for storing two information.
In order to increase storage density, reduce unit carrying cost, constantly reduce node, but along with constantly dwindling of node, also more and more difficult in technique, and by dwindling node, to reduce the method for unit storage unit cost more and more difficult, and physical memory cell of prior art can only be stored two information, storage density is not high enough, causes unit carrying cost higher.
Summary of the invention
Thus, the present invention proposes a kind of electron capture memory cell, can improve the storage density of electron capture memory cell.
The invention provides a kind of electron capture memory cell, comprise the insulating barrier (25) between raceway groove (26) and adjacent two described raceway grooves, also further comprise:
Raceway groove control gate (27), is arranged in described insulating barrier (25), and is electric good conductor.
Preferably, described raceway groove control gate (27) is positioned at the described first storage raceway groove (261) of described raceway groove (26) both sides and the opening and closing of described the second storage raceway groove (262) for controlling.
Preferably, the number of the described raceway groove control gate (27) in each described insulating barrier (25) is 1.
Preferably, a described raceway groove control gate (27), for control a side raceway groove described second storage raceway groove (262) opening and closing, and control opposite side raceway groove described first storage raceway groove (261) opening and closing.
Preferably, the number of the described raceway groove control gate (27) in each described insulating barrier (25) is 2.
Preferably, a described raceway groove control gate is used for the opening and closing of the described second storage raceway groove (262) of the raceway groove of controlling a side, and described in another, raceway groove control gate is used for the opening and closing of the described first storage raceway groove (261) of the raceway groove of controlling opposite side.
Preferably, described raceway groove control gate (27) is Cu, W, and Al, Ta metal, or be TiN
x, WN
x, CoSi
x, NiSi
x, TiSi
xcompound.
Preferably, the memory cell of described electron capture memory cell (23) is disconnection.
Preferably, the memory cell of described electron capture memory cell (23) is continuous.
Preferably, described electron capture memory cell is SONOS memory cell.
The present invention is by adding raceway groove control gate, control raceway groove in the physical significance both sides near raceway groove control gate, the first memory cell and the second memory cell open and close respectively, the virtual memory cell of such prior art can be stored two information, therefore, storage density uprises, and unit carrying cost reduces.
Brief description of the drawings
Fig. 1 a is the structural representation of the electron capture memory cell of prior art;
Fig. 1 b is the cutaway view along the A-A ' line of Fig. 1 a;
Fig. 1 c is the cutaway view along the B-B ' line of Fig. 1 a;
Fig. 1 d is the cutaway view along the C-C ' line of Fig. 1 b;
Fig. 2 a is the structural representation of the electron capture memory cell of first embodiment of the invention;
Fig. 2 b is the cutaway view along the A-A ' line of Fig. 2 a;
Fig. 2 c is the cutaway view along the B-B ' line of Fig. 2 a;
Fig. 2 d is the cutaway view along the C-C ' line of Fig. 2 b;
Fig. 3 is the structural representation of the electron capture memory cell of second embodiment of the invention;
Fig. 4 is the memory cell structure schematic diagram that electron capture of the present invention disconnects; And
Fig. 5 is the continuous memory cell structure schematic diagram of electron capture of the present invention.
Embodiment
Further illustrate technical scheme of the present invention below in conjunction with accompanying drawing and by embodiment.Be understandable that, specific embodiment described herein is only for explaining the present invention, but not limitation of the invention.It also should be noted that, for convenience of description, in accompanying drawing, only show part related to the present invention but not full content.
Fig. 2 a is the structural representation of the electron capture memory cell of first embodiment of the invention; Fig. 2 b is the cutaway view along the A-A ' line of Fig. 2 a; Fig. 2 c is the cutaway view along the B-B ' line of Fig. 2 a; Fig. 2 d is the cutaway view along the C-C ' line of Fig. 2 b, and wherein, Fig. 2 d is the overall cutaway view of memory cell along C-C ' line.
As shown in Fig. 2 a-Fig. 2 d, the invention provides a kind of electron capture memory cell, comprise the insulating barrier 25 between insulation dielectric 22, tunnel insulation dielectric 24, raceway groove 26 and adjacent two raceway grooves between control gate 21, memory cell 23, control gate 21 and memory cell 23, but also comprise raceway groove control gate 27, raceway groove control gate 27 is arranged in insulating barrier 25, and is electric good conductor.Wherein, memory cell 23 is nonconducting, and raceway groove control gate 27 can be Cu, W, and Al, the metals such as Ta, or be TiN
x, WN
x, CoSi
x, NiSi
x, TiSi
xdeng compound.Preferably, electron capture memory cell can be SONOS memory cell.
Can find out from Fig. 2 b, Fig. 2 c and Fig. 2 d, the present invention has a raceway groove 26 in physical significance, but there are two raceway grooves 261 and 262 in storage meaning, a virtual memory cell of the prior art is divided into two virtual memory cells, and namely a physical memory cell has four virtual memory cells.Wherein, raceway groove control gate 27 is for controlling the opening and closing of the first storage raceway groove 261 and the second storage raceway groove 262 that are positioned at raceway groove 26 both sides.
Raceway groove 26 is a passage in physical significance, by add control voltage on raceway groove control gate 27, can control the opening and closing of raceway groove 26 near the left and right sides of raceway groove control gate 27, raceway groove 26 in such physical significance is just divided into two raceway grooves in storage meaning, as shown in Figure 2 d, be respectively the first storage raceway groove 261 and the second storage raceway groove 262.So, a virtual memory cell (as shown in 131 or 132 in Fig. 1 c) of prior art is just divided into two virtual memory cells (as shown in Fig. 2 a 231 or 232), as shown in Figure 2 c, two virtual memory cells 231 are respectively the first memory cell 2311 and 2312, two virtual memory cells 232 of the second memory cell are respectively the 3rd memory cell 2321 and the 4th memory cell 2322.Therefore, from Fig. 2, can find out, it is four virtual memory cells in storage meaning that a physical memory cell 23 just has, and every virtual memory cell can be stored an information, and this physical memory cell 23 just can be used for storing four information.
Particularly, all there is respectively a raceway groove control gate 27 raceway groove 26 both sides in every physical significance.If the raceway groove control gate in a side applies high voltage, the raceway groove control gate of an other side applies low-voltage, like this, the raceway groove 26 in a physical significance is just divided into two raceway grooves in storage meaning, is respectively the first storage raceway groove 261 and the second storage raceway groove 262., corresponding two virtual memory cells of storage raceway groove, for example, the first storage corresponding the first memory cell 2311 of raceway groove 261 and the 3rd memory cell 2321, the second storage corresponding the second memory cell 2312 of raceway groove 262 and the 4th memory cell 2322.
If two virtual memory cells (the first memory cell 2311 and the 3rd memory cell 1321) of the first storage raceway groove 261 and its correspondence are operated and (are write, read, wipe) apply high voltage on the raceway groove control gate of the first storage raceway groove 261 that is near at hand, on the raceway groove control gate of contiguous the second storage raceway groove 262, apply low-voltage.If two virtual memory cells (the second memory cell 2312 and the 4th memory cell 1322) of the second storage raceway groove 262 and its correspondence are operated and (are write, read, wipe), be near at hand on the raceway groove control gate of the second storage raceway groove 262 and apply high voltage, on the raceway groove control gate of contiguous the first storage raceway groove 261, apply low-voltage.That is to say, by different raceway groove control gates being applied to the voltage of certain rule, control the operation of the memory cell of adjacent storage raceway groove and correspondence.
Wherein, the number of the raceway groove control gate 27 in each insulating barrier 25 is 1, each raceway groove control gate 27 for control an adjacent side raceway groove second storage raceway groove 262 opening and closing, and control adjacent opposite side raceway groove first storage raceway groove 261 opening and closing.
After adding raceway groove control gate 27, can be by add control voltage on raceway groove control gate, control the both sides of the raceway groove in a physical significance, the first storage raceway groove and the second storage raceway groove open and close respectively, such raceway groove has just been divided into two in storage meaning, and the virtual memory cell of a prior art definition just can be stored two information thus.Therefore, storage density uprises, and unit carrying cost reduces.
The structural representation of the electron capture memory cell of Fig. 3 second embodiment of the invention.As shown in Figure 3, the number of the raceway groove control gate 27 in each insulating barrier 25 is 2, one of them raceway groove control gate is used for the opening and closing of the second storage raceway groove 262 of the raceway groove of controlling an adjacent side, and another raceway groove control gate is used for the opening and closing of the first storage raceway groove 261 of the raceway groove of controlling adjacent opposite side.In this embodiment, except having two raceway groove control gates, other structure divisions and principle are identical with the first embodiment.
Particularly, all there are respectively two raceway groove control gates 27 raceway groove 26 both sides in every physical significance.If the most contiguous raceway groove control gate in a side applies high voltage, a most contiguous raceway groove control gate of an other side applies low-voltage, like this, article one, the raceway groove 26 in physical significance is just divided into two raceway grooves in storage meaning, is respectively the first storage raceway groove 261 and the second storage raceway groove 262., corresponding two virtual memory cells of storage raceway groove, for example, the first storage corresponding the first memory cell 2311 of raceway groove 261 and the 3rd memory cell 2321, the second storage corresponding the second memory cell 2312 of raceway groove 262 and the 4th memory cell 2322.
If two virtual memory cells (the first memory cell 2311 and the 3rd memory cell 1321) of the first storage raceway groove 261 and its correspondence are write, read, wipe, just on the raceway groove control gate of the most contiguous the first storage raceway groove 261, apply high voltage, on the raceway groove control gate of the most contiguous the second storage raceway groove 262, apply low-voltage.If two virtual memory cells (the second memory cell 2312 and the 4th memory cell 1322) of the second storage raceway groove 262 and its correspondence are write, read, wipe, just on the raceway groove control gate of the most contiguous the second storage raceway groove 262, apply high voltage, on the raceway groove control gate of the most contiguous the first storage raceway groove 261, apply low-voltage.That is to say, by different raceway groove control gates being applied to the voltage of certain rule, control the operation of the memory cell of adjacent storage raceway groove and correspondence.
After adding two raceway groove control gates 27, can be by add control voltage on raceway groove control gate, control the both sides of the raceway groove in a physical significance, the first storage raceway groove and the second storage raceway groove open and close respectively, such raceway groove has just been divided into two in storage meaning, and the virtual memory cell of a prior art definition just can be stored two information thus.Therefore, storage density uprises, and unit carrying cost reduces.
Fig. 4 is that the memory cell of electronic capture unit of the present invention is the structural representation disconnecting; Fig. 5 is that the memory cell of electronic capture unit of the present invention is continuous structural representation.As shown in Figure 4, the memory cell 23 of electron capture memory cell can be what disconnect.As shown in Figure 5, the memory cell 23 of electron capture memory cell can be continuous.The memory cell of the electron capture memory cell of first embodiment of the invention and the second embodiment can be continuous, can be also what disconnect.
These are only preferred embodiment of the present invention, in order to limit the present invention, within the spirit and principles in the present invention not all, any amendment of doing, be equal to replacement, improvement etc., within all should being included in protection scope of the present invention.
Claims (10)
1. an electron capture memory cell, comprises the insulating barrier (25) between raceway groove (26) and adjacent two described raceway grooves, it is characterized in that, also comprises:
Raceway groove control gate (27), is arranged in described insulating barrier (25), and is electric good conductor.
2. electron capture memory cell according to claim 1, it is characterized in that, described raceway groove control gate (27) is positioned at the described first storage raceway groove (261) of described raceway groove (26) both sides and the opening and closing of described the second storage raceway groove (262) for controlling.
3. electron capture memory cell according to claim 1, is characterized in that, the number of the described raceway groove control gate (27) in each described insulating barrier (25) is 1.
4. electron capture memory cell according to claim 3, is characterized in that,
Each described raceway groove control gate (27), for control an adjacent side raceway groove described second storage raceway groove (262) opening and closing, and control adjacent opposite side raceway groove described first storage raceway groove (261) opening and closing.
5. electron capture memory cell according to claim 1, is characterized in that, the number of the described raceway groove control gate (27) in each described insulating barrier (25) is 2.
6. electron capture memory cell according to claim 5, is characterized in that,
A described raceway groove control gate is used for the opening and closing of the described second storage raceway groove (262) of the raceway groove of controlling an adjacent side, and described in another, raceway groove control gate is used for the opening and closing of the described first storage raceway groove (261) of the raceway groove of controlling adjacent opposite side.
7. according to the electron capture memory cell described in claim 1-6 any one, it is characterized in that, described raceway groove control gate (27) is Cu, W, and Al, Ta metal, or be TiN
x, WN
x, CoSi
x, NiSi
x, TiSi
xcompound.
8. according to the electron capture memory cell described in claim 1-6 any one, it is characterized in that, the memory cell (23) of described electron capture memory cell is disconnection.
9. according to the electron capture memory cell described in claim 1-6 any one, it is characterized in that, the memory cell (23) of described electron capture memory cell is continuous.
10. according to the electron capture memory cell described in claim 1-6 any one, it is characterized in that, described electron capture memory cell is SONOS memory cell.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310164838.XA CN104143552B (en) | 2013-05-07 | 2013-05-07 | A kind of electronics trapping memory cells |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310164838.XA CN104143552B (en) | 2013-05-07 | 2013-05-07 | A kind of electronics trapping memory cells |
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| CN104143552A true CN104143552A (en) | 2014-11-12 |
| CN104143552B CN104143552B (en) | 2018-02-06 |
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| CN1943028A (en) * | 2004-02-24 | 2007-04-04 | 微米技术股份有限公司 | Vertical eeprom nrom memory devices |
| US20060197140A1 (en) * | 2005-03-04 | 2006-09-07 | Freescale Semiconductor, Inc. | Vertical transistor NVM with body contact structure and method |
| CN1945836A (en) * | 2005-05-20 | 2007-04-11 | 硅存储技术公司 | Bidirectional split gate nand flash memory structure/array, programming, erasing reading and manufacturing |
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Address after: Room 101, Floor 1-5, Building 8, Yard 9, Fenghao East Road, Haidian District, Beijing 100094 Patentee after: Zhaoyi Innovation Technology Group Co.,Ltd. Address before: 100083 12 Floors, Block A, Tiangong Building, Science and Technology University, 30 College Road, Haidian District, Beijing Patentee before: GIGADEVICE SEMICONDUCTOR(BEIJING) Inc. |