CN104253016A - Method for improving productive capacity of high-ohmic resistor - Google Patents
Method for improving productive capacity of high-ohmic resistor Download PDFInfo
- Publication number
- CN104253016A CN104253016A CN201310259759.7A CN201310259759A CN104253016A CN 104253016 A CN104253016 A CN 104253016A CN 201310259759 A CN201310259759 A CN 201310259759A CN 104253016 A CN104253016 A CN 104253016A
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- CN
- China
- Prior art keywords
- metering
- polysilicon layer
- high resistant
- cleaning
- polycrystalline silicon
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/20—Resistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
Abstract
The invention provides a method for improving productive capacity of a high-ohmic resistor. The method comprises the steps of continuously cleaning the upper surface of a first polycrystalline silicon layer with acid liquid for preset time after the first polycrystalline silicon layer is prepared in a process of preparing the high-ohmic resistor in a polycrystalline silicon deposition furnace tube, preparing a capacitor intermediate dielectric layer on the cleaned upper surface of the first polycrystalline silicon layer, preparing a second polycrystalline silicon layer on the capacitor intermediate dielectric layer, and injecting a second metering impurity element on the second polycrystalline silicon layer, wherein second metering is more than first metering, and the first metering is metering of an impurity element to be injected on the second polycrystalline silicon layer in a process of preparing a high-ohmic resistor with the same resistance, without cleaning the upper surface of the first polycrystalline silicon layer. According to the method, the productive capacity of the high-ohmic resistor prepared by the polycrystalline silicon deposition furnace tube is improved by cleaning with the acid liquid before preparing the capacitor intermediate dielectric layer and subsequently adding a generation technology of impurity element injection metering.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly relate to a kind of method improving high resistant production capacity.
Background technology
At complementary metal oxide semiconductors (CMOS) (ComplementaryMetalOxideSemiconductor; Be called for short: CMOS) in technique, high resistant is generally applied polysilicon and is made in deposit boiler tube, and deposit boiler tube comprises multiple brilliant boat for making high resistant.Due to reasons such as polysilicon deposition furnace tube temperature uniformity and airflow homogeneities, the rete being in the wafer growth of the brilliant boat of fire door is thicker, and in stove and stove tail thinner, so just cause in a long body of heater, and the boat position of not all can meet production requirement.
Such as, when application comprises at least 6 deposit boiler tubes placing the brilliant boat of wafers to make the high resistant of 1K ohm, operation one stove only has No. 2 boat potential energies to meet production requirement, fluctuated within the scope of 800-1200 ohm by the resistance testing the high resistant that known No. 2 boat positions are produced, this is specification line, exceeds this range product and is considered as defective.Generally, the high resistant that other boat position makes except No. 2 boat positions easily exceeds prescribed limit, does not meet and generates requirement, limit production capacity.
Summary of the invention
For the defect of prior art, the invention provides a kind of method improving high resistant production capacity, comprising:
Prepare in polysilicon deposition boiler tube in the process of high resistant, after the silicon chip of each boat position has prepared the first polysilicon layer, the upper surface of application acidic liquid to the first polysilicon layer on each boat position carries out the cleaning of lasting Preset Time;
Electric capacity middle dielectric layer is prepared at the upper surface of the first polysilicon layer through cleaning;
Described electric capacity middle dielectric layer prepares the second polysilicon layer, and on described second polysilicon layer, injects the impurity element of the second metering; Described second metering is more than the first metering, and described first measures as not cleaning the upper surface of described first polysilicon layer and prepare in the process of the high resistant of similar resistance, needs the metering of the impurity element injected on described second polysilicon layer.
The method of raising high resistant production capacity provided by the invention, by increasing the cleaning of acidic liquid before preparing electric capacity middle dielectric layer, and at the generating process that the injection of follow-up increase impurity element is measured, provides polysilicon deposition boiler tube to prepare the production capacity of high resistant.
Accompanying drawing explanation
Fig. 1 is the embodiment of the method schematic flow sheet that the present invention improves high resistant production capacity;
Fig. 2 is that the embodiment of the present invention is through cleaning and the high resistant resistance contrast schematic diagram without cleaning;
Fig. 3 is embodiment of the present invention electric capacity uniformity contrast schematic diagram;
Fig. 4 is the embodiment of the present invention No. 2 boat position high resistant resistance fluctuation schematic diagrames;
Fig. 5 is the embodiment of the present invention No. 3 boat position high resistant resistance fluctuation schematic diagrames.
Embodiment
When prior art application polysilicon deposition boiler tube prepares high resistant, because of the impact of the factor such as temperature homogeneity and airflow homogeneity, operation one stove only has the high resistant of a boat position to meet production requirement.Test shows that the adjacent each boat interdigit of high resistant making 1K ohm differs 50 ohm, only has the high resistant of No. 2 boat positions to meet the demands, because which limit the high resistant production capacity of polysilicon deposition boiler tube.The present invention is directed to the defect of prior art, provide a solution to transform semiconductor device technological process, first carry out the cleaning of acid solution, and inject at follow-up increase high resistant the high resistant production capacity that metering improves polysilicon deposition boiler tube.
Fig. 1 is the embodiment of the method schematic flow sheet that the present invention improves high resistant production capacity, and the method improves the technological process of production that prior art application polysilicon deposition boiler tube prepares high resistant, and particularly as shown in Figure 1, the method comprises:
Step 101, prepare in the process of high resistant in polysilicon deposition boiler tube, after the silicon chip of each boat position has prepared the first polysilicon layer, the upper surface of application acidic liquid to the first polysilicon layer on each boat position carries out the cleaning of lasting Preset Time;
Prepare in the process of high resistant in application polysilicon deposition boiler tube, first in deposit boiler tube, each boat position arranges suitable silicon chip, and carry out an oxygen, then on silicon chip, prepare the first polysilicon layer.Above preparation flow is identical with the preparation flow of prior art, repeats no more herein.
In the embodiment of the present invention, after preparation completes the first polysilicon layer, directly do not prepare electric capacity middle dielectric layer, but first the upper surface of the first polysilicon layer on each boat position is cleaned, specifically can apply the cleaning that acidic liquid carries out lasting Preset Time.Preferably, acidic liquid can be hydrofluoric acid.The embodiment of the present invention is cleaned by the upper surface of application hydrofluoric acid to the first polysilicon layer, can by more smooth for the upper surface of the first polysilicon layer, then the electric capacity middle dielectric layer prepared thereon also will be comparatively smooth, avoid the high resistant generating out to occur electric capacity middle dielectric layer uneven distribution, even occur the defect in dew hole.
To further, the duration of the cleaning that application acidic liquid carries out, can set according to actual conditions and empirical value.
Step 102, prepare electric capacity middle dielectric layer at the upper surface of the first polysilicon layer through cleaning;
Application acidic liquid carries out after cleaning completes, continuing to prepare electric capacity middle dielectric layer at the upper surface of the first polysilicon layer through cleaning to the first polysilicon layer.The flow process preparing electric capacity middle dielectric layer is same as the prior art, repeats no more herein.
Step 103, on described electric capacity middle dielectric layer, prepare the second polysilicon layer, and on described second polysilicon layer, inject the impurity element of the second metering; Described second metering is more than the first metering, and described first measures as not cleaning the upper surface of described first polysilicon layer and prepare in the process of the high resistant of similar resistance, needs the metering of the impurity element injected on described second polysilicon layer.
After having prepared electric capacity middle dielectric layer, continue to prepare the second polysilicon layer on electric capacity middle dielectric layer, and on the second polysilicon layer, inject the impurity element such as phosphonium ion of the second metering.
Should be noted that, after preparation first polysilicon layer in the prior art, directly prepare electric capacity middle dielectric layer, and continue in the technological process of preparation second polysilicon layer, also implanted dopant element on the second polysilicon layer is needed, such as needing to inject metering according to the resistance of the high resistant that will produce is the first metering, and the impurity element namely injecting the first metering in prior art on the second polysilicon layer can meet the production requirement of high resistant resistance.
Due in the embodiment of the present invention, will apply hydrofluoric acid and clean the first polysilicon layer before preparing electric capacity middle dielectric layer, the resistance of the high resistant therefore prepared causing the resistance value ratio of high resistant entirety not carry out hydrofluoric acid clean wants high.Therefore, in order to meet production requirement, the resistance of high resistant entirety be lowered, therefore in the embodiment of the present invention in the process to implanted dopant element on the second polysilicon layer, increase and inject metering and reduce the resistance of high resistant entirety.Because the first metering is prepared in the process of the high resistant of similar resistance for not cleaning the upper surface of the first polysilicon layer, need the metering of the impurity element injected on the second polysilicon layer, second metering of therefore injecting in the embodiment of the present invention is more than the first metering.
By increasing the injection metering of impurity element, the resistance raised before making declines, thus meets production requirement; And further, by the high resistant having at least two boat positions productions being met production requirement in above-mentioned technological process polysilicon deposition boiler tube, thus the production capacity of the high resistant improved.
Below in conjunction with an instantiation, introduce the method for the raising high resistant production capacity that the embodiment of the present invention provides in detail.
The embodiment of the present invention needs production resistance to be the high resistant of 1K ohm.Idiographic flow comprises: each boat position in polysilicon deposition boiler tube arranges silicon chip, silicon chip is prepared the first polysilicon layer.
Fig. 2 is that the embodiment of the present invention is through cleaning and the high resistant resistance contrast schematic diagram without cleaning, (in figure, Y-axis represents resistance as shown in Figure 2, left figure is the schematic diagram through cleaning, right figure is the schematic diagram without cleaning), before preparing electric capacity middle dielectric layer, add hydrofluoric acid clean 120 seconds (or longer time), high resistant entirety can be made to exceed 100 ohm.Cleaning is prepared electric capacity middle dielectric layer, and prepare the second polysilicon layer on electric capacity middle dielectric layer after introducing on the first polysilicon layer, then injects phosphonium ion to the second polysilicon layer.Fig. 3 is embodiment of the present invention electric capacity uniformity contrast schematic diagram, (in figure, Y-axis represents electric capacity as shown in Figure 3, left figure is schematic diagram of the present invention, right figure is the schematic diagram of prior art), the embodiment of the present invention strengthens the implantation dosage of 10% on the whole compared to prior art, concentration due to phosphonium ion becomes large, and electric capacity uniformity can improve.Increase hydrofluoric acid clean 120 seconds electric capacity uniformities as seen by upper figure can improve, high resistant can be higher 100 ohm than not doing the high resistant cleaned, so 1K high resistant implantation dosage is become 2.2E15 from 2.1E15 every square centimeter, because concentration becomes large so high resistant can become even.Fig. 4 is the embodiment of the present invention No. 2 boat position high resistant resistance fluctuation schematic diagrames, Fig. 5 is the embodiment of the present invention No. 3 boat position high resistant resistance fluctuation schematic diagrames, from Fig. 4 and Fig. 5, the high resistant resistance fluctuation of No. 2 and No. 3 boat positions in acceptability limit, therefore can double high resistant operation production capacity.
Last it is noted that above each embodiment is only in order to illustrate technical scheme of the present invention, be not intended to limit; Although with reference to foregoing embodiments to invention has been detailed description, those of ordinary skill in the art is to be understood that: it still can be modified to the technical scheme described in foregoing embodiments, or carries out equivalent replacement to wherein some or all of technical characteristic; And these amendments or replacement, do not make the essence of appropriate technical solution depart from the scope of various embodiments of the present invention technical scheme.
Claims (5)
1. improve a method for high resistant production capacity, it is characterized in that, comprising:
Prepare in polysilicon deposition boiler tube in the process of high resistant, after the silicon chip of each boat position has prepared the first polysilicon layer, the upper surface of application acidic liquid to the first polysilicon layer on each boat position carries out the cleaning of lasting Preset Time;
Electric capacity middle dielectric layer is prepared at the upper surface of the first polysilicon layer through cleaning;
Described electric capacity middle dielectric layer prepares the second polysilicon layer, and on described second polysilicon layer, injects the impurity element of the second metering; Described second metering is more than the first metering, and described first measures as not cleaning the upper surface of described first polysilicon layer and prepare in the process of the high resistant of similar resistance, needs the metering of the impurity element injected on described second polysilicon layer.
2. method according to claim 1, is characterized in that, described acidic liquid is hydrofluoric acid.
3. method according to claim 1 and 2, is characterized in that, described Preset Time is more than or equal to 120 seconds.
4. method according to claim 1 and 2, is characterized in that, described second metering is than the first metering many 10%.
5. method according to claim 1 and 2, is characterized in that, described impurity element is phosphonium ion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310259759.7A CN104253016B (en) | 2013-06-26 | 2013-06-26 | The method for improving high resistant production capacity |
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| CN201310259759.7A CN104253016B (en) | 2013-06-26 | 2013-06-26 | The method for improving high resistant production capacity |
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| CN104253016A true CN104253016A (en) | 2014-12-31 |
| CN104253016B CN104253016B (en) | 2017-04-05 |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6010942A (en) * | 1999-05-26 | 2000-01-04 | Vanguard International Semiconductor Corporation | Post chemical mechanical polishing, clean procedure, used for fabrication of a crown shaped capacitor structure |
| US20030040162A1 (en) * | 2001-08-24 | 2003-02-27 | Hynix Semiconductor Inc. | Method for fabricating a capacitor |
| CN102468127A (en) * | 2010-11-03 | 2012-05-23 | 北大方正集团有限公司 | Method for cleaning wafer in double polycrystalline capacitance process |
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2013
- 2013-06-26 CN CN201310259759.7A patent/CN104253016B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6010942A (en) * | 1999-05-26 | 2000-01-04 | Vanguard International Semiconductor Corporation | Post chemical mechanical polishing, clean procedure, used for fabrication of a crown shaped capacitor structure |
| US20030040162A1 (en) * | 2001-08-24 | 2003-02-27 | Hynix Semiconductor Inc. | Method for fabricating a capacitor |
| CN102468127A (en) * | 2010-11-03 | 2012-05-23 | 北大方正集团有限公司 | Method for cleaning wafer in double polycrystalline capacitance process |
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| CN104253016B (en) | 2017-04-05 |
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Effective date of registration: 20220721 Address after: 518116 founder Microelectronics Industrial Park, No. 5, Baolong seventh Road, Baolong Industrial City, Longgang District, Shenzhen, Guangdong Province Patentee after: SHENZHEN FOUNDER MICROELECTRONICS Co.,Ltd. Address before: 100871, Beijing, Haidian District, Cheng Fu Road, No. 298, Zhongguancun Fangzheng building, 9 floor Patentee before: PEKING UNIVERSITY FOUNDER GROUP Co.,Ltd. Patentee before: SHENZHEN FOUNDER MICROELECTRONICS Co.,Ltd. |